 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| user?s manual all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various m eans, including the renesas electronics corp. website (http://www.renesas.com). 78k0/kx2 user?s manual: hardware rev.4.01 jul 2010 8 8-bit single-chip microcontrollers www.renesas.com
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, et c., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semi conductor devices must be stored and transported in an anti-static container, static shielding bag or conducti ve material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch o ff the external power supply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device. how to use this manual readers this manual is intended for user engineers w ho wish to understand the f unctions of the 78k0/kx2 microcontrollers and design and develop applic ation systems and programs for these devices. the target products are as follows. conventional-specification produc ts expanded-specification products 78k0/kb2 pd78f0500, 78f0501, 78f0502, 78f0503, 78f0503d, 78f0500(a), 78f0501(a), 78f0502(a), 78f0503(a), 78f0500(a2), 78f0501(a2), 78f0502(a2), 78f0503(a2) pd78f0500a, 78f0501a, 78f0502a, 78f0503a, 78f0503da, 78f0500a(a), 78f0501a(a), 78f0502a(a), 78f0503a(a), 78f0500a(a2), 78f0501a(a2), 78f0502a(a2), 78f0503a(a2) 78k0/kc2 pd78f0511, 78f0512, 78f0513, 78f0514, 78f0515, 78f0513d, 78f0515d, 78f0511(a), 78f0512(a), 78f0513(a), 78f0514(a), 78f0515(a), 78f0511(a2), 78f0512(a2), 78f0513(a2), 78f0514(a2), 78f0515(a2) pd78f0511a, 78f0512a, 78f0513a, 78f0514a, 78f0515a, 78f0513da, 78f0515da, 78f0511a(a), 78f0512a(a), 78f0513a(a), 78f0514a(a), 78f0515a(a), 78f0511a(a2), 78f0512a(a2), 78f0513a(a2), 78f0514a(a2), 78f0515a(a2) 78k0/kd2 pd78f0521, 78f0522, 78f0523, 78f0524, 78f0525, 78f0526, 78f0527, 78f0527d, 78f0521(a), 78f0522(a), 78f0523(a), 78f0524(a), 78f0525(a), 78f0526(a), 78f0527(a), 78f0521(a2), 78f0522(a2), 78f0523(a2), 78f0524(a2), 78f0525(a2), 78f0526(a2), 78f0527(a2) pd78f0521a, 78f0522a, 78f0523a, 78f0524a, 78f0525a, 78f0526a, 78f0527a, 78f0527da, 78f0521a(a), 78f0522a(a), 78f0523a(a), 78f0524a(a), 78f0525a(a), 78f0526a(a), 78f0527a(a), 78f0521a(a2), 78f0522a(a2), 78f0523a(a2), 78f0524a(a2), 78f0525a(a2), 78f0526a(a2), 78f0527a(a2) 78k0/ke2 pd78f0531, 78f0532, 78f0533, 78f0534, 78f0535, 78f0536, 78f0537, 78f0537d, 78f0531(a), 78f0532(a), 78f0533(a), 78f0534(a), 78f0535(a), 78f0536(a), 78f0537(a), 78f0531(a2), 78f0532(a2), 78f0533(a2), 78f0534(a2), 78f0535(a2), 78f0536(a2), 78f0537(a2) pd78f0531a, 78f0532a, 78f0533a, 78f0534a, 78f0535a, 78f0536a, 78f0537a, 78f0537da, 78f0531a(a), 78f0532a(a), 78f0533a(a), 78f0534a(a), 78f0535a(a), 78f0536a(a), 78f0537a(a), 78f0531a(a2), 78f0532a(a2), 78f0533a(a2), 78f0534a(a2), 78f0535a(a2), 78f0536a(a2), 78f0537a(a2) 78k0/kf2 pd78f0544, 78f0545, 78f0546, 78f0547, 78f0547d, 78f0544(a), 78f0545(a), 78f0546(a), 78f0547(a), 78f0544(a2), 78f0545(a2), 78f0546(a2), 78f0547(a2) pd78f0544a, 78f0545a, 78f0546a, 78f0547a, 78f0547da, 78f0544a(a), 78f0545a(a), 78f0546a(a), 78f0547a(a), 78f0544a(a2), 78f0545a(a2), 78f0546a(a2), 78f0547a(a2) differences between c onventional-specification products a nd expanded-specification products the differences between the convent ional-specification products ( pd78f05xx, 78f05xxd) and expanded- specification products ( pd78f05xxa, 78f05xxda) of the 78k0/kx2 microcontrollers are described below. ? a/d conversion time ? x1 oscillator characteristics ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, an d external main system clock input lo w-level width (ac characteristics) ? the number of flash memory rewrites and retention time ? processing time of the self programming library ? interrupt response time of the self programming library for details, see 1.1 differences between conventi onal-specification products ( pd78f05xx, 78f05xxd) and expanded-specification products ( pd78f05xxa, 78f05xxda). purpose this manual is intended to give users an u nderstanding of the functions described in the organization below. organization the manual for the 78k0/kx2 microcontrollers is separated into two parts: this manual and the instructions edition (comm on to the 78k0 microcontrollers). 78k0/kx2 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this m anual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? when using this manual as the manual for (a) grade products and (a2) grade products of the 78k0/kx2 microcontrollers: only the quality grade differs between standa rd products and (a), (a2) grade products. read the part number as follows. ? pd78f05xx pd78f05xx(a), 78f05xx(a2) ? pd78f05xxa pd78f05xxa(a), 78f05xxa(a2) ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ? ? to know details of the 78k 0 microcontroller instructions: refer to the separate document 78k/0 series instructions user?s manual (u12326e) . conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publ ication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/kx2 user?s manual this manual 78k/0 series instructions user?s manual u12326e 78k0/kx2 flash memory programming (pr ogrammer) application note u17739e 78k0/kx2 flash memory self programming user?s manual u17516e 78k0/kx2 eeprom tm emulation application note u17517e 78k0 microcontrollers self programmi ng library type01 user?s manual u18274e 78k0 microcontrollers eeprom emulation library type01 user?s manual u18275e documents related to fl ash memory programming document name document no. pg-fp5 flash memory programmer user?s manual u18865e pg-fp4 flash memory programmer user?s manual u15260e documents related to devel opment tools (hardware) document name document no. qb-78k0kx2 in-circuit emulator user?s manual u17341e qb-mini2 on-chip debug emulator with pr ogramming function user?s manual u18371e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. documents related to devel opment tools (software) document name document no. operation u17199e language u17198e ra78k0 ver.3.80 assembler package user?s manual note 1 structured assembly language u17197e 78k0 assembler package ra78k0 ver.4.01 operating precautions (notification document) note 1 zud-cd-07-0181-e operation u17201e cc78k0 ver.3.70 c compiler user?s manual note 2 language u17200e 78k0 c compiler cc78k0 ver. 4.00 operating precautions (notification document) note 2 zud-cd-07-0103-e operation u18601e sm+ system simulator user?s manual user open interface u18212e id78k0-qb ver.2.94 integrated debugger user?s manual operation u18330e id78k0-qb ver.3.00 integrated debugger user?s manual operation u18492e pm plus ver.5.20 note 3 user?s manual u16934e pm+ ver.6.30 note 4 user?s manual u18416e notes 1. this document is installed into the pc together with the tool when installing ra78k0 ver. 4.01. for descriptions not included in ?78k0 assembler package ra78 k0 ver. 4.01 operating precautions?, refer to the user?s manual of ra78k0 ver. 3.80. 2. this document is installed into t he pc together with the tool when in stalling cc78k0 ver. 4.00. for descriptions not included in ?78k0 c compiler cc78k0 ve r. 4.00 operating precautions ?, refer to the user?s manual of cc78k0 ver. 3.70. 3. pm plus ver. 5.20 is the integrated developm ent environment included with ra78k0 ver. 3.80. 4. pm+ ver. 6.30 is the integrated dev elopment environment included with ra 78k0 ver. 4.01. software tool (assembler, c compiler, debugger, and simulator) products of different versions can be managed. other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (http://www2.rene sas.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. all trademarks and registered trademarks ar e the property of their respective owners. eeprom is a trademark of rene sas electronics corporation. windows is a registered trademark or trademark of microsof t corporation in the united states and/or other countries. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. r01uh0008ej0401 rev.4.01 9 jul 15, 2010 contents chapter 1 outline........................................................................................................... .................. 19 1.1 differences between conventional-specification products ( pd78f05xx and 78f05xxd) and expanded-specification products ( pd78f05xxa and 78f05xxda) ..................................... 19 1.1.1 a/d c onversion time ..................................................................................................... ................... 20 1.1.2 x1 oscillator characteristics........................................................................................... .................. 20 1.1.3 time instruction cycle, peripheral hardware cl ock frequency, external main system clock frequency, external main system clock input high-level width, and external ma in system clock input low-level width (ac char acterist ics) .................................................................................................... ........... 21 1.1.4 number of flash memory rewrites and retentio n time ...................................................................... 22 1.1.5 processing time for self programmi ng libr ary ............................................................................ ...... 23 1.1.6 interrupt response time for self progr amming li brary .................................................................... ... 29 1.2 features.................................................................................................................. ....................... 33 1.3 applications .............................................................................................................. .................... 34 1.4 ordering information...................................................................................................... .............. 35 1.5.1 78k 0/kb2 ................................................................................................................ ........................ 42 1.5.2 78k 0/kc2................................................................................................................ ........................ 44 1.5.3 78k 0/kd2................................................................................................................ ........................ 47 1.5.4 78k 0/ke2 ................................................................................................................ ........................ 48 1.5.5 78k 0/kf2 ................................................................................................................ ........................ 50 1.6 pin identification........................................................................................................ ................... 51 1.7 block diagram ............................................................................................................. ................. 52 1.7.1 78k 0/kb2 ................................................................................................................ ........................ 52 1.7.2 78k 0/kc2................................................................................................................ ........................ 53 1.7.3 78k 0/kd2................................................................................................................ ........................ 54 1.7.4 78k 0/ke2 ................................................................................................................ ........................ 55 1.7.5 78k 0/kf2 ................................................................................................................ ........................ 56 1.8 outline of functions...................................................................................................... ............... 57 chapter 2 pin functions .................................................................................................... ........... 60 2.1 pin function list ......................................................................................................... ................. 60 2.1.1 78k 0/kb2 ................................................................................................................ ........................ 61 2.1.2 78k 0/kc2................................................................................................................ ........................ 64 2.1.3 78k 0/kd2................................................................................................................ ........................ 67 2.1.4 78k 0/ke2 ................................................................................................................ ........................ 70 2.1.5 78k 0/kf2 ................................................................................................................ ........................ 74 2.2 description of pin func tions .............................................................................................. ........ 78 2.2.1 p00 to p06 (por t 0) ..................................................................................................... ..................... 78 2.2.2 p10 to p17 (por t 1) ..................................................................................................... ..................... 79 2.2.3 p20 to p27 (por t 2) ..................................................................................................... ..................... 81 2.2.4 p30 to p33 (por t 3) ..................................................................................................... ..................... 82 2.2.5 p40 to p47 (por t 4) ..................................................................................................... ..................... 83 2.2.6 p50 to p57 (por t 5) ..................................................................................................... ..................... 84 2.2.7 p60 to p67 (por t 6) ..................................................................................................... ..................... 84 2.2.8 p70 to p77 (por t 7) ..................................................................................................... ..................... 85 2.2.9 p120 to p124 (por t 12) .................................................................................................. .................. 86 r01uh0008ej0401 rev.4.01 10 jul 15, 2010 2.2.10 p130 (por t 13) ......................................................................................................... ...................... 87 2.2.11 p140 to p145 ( port 14) ................................................................................................. ................. 88 2.2.12 av ref , av ss , v dd , ev dd , v ss , ev ss ............................................................................................... 89 2.2.13 reset .................................................................................................................. ........................ 90 2.2.14 regc................................................................................................................... ......................... 90 2.2.15 flmd0 .................................................................................................................. ........................ 90 2.3 pin i/o circuits and recomme nded connection of unu sed pins ........................................... 91 chapter 3 cpu architecture ................................................................................................. ..... 96 3.1 memory space .............................................................................................................. ................ 96 3.1.1 internal progr am memory space ........................................................................................... ........ 111 3.1.2 memory bank (products whose fl ash memory is at least 96 kb only) ........................................... 113 3.1.3 internal dat a memory space.............................................................................................. ............ 114 3.1.4 special function register (sfr) area .................................................................................... ......... 116 3.1.5 data me mory addr essing .................................................................................................. ............ 116 3.2 processor registers....................................................................................................... ............ 125 3.2.1 contro l regist ers ....................................................................................................... ..................... 125 3.2.2 general-pur pose registers............................................................................................... .............. 129 3.2.3 special functi on register s (sfrs) ....................................................................................... ........... 130 3.3 instruction address addressi ng............................................................................................ ... 136 3.3.1 relati ve addre ssing..................................................................................................... .................. 136 3.3.2 immedi ate addres sing .................................................................................................... ............... 137 3.3.3 table indi rect addr essing ............................................................................................... ............... 138 3.3.4 regist er addre ssing ..................................................................................................... ................. 139 3.4 operand address addressi ng ................................................................................................ .. 139 3.4.1 impli ed addre ssing ...................................................................................................... .................. 139 3.4.2 regist er addre ssing ..................................................................................................... ................. 140 3.4.3 direct addre ssing ....................................................................................................... ................... 141 3.4.4 short di rect addr essing ................................................................................................. ................ 142 3.4.5 special function register (sfr ) addres sing .............................................................................. ..... 143 3.4.6 register i ndirect addr essi ng............................................................................................ .............. 144 3.4.7 based addre ssing........................................................................................................ .................. 145 3.4.8 based in dexed addr essing ................................................................................................ ............ 146 3.4.9 stack addre ssing........................................................................................................ ................... 147 chapter 4 memory bank select function (products whose flash memory is at least 96 kb only)....................................................................................................... 148 4.1 memory bank ............................................................................................................... ............... 148 4.2 difference in re presentation of memory space ................. .................................................... 149 4.3 memory bank select register (bank) ..................................................................................... 150 4.4 selecting memory bank ..................................................................................................... ........ 151 4.4.1 referencing val ues between me mory banks................................................................................. 151 4.4.2 branching instruct ion between me mory banks.............................................................................. 153 4.4.3 subroutine call bet ween memory banks.................................................................................... .... 155 4.4.4 instruction branch to bank area by inte rrupt ............................................................................ ...... 157 r01uh0008ej0401 rev.4.01 11 jul 15, 2010 chapter 5 port functions ................................................................................................... ...... 159 5.1 port functions ............................................................................................................ ................ 159 5.2 port configuration..................................................... ................................................... .............. 163 5.2.1 po rt 0.................................................................................................................. ........................... 164 5.2.2 po rt 1.................................................................................................................. ........................... 175 5.2.3 po rt 2.................................................................................................................. ........................... 181 5.2.4 po rt 3.................................................................................................................. ........................... 183 5.2.5 po rt 4.................................................................................................................. ........................... 186 5.2.6 po rt 5.................................................................................................................. ........................... 188 5.2.7 po rt 6.................................................................................................................. ........................... 189 5.2.8 po rt 7.................................................................................................................. ........................... 194 5.2.9 po rt 12................................................................................................................. .......................... 196 5.2.10 po rt 13................................................................................................................ ......................... 199 5.2.11 po rt 14................................................................................................................ ......................... 200 5.3 registers controlling port function ....................... ................................................................ . 204 5.4 port function operations .................................................................................................. ........ 221 5.4.1 writi ng to i/o port ..................................................................................................... ..................... 221 5.4.2 reading from i/o port................................................................................................... ................. 221 5.4.3 operatio ns on i/o port.................................................................................................. ................. 221 5.5 settings of port mode register and output latch when using alternate function........... 221 5.6 cautions on 1-bit manipulation instruction for port register n (p n).................................... 224 chapter 6 clock generator .................................................................................................. .. 225 6.1 functions of clock generator.............................................................................................. ..... 225 6.2 configuration of clock gene rator .......................................................................................... .. 226 6.3 registers controlling clock generator................... ................................................................. 2 29 6.4 system clock oscillator ................................................................................................... ......... 240 6.4.1 x1 oscill ator........................................................................................................... ........................ 240 6.4.2 xt1 oscilla tor .......................................................................................................... ...................... 240 6.4.3 when subsystem clock is not us ed ........................................................................................ ....... 243 6.4.4 internal hi gh-speed os cillator .......................................................................................... .............. 243 6.4.5 internal lo w-speed os cillator........................................................................................... ............... 243 6.4.6 pr escaler ............................................................................................................... ........................ 243 6.5 clock generator operation ................................................................................................. ...... 244 6.6 controlling clock......................................................................................................... ............... 248 6.6.1 example of controlli ng high-speed syst em clock .......................................................................... . 248 6.6.2 example of controlling intern al high-speed osc illation cl ock.......................................................... 25 1 6.6.3 example of cont rolling subsyst em clock.................................................................................. ...... 254 6.6.4 example of controlling intern al low-speed osci llation cl ock ........................................................... 25 6 6.6.5 clocks supplied to cp u and peripheral hardwar e ......................................................................... 2 57 6.6.6 cpu clock stat us transiti on diagr am..................................................................................... ......... 258 6.6.7 condition before changing cpu clock and processi ng after changing cpu cl ock ........................ 265 6.6.8 time required for switchover of cpu clock and main system cl ock .............................................. 266 6.6.9 conditions before clock osc illation is stopp ed .......................................................................... ..... 268 6.6.10 peripheral hardw are and sour ce clocks .................................................................................. .... 269 r01uh0008ej0401 rev.4.01 12 jul 15, 2010 chapter 7 16-bit timer/event counters 00 and 01......................................................... 270 7.1 functions of 16-bit timer/even t counters 00 and 01..................... ........................................ 270 7.2 configuration of 16-bit time r/event counters 00 and 01 .............. ........................................ 271 7.3 registers controlling 16-bit ti mer/event counters 00 and 01......... ..................................... 277 7.4 operation of 16-bit timer/even t counters 00 and 01 ..................... ........................................ 289 7.4.1 interval timer oper ation................................................................................................ .................. 289 7.4.2 square-wave output op eration ............................................................................................ .......... 292 7.4.3 external event counter operatio n ........................................................................................ .......... 295 7.4.4 operation in clear & start mode entered by ti 00n pin valid ed ge input ......................................... 299 7.4.5 free-runni ng timer oper ation............................................................................................ ............. 312 7.4.6 ppg out put operat ion.................................................................................................... ................ 321 7.4.7 one-shot pul se output operatio n ......................................................................................... .......... 325 7.4.8 pulse width m easurement operatio n ....................................................................................... ...... 330 7.5 special use of tm0n....................................................................................................... ............ 338 7.5.1 rewriting cr01n during tm0n operatio n ................................................................................... ... 338 7.5.2 setting l vs0n and lvr0n ................................................................................................. ........... 338 7.6 cautions for 16-bit timer/e vent counters 00 and 01 ..................... ........................................ 340 chapter 8 8-bit timer/event counters 50 and 51........................................................... 345 8.1 functions of 8-bit timer/event counters 50 and 51............................................................... 345 8.2 configuration of 8-bit timer/ event counters 50 and 51 ........................................................ 345 8.3 registers controlling 8-bit time r/event counters 50 and 51................................................ 348 8.4 operations of 8-bit timer/e vent counters 50 and 51 ..................... ........................................ 354 8.4.1 operation as interval timer ............................................................................................. ............... 354 8.4.2 operation as ex ternal event count er ..................................................................................... ........ 356 8.4.3 square-wave output op eration ............................................................................................ .......... 357 8.4.4 pwm out put operat ion.................................................................................................... ............... 358 8.5 cautions for 8-bit timer/even t counters 50 and 51 ............................................................... 362 chapter 9 8-bit timers h0 and h1........................................................................................ ... 363 9.1 functions of 8-bit timers h0 and h1 ............... ........................................................................ 363 9.2 configuration of 8-bit timers h0 and h1 ......... ........................................................................ 36 3 9.3 registers controlling 8-bit timers h0 and h1 ....... ................................................................. 367 9.4 operation of 8-bit timers h0 and h1................ ....................................................................... . 373 9.4.1 operation as interv al timer/squar e-wave output .......................................................................... .. 373 9.4.2 operatio n as pw m out put ................................................................................................. ............ 376 9.4.3 carrier generator operat ion (8-bit ti mer h1 only)....................................................................... .... 382 r01uh0008ej0401 rev.4.01 13 jul 15, 2010 chapter 10 watch timer..................................................................................................... ......... 389 10.1 functions of watch timer ................................................................................................. ...... 389 10.2 configuration of watch timer............................................................................................. .... 391 10.3 register controlling watch timer ......................................................................................... . 391 10.4 watch timer operations ................................................................................................... ....... 394 10.4.1 watch ti mer operat ion .................................................................................................. ............... 394 10.4.2 interval timer oper ation............................................................................................... ................. 394 10.5 cautions for watch timer................................................................................................. ....... 395 chapter 11 watchdog timer .................................................................................................. ... 396 11.1 functions of watchdog timer.............................................................................................. ... 396 11.2 configuration of watchdog ti mer .......................................................................................... 397 11.3 register controlling watchdog timer...................... .............................................................. 39 8 11.4 operation of watchdog timer.............................................................................................. ... 399 11.4.1 controlling oper ation of wa tchdog ti mer ................................................................................ ...... 399 11.4.2 setting overflow time of wa tchdog ti mer................................................................................ ...... 400 11.4.3 setting window open pe riod of watc hdog ti mer ........................................................................... 401 chapter 12 clock output/buzzer output controller............................................... 403 12.1 functions of clock output/bu zzer output controller .................. ........................................ 403 12.2 configuration of clock output /buzzer output controller.................................................... 404 12.3 registers controlling clock output/buzzer output controller ........................................... 404 12.4 operations of clock output/b uzzer output controller ........................................................ 408 12.4.1 operation as clock output.............................................................................................. .............. 408 12.4.2 operation as buzzer output ............................................................................................. ............ 408 chapter 13 a/d converter ................................................................................................... ...... 409 13.1 function of a/d converter................................................................................................ ....... 409 13.2 configuration of a/d converter ........................................................................................... ... 410 13.3 registers used in a/d converter.......................................................................................... .. 412 13.4 a/d converter operations ............................................. .................................................... ...... 421 13.4.1 basic operations of a/d c onverter ...................................................................................... ......... 421 13.4.2 input voltage and conversion results ................................................................................... ........ 422 13.4.3 a/d converte r operati on mode ........................................................................................... ......... 424 13.5 how to read a/d converter characteristics tabl e............................................................... 426 13.6 cautions for a/d converter ............................................................................................... ...... 428 chapter 14 serial interface uart0 ...................................................................................... 432 14.1 functions of serial interface uart0 ..................... ................................................................. 432 14.2 configuration of serial inte rface uart0................................................................................ 43 3 14.3 registers controlling serial interface uart0...... ................................................................. 436 14.4 operation of serial interface uart0 ..................... ................................................................. 441 14.4.1 operat ion stop mode.................................................................................................... ............... 441 14.4.2 asynchronous serial interface (u art) mode .............................................................................. 442 14.4.3 dedicated ba ud rate g enerat or.......................................................................................... .......... 448 14.4.4 calculati on of bau d rate ............................................................................................... ............... 449 r01uh0008ej0401 rev.4.01 14 jul 15, 2010 chapter 15 serial interface uart6 ...................................................................................... 453 15.1 functions of serial interface uart6 ..................... ................................................................. 453 15.2 configuration of serial inte rface uart6................................................................................ 45 7 15.3 registers controlling serial interface uart6...... ................................................................. 460 15.4 operation of serial interface uart6 ..................... ................................................................. 469 15.4.1 operat ion stop mode.................................................................................................... ............... 469 15.4.2 asynchronous serial interface (u art) mode .............................................................................. 470 15.4.3 dedicated ba ud rate g enerat or.......................................................................................... .......... 483 15.4.4 calculati on of bau d rate ............................................................................................... ............... 484 chapter 16 serial interfaces csi10 and csi11 ................................................................ 490 16.1 functions of serial interfaces csi10 and csi11 ................................................................... 490 16.2 configuration of serial inte rfaces csi10 and csi11 ............................................................. 491 16.3 registers controlling serial interfaces csi10 a nd csi11 .................................................... 493 16.4 operation of serial interfaces csi10 and csi11 .................................................................... 499 16.4.1 operat ion stop mode.................................................................................................... ............... 499 16.4.2 3-wire se rial i/o mode ................................................................................................. ................ 500 chapter 17 serial interface csia0........................................................................................ 5 12 17.1 functions of serial interface csia0 ...................... ................................................................ . 512 17.2 configuration of serial inte rface csia0 ................................................................................. 5 13 17.3 registers controlling serial interface csia0 ....... ................................................................. 515 17.4 operation of serial interface csia0............. ......................................................................... .. 524 17.4.1 operat ion stop mode.................................................................................................... ............... 524 17.4.2 3-wire se rial i/o mode ................................................................................................. ................ 525 17.4.3 3-wire serial i/o mode with automat ic transmit/recei ve func tion .................................................. 530 chapter 18 serial interface iic0.......................................................................................... .. 550 18.1 functions of serial interface iic0 ................ ....................................................................... .... 550 18.2 configuration of serial inte rface iic0 ................................................................................... .. 553 18.3 registers to control serial interface iic0 ............. ................................................................. 5 56 18.4 i 2 c bus mode functions........................................................................................................... 569 18.4.1 pin c onfigurat ion ...................................................................................................... ................... 569 18.5 i 2 c bus definitions and control methods .............................................................................. 570 18.5.1 start conditi ons ....................................................................................................... .................... 570 18.5.2 a ddresses .............................................................................................................. ..................... 571 18.5.3 transfer direct ion specif ication....................................................................................... ............. 571 18.5.4 ackno wledge (a ck) ...................................................................................................... .............. 572 18.5.5 stop condition ......................................................................................................... .................... 573 18.5.6 wait ................................................................................................................... .......................... 574 18.5.7 canc eling wait ......................................................................................................... .................... 576 18.5.8 interrupt request (intiic0) ge neration timing and wait cont rol .................................................... 576 18.5.9 address matc h detection method ......................................................................................... ....... 577 18.5.10 erro r detec tion....................................................................................................... .................... 577 18.5.11 exte nsion code........................................................................................................ .................. 578 18.5.12 arbi tration........................................................................................................... ....................... 579 18.5.13 wake up func tion....................................................................................................... ................. 580 18.5.14 communicati on reserv ation............................................................................................. .......... 581 r01uh0008ej0401 rev.4.01 15 jul 15, 2010 18.5.15 ca utions .............................................................................................................. ...................... 584 18.5.16 communica tion oper ations.............................................................................................. .......... 585 18.5.17 timing of i 2 c interrupt request (int iic0) occu rrence................................................................. 593 18.6 timing charts ............................................................................................................ ............... 614 chapter 19 multiplier/divider ............................................................................................... .... 621 19.1 functions of multiplier/d ivider.......................................................................................... ...... 621 19.2 configuration of multiplier/ divider ...................................................................................... ... 621 19.3 register controlling multiplier/divider.................. ................................................................ . 625 19.4 operations of multiplier/ divider......................................................................................... ..... 626 19.4.1 multiplica tion oper ation............................................................................................... ................. 626 19.4.2 divisio n operat ion..................................................................................................... ................... 628 chapter 20 interrupt functions............................................................................................. 630 20.1 interrupt function types ................................................................................................. ........ 630 20.2 interrupt sources and configur ation ..................................................................................... 6 30 20.3 registers controlling interrupt functions............ ................................................................. 635 20.4 interrupt servicing oper ations ........................................................................................... .... 656 20.4.1 maskable interr upt acknow ledgment ...................................................................................... ..... 656 20.4.2 software interrupt request ack nowledg ment .............................................................................. . 658 20.4.3 multiple in terrupt se rvicing........................................................................................... ................ 659 20.4.4 interrupt request hold ................................................................................................. ................. 662 chapter 21 key interrupt function ..................................................................................... 663 21.1 functions of key interrupt ............................................................................................... ....... 663 21.2 configuration of key in terrupt ........................................................................................... ..... 664 21.3 register controlling key interrupt ........................ ............................................................... .. 665 chapter 22 standby function ................................................................................................ .. 666 22.1 standby function and co nfiguration ..................................................................................... 66 6 22.1.1 standby func tion ....................................................................................................... .................. 666 22.1.2 registers contro lling standby function................................................................................. ........ 667 22.2 standby function operatio n ............................................................................................... .... 669 22.2.1 ha lt m ode .............................................................................................................. ................... 669 22.2.2 st op m ode .............................................................................................................. .................. 674 chapter 23 reset function.................................................................................................. ...... 681 23.1 register for confirming reset source .................. ................................................................. 69 1 chapter 24 power-on-clear circuit...................................................................................... 692 24.1 functions of power-on-clear circuit..................... ................................................................. 692 24.2 configuration of power-on-clea r circuit ............................................................................... 693 24.3 operation of power-on-clear circuit ..................... ................................................................. 693 24.4 cautions for power-on-clear circuit ..................... ................................................................. 696 r01uh0008ej0401 rev.4.01 16 jul 15, 2010 chapter 25 low-voltage detector ....................................................................................... 698 25.1 functions of low-voltage detector....................... ................................................................. 698 25.2 configuration of low-voltage detector ................................................................................. 699 25.3 registers controlling low-voltage detector........... .............................................................. 699 25.4 operation of low-voltage detector ....................... ................................................................. 702 25.4.1 when us ed as re set ..................................................................................................... ............... 703 25.4.2 when used as interrupt ................................................................................................. .............. 708 25.5 cautions for low-voltage detector ....................... ................................................................. 713 chapter 26 option byte..................................................................................................... .......... 716 26.1 functions of option by tes ................................................................................................ ...... 716 26.2 format of option byte.................................................................................................... .......... 717 chapter 27 flash memory .................................................................................................... ...... 721 27.1 internal memory size switching register ............. ................................................................. 721 27.2 internal expansion ram size switching register ................................................................ 722 27.3 writing with flash memory programmer ............................................................................... 724 27.4 programming environment .................................................................................................. ... 724 27.5 communication mode ....................................................................................................... ....... 725 27.6 connection of pins on board.............................................................................................. .... 727 27.6.1 fl md0 pin.............................................................................................................. ..................... 728 27.6.2 serial interfac e pins.................................................................................................. ................... 728 27.6.3 r eset pin .............................................................................................................. .................... 730 27.6.4 po rt pins .............................................................................................................. ........................ 730 27.6.5 re gc pin ............................................................................................................... ..................... 730 27.6.6 other signal pins ...................................................................................................... ................... 731 27.6.7 powe r suppl y........................................................................................................... .................... 731 27.7 programming method ....................................................................................................... ....... 732 27.7.1 controlli ng flash memory............................................................................................... .............. 732 27.7.2 flash memory programmi ng mode.......................................................................................... .... 732 27.7.3 selecting communicati on mode ........................................................................................... ....... 733 27.7.4 communi cation co mmands................................................................................................. ........ 734 27.8 security settings ........................................................................................................ .............. 735 27.9 processing time for each command when pg-fp4 or pg-fp5 is used (reference) ...... 737 27.10 flash memory programming by self-programming ........................................................... 739 27.10.1 boot swap func tion .................................................................................................... ................ 753 27.11 creating rom code to place order for previ ously written product ................................ 755 27.11.1 procedure for using ro m code to plac e an or der ..................................................................... 755 chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only)................. 756 28.1 connecting qb-mini2 to pd78f05xxd and 78f05xxda ..................................................... 756 28.2 reserved area used by qb-mini2 .......................................................................................... 7 58 r01uh0008ej0401 rev.4.01 17 jul 15, 2010 chapter 29 instruction set................................................................................................. ...... 759 29.1 conventions used in operation list ..................... ................................................................. 7 59 29.1.1 operand identifiers and specificat ion me thods.......................................................................... .. 759 29.1.2 description of operation column ........................................................................................ .......... 760 29.1.3 description of flag operati on colu mn ................................................................................... ........ 760 29.2 operation list ........................................................................................................... ................ 761 29.3 instructions listed by addressing type............... ................................................................. 769 chapter 30 electrical specifications (standard products) ................................... 772 chapter 31 electrical specifications ((a) grade products) .................................... 802 chapter 32 electrical specific ations ((a2) grade products: t a = ? 40 to +110 c) ........830 chapter 33 electrical specific ations ((a2) grade products: t a = ? 40 to +125 c) ........859 chapter 34 package drawings ................................................................................................ 888 34.1 78k0/kb2................................................................................................................. .................. 888 34.2 78k0/kc2................................................................................................................. .................. 891 34.3 78k0/kd2................................................................................................................. .................. 896 34.4 78k0/ke2 ................................................................................................................. .................. 898 34.5 78k0/kf2 ................................................................................................................. .................. 908 chapter 35 recommended soldering conditions ........................................................... 912 chapter 36 cautions for wait.............................................................................................. ... 917 36.1 cautions for wait........................................................................................................ .............. 917 36.2 peripheral hardware that gene rates wait ............................................................................ 918 appendix a development tools............................................................................................... 920 a.1 software package .......................................................................................................... ............ 923 a.2 language processing software ..................................... ......................................................... . 923 a.3 flash memory programming tools.......................................................................................... 92 4 a.3.1 when using flash memory programme r fg-fp5, fl-pr5, fg -fp4, and fl -pr4 ........................ 924 a.3.2 when using on-chip debug emulator with programm ing function qb-mini2................................. 925 a.4 debugging tools (hardware)............................................. ................................................... .... 925 a.4.1 when using in-circu it emulator qb-78k0kx2 ............................................................................... 925 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2................................. 927 a.5 debugging tools (software) .............................................. .................................................. ..... 928 r01uh0008ej0401 rev.4.01 18 jul 15, 2010 appendix b notes on target system design ................................................................... 929 appendix c register index .................................................................................................. ....... 936 c.1 register index (in alphabeti cal order with respect to regist er names) ............................ 936 c.2 register index (in alphabetical order with re spect to register symbol)........................... 940 appendix d list of cautions............................................................................................... 944 appendix e revision history................................................................................................ ...... 974 e.1 major revisions in this edition........................................................................................... ..... 974 e.2 revision history of preceding ed itions................................................................................... 9 75 r01uh0008ej0401 rev.4.01 19 jul 15, 2010 r01uh0008ej0401 rev.4.01 jul 15, 2010 78k0/kx2 renesas mcu chapter 1 outline 1.1 differences between conventional-specification products ( pd78f05xx and 78f05xxd) and expanded-specification products ( pd78f05xxa and 78f05xxda) the differences between the convent ional-specification products ( pd78f05xx and 78f05xxd) and expanded- specification products ( pd78f05xxa and 78f05xxda) of the 78k0/kx 2 microcontrollers are described below. ? a/d conversion time ? x1 oscillator characteristics ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width (ac characteristics) ? the number of flash memory rewrites and retention time ? processing time of the self programming library ? interrupt response time of the self programming library 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 20 jul 15, 2010 1.1.1 a/d conversion time (1) conventional-specification products ( pd78f05xx and 78f05xxd) parameter symbol conditions min. max. unit 4.0 v av ref 5.5 v 6.1 36.7 s 2.7 v av ref < 4.0 v 12.2 36.7 s conversion time t conv 2.3 v av ref < 2.7 v note 27 66.6 s (2) expanded-specification products ( pd78f05xxa and 78f05xxda) parameter symbol conditions min. max. unit 4.0 v av ref 5.5 v 6.1 66.6 s 2.7 v av ref < 4.0 v 12.2 66.6 s conversion time t conv 2.3 v av ref < 2.7 v note 27 66.6 s note standard and (a) grade products only 1.1.2 x1 oscilla tor characteristics (1) conventional-specification products ( pd78f05xx and 78f05xxd) resonator parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 note 2 20.0 2.7 v v dd < 4.0 v 1.0 note 2 10.0 ceramic resonator x1 clock oscillation frequency (f x ) 1.8 v v dd < 2.7 v note 1 1.0 5.0 mhz (2) expanded-specification products ( pd78f05xxa and 78f05xxda) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 1.0 note 2 20.0 ceramic resonator x1 clock oscillation frequency (f x ) 1.8 v v dd < 2.7 v note 1 1.0 5.0 mhz notes 1. standard and (a) grade products only 2. it is 2.0 mhz (min.) when programming on the board via uart6. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 21 jul 15, 2010 1.1.3 time instruction cycle, peri pheral hardware clock frequency, ext ernal main system clock frequency, external main system clock input high-level width, a nd external main system clock input low-level width (ac characteristics) (1) conventional-specification products ( pd78f05xx and 78f05xxd) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s 2.7 v v dd < 4.0 v 0.2 32 s main system clock (f xp ) operation 1.8 v v dd < 2.7 v note 1 0.4 note 3 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 2 114 122 125 s f prs 4.0 v v dd 5.5 v 20 mhz peripheral hardware clock frequency f prs = f xh (xsel = 1) 2.7 v v dd < 4.0 v 10 mhz 1.8 v v dd < 2.7 v note 1 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 mhz f prs = f rh (xsel = 0) 1.8 v v dd < 2.7 v notes 1, 5 7.6 10.4 mhz 4.0 v v dd 5.5 v 1.0 note 6 20.0 mhz 2.7 v v dd < 4.0 v 1.0 note 6 10.0 mhz external main system clock frequency f exclk 1.8 v v dd < 2.7 v note 1 1.0 5.0 mhz 4.0 v v dd 5.5 v 24 ns 2.7 v v dd < 4.0 v 48 ns external main system clock input high-level width, low-level width t exclkh , t exclkl 1.8 v v dd < 2.7 v note 1 96 ns (2) expanded-specification products ( pd78f05xxa and 78f05xxda) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.1 32 s main system clock (f xp ) operation 1.8 v v dd < 2.7 v note 1 0.4 note 3 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 2 114 122 125 s f prs 4.0 v v dd 5.5 v 20 mhz peripheral hardware clock frequency f prs = f xh (xsel = 1) 2.7 v v dd < 4.0 v note 4 20 mhz 1.8 v v dd < 2.7 v note 1 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 mhz f prs = f rh (xsel = 0) 1.8 v v dd < 2.7 v notes 1, 5 7.6 10.4 mhz 2.7 v v dd 5.5 v 1.0 note 6 20.0 mhz external main system clock frequency f exclk 1.8 v v dd < 2.7 v note 1 1.0 5.0 mhz 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exclkh , t exclkl 1.8 v v dd < 2.7 v note 1 96 ns notes 1. standard and (a) grade products only 2. the 78k0/kb2 is not provi ded with a subsystem clock. 3. 0.38 s when operating with the 8 mhz internal oscillator. 4. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f xh /2 (10 mhz) or less. the multipli er/divider, however, can operate on f xh (20 mhz). 5. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f rh /2 or less. 6. 2.0 mhz (min.) when using uart6 during on-board programming. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 22 jul 15, 2010 1.1.4 number of flash memory rewrites and retention time item conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) ? when a flash memory programmer is used, and the libraries note 1 provided by renesas electronics are used ? for program update 1,000 times (retention: 15 years) ? when the eeprom emulation libraries note 2 provided by renesas electronics are used ? the rewritable rom size: 4 kb ? for data update 10,000 times (retention: 5 years) number of rewrites per chip (retention time) 100 times (retention: 10 years) conditions other than the above note 3 100 times (retention: 10 years) notes 1. the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) is excluded. 2. the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) is excluded. 3. these include when the samp le library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) and the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) are used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 23 jul 15, 2010 1.1.5 processing time fo r self programming library (1) conventional-specification products ( pd78f05xx and 78f05xxd) (1/3) <1> when internal high-speed oscillation clock is u sed and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.25 initialize library 977.75 mode check library 753.875 753.125 block blank check library 12770.875 12765.875 block erase library 36909.5 356318 36904.5 356296.25 word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375) block verify library 25618.875 25613.875 self programming end library 4.25 option value: 03h 871.25 (871.375) 866 (866.125) option value: 04h 863.375 (863.5) 858.125 (858.25) get information library option value: 05h 1024.75 (1043.625) 1037.5 (1038.375) set information library 105524.75 790809.375 105523.75 790808.375 eeprom write library 1496.5 (1496.875) 2691.5 (2691.875) 1489.5 (1489.875) 2684.5 (2684.875) <2> when internal high-speed oscillati on clock is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.25 initialize library 443.5 mode check library 219.625 218.875 block blank check library 12236.625 12231.625 block erase library 36363.25 355771.75 36358.25 355750 word write library 679.75 (680.125) 1874.75 (1875.125) 672.75 (673.125) 1867.75 (1868.125) block verify library 25072.625 25067.625 self programming end library 4.25 option value: 03h 337 (337.125) 331.75 (331.875) option value: 04h 329.125 (239.25) 323.875 (324) get information library option value: 05h 502.25 (503.125) 497 (497.875) set information library 104978.5 541143.125 104977.5 541142.125 eeprom write library 962.25 (962.625) 2157.25 (2157.625) 955.25 (955.625) 2150.25 (2150.625) remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 24 jul 15, 2010 (1) conventional-specification products ( pd78f05xx and 78f05xxd) (2/3) <3> when high-speed system clock (x1 oscillation or external clock i nput) is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 49/f cpu + 485.8125 mode check library 35/f cpu + 374.75 29/f cpu + 374.75 block blank check library 174/f cpu + 6382.0625 134/f cpu + 6382.0625 block erase library 174/f cpu + 31093.875 174/f cpu + 298948.125 134/f cpu + 31093.875 134/f cpu + 298948.125 word write library 318 (321)/f cpu + 644.125 318 (321)/f cpu + 1491.625 262 (265)/f cpu + 644.125 262 (265)/f cpu + 1491.625 block verify library 174/f cpu + 13448.5625 134/f cpu + 13448.5625 self programming end library 34/f cpu option value: 03h 171 (172 )/f cpu + 432.4375 129 (130)/f cpu + 432.4375 option value: 04h 181 (182)/f cpu + 427.875 139 (140)/f cpu + 427.875 get information library option value: 05h 404 (411)/f cpu + 496.125 362 (369)/f cpu + 496.125 set information library 75/f cpu + 79157.6875 75/f cpu + 652400 67f cpu + 79157.6875 67f cpu + 652400 eeprom write library 318 (321)/f cpu + 799.875 318 (321)/f cpu + 1647.375 262 (265)/f cpu + 799.875 262 (265)/f cpu + 1647.375 remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. f cpu : cpu operation clock frequency 4. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 25 jul 15, 2010 (1) conventional-specification products ( pd78f05xx and 78f05xxd) (3/3) <4> when high-speed system clock (x1 oscillation or external clock i nput) is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 49/f cpu + 224.6875 mode check library 35/f cpu + 113.625 29/f cpu + 113.625 block blank check library 174/f cpu + 6120.9375 134/f cpu + 6120.9375 block erase library 174/f cpu + 30820.75 174/f cpu + 298675 134/f cpu + 30820.75 134/f cpu + 298675 word write library 318 (321)/f cpu + 383 318 (321)/f cpu + 1230.5 262 (265)/f cpu + 383 262 (265)/f cpu + 1230.5 block verify library 174/f cpu + 13175.4375 134/f cpu + 13175.4375 self programming end library 34/f cpu option value: 03h 171 (172)/f cpu + 171.3125 129 (130)/f cpu + 171.3125 option value: 04h 181 (182)/f cpu + 166.75 139 (140)/f cpu + 166.75 get information library option value: 05h 404 (411)/f cpu + 231.875 362 (369)/f cpu + 231.875 set information library 75/f cpu + 78884.5625 75/f cpu + 527566.875 67/f cpu + 78884.5625 67/f cpu + 527566.875 eeprom write library 318 (321)/f cpu + 538.75 318 (321)/f cpu + 1386.25 262 (265)/f cpu + 538.75 262 (265)/f cpu + 1386.25 remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. f cpu : cpu operation clock frequency 4. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 26 jul 15, 2010 (2) expanded-specification products ( pd78f05xxa and 78f05xxda) (1/3) <1> when internal high-speed oscillation clock is u sed and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.0 4.5 4.0 4.5 initialize library 1105.9 1106.6 1105.9 1106.6 mode check library 905.7 906.1 904.9 905.3 block blank check library 12776.1 12778.3 12770.9 12772.6 block erase library 26050.4 349971.3 26045.3 349965.6 word write library 1180.1 + 203 w 1184.3 + 2241 w 1172.9 + 203 w 1176.3 + 2241 w block verify library 25337.9 25340.2 25332.8 25334.5 self programming end library 4.0 4.5 4.0 4.5 option value: 03h 1072.9 1075.2 1067.5 1069.1 option value: 04h 1060.2 1062.6 1054.8 1056.6 get information library option value: 05h 1023.8 1028.2 1018.3 1022.1 set information library 70265.9 759995.0 70264.9 759994.0 eeprom write library 1316.8 + 347 w 1320.9 + 2385 w 1309.0 + 347 w 1312.4 + 2385 w <2> when internal high-speed oscillati on clock is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.0 4.5 4.0 4.5 initialize library 449.5 450.2 449.5 450.2 mode check library 249.3 249.7 248.6 248.9 block blank check library 12119.7 12121.9 12114.6 12116.3 block erase library 25344.7 349266.4 25339.6 349260.8 word write library 445.8 + 203 w 449.9 + 2241 w 438.5 + 203 w 441.9 + 2241 w block verify library 24682.7 24684.9 24677.6 24679.3 self programming end library 4.0 4.5 4.0 4.5 option value: 03h 417.6 419.8 412.1 413.8 option value: 04h 405.0 407.4 399.5 401.3 get information library option value: 05h 367.4 371.8 361.9 365.8 set information library 69569.3 759297.3 69568.3 759296.2 eeprom write library 795.1 + 347 w 799.3 + 2385 w 787.4 + 347 w 790.8 + 2385 w remarks 1. the above processing times are those when a write st art address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 27 jul 15, 2010 (2) expanded-specification products ( pd78f05xxa and 78f05xxda) (2/3) <3> when high-speed system clock (x1 oscillation or external clock i nput) is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 55/f cpu + 594 mode check library 36/f cpu + 495 30/f cpu + 495 block blank check library 179/f cpu + 6429 136/f cpu + 6429 block erase library 179/f cpu + 19713 179/f cpu + 268079 136/f cpu + 19713 136/f cpu + 268079 word write library 333/f cpu + 647 + 136 w 333/f cpu + 647 + 1647 w 272/f cpu + 647 + 136 w 272/f cpu + 647 + 1647 w block verify library 179/f cpu + 13284 136/f cpu + 13284 self programming end library 34/f cpu option value: 03h 180/f cpu + 581 134f cpu + 581 option value: 04h 190/f cpu + 574 144/f cpu + 574 get information library option value: 05h 350/f cpu + 535 304/f cpu + 535 set information library 80/f cpu + 43181 80/f cpu + 572934 72/f cpu + 43181 72/f cpu + 572934 eeprom write library 333/f cpu + 729 + 209 w 333/f cpu + 729 + 1722 w 268/f cpu + 729 + 209 w 268/f cpu + 729 + 1722 w remarks 1. the above processing times are those when a write st art address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. f cpu : cpu operation clock frequency 4. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 28 jul 15, 2010 (2) expanded-specification products ( pd78f05xxa and 78f05xxda) (3/3) <4> when high-speed system clock (x1 oscillation or external clock i nput) is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 55/f cpu + 272 mode check library 36/f cpu + 173 30/f cpu + 173 block blank check library 179/f cpu + 6108 136/f cpu + 6108 block erase library 179/f cpu + 19371 179/f cpu + 267738 136/f cpu + 19371 136/f cpu + 267738 word write library 333/f cpu + 247 + 136 w 333/f cpu + 247 + 1647 w 272/f cpu + 247 + 136 w 272/f cpu + 247 + 1647 w block verify library 179/f cpu + 12964 136/f cpu + 12964 self programming end library 34/f cpu option value: 03h 180/f cpu + 261 134/f cpu + 261 option value: 04h 190/f cpu + 254 144/f cpu + 254 get information library option value: 05h 350/f cpu + 213 304/f cpu + 213 set information library 80/f cpu + 42839 80/f cpu + 572592 72/f cpu + 42839 72/f cpu + 572592 eeprom write library 333/f cpu + 516 + 209 w 333/f cpu + 516 + 1722 w 268/f cpu + 516 + 209 w 268/f cpu + 516 + 1722 w remarks 1. the above processing times are those when a write st art address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. f cpu : cpu operation clock frequency 4. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 29 jul 15, 2010 1.1.6 interrupt response time for self programming library (1) conventional-specification products ( pd78f05xx and 78f05xxd) (1/2) <1> when internal high-speed oscillation clock is used interrupt response time ( s (max.)) normal model of c compiler static model of c compiler/assembler library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 933.6 668.6 927.9 662.9 block erase library 1026.6 763.6 1020.9 757.9 word write library 2505.8 1942.8 2497.8 1934.8 block verify library 958.6 693.6 952.9 687.9 set information library 476.5 211.5 475.5 210.5 eeprom write library 2760.8 2168.8 2759.5 2167.5 remarks 1. the above interrupt response times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) <2> when high-speed system clock is used (normal model of c compiler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 179/f cpu + 507 179/f cpu + 407 179/f cpu + 1650 179/f cpu + 714 block erase library 179/f cpu + 559 179/f cpu + 460 179/f cpu + 1702 179/f cpu + 767 word write library 333/f cpu + 1589 333/f cpu + 1298 333/f cpu + 2732 333/f cpu + 1605 block verify library 179/f cpu + 518 179/f cpu + 418 179/f cpu + 1661 179/f cpu + 725 set information library 80/f cpu + 370 80/f cpu + 165 80/f cpu + 1513 80/f cpu + 472 29/f cpu + 1759 29/f cpu + 1468 29/f cpu + 1759 29/f cpu + 1468 eeprom write library note 333/f cpu + 834 333/f cpu + 512 333/f cpu + 2061 333/f cpu + 873 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 30 jul 15, 2010 (1) conventional-specification products ( pd78f05xx and 78f05xxd) (2/2) <3> when high-speed system clock is used (static model of c compiler/assembler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 136/f cpu + 507 136/f cpu + 407 136/f cpu + 1650 136/f cpu + 714 block erase library 136/f cpu + 559 136/f cpu + 460 136/f cpu + 1702 136/f cpu + 767 word write library 272/f cpu + 1589 272/f cpu + 1298 272/f cpu + 2732 272/f cpu + 1605 block verify library 136/f cpu + 518 136/f cpu + 418 136/f cpu + 1661 136/f cpu + 725 set information library 72/f cpu + 370 72/f cpu + 165 72/f cpu + 1513 72/f cpu + 472 19/f cpu + 1759 19/f cpu + 1468 19/f cpu + 1759 19/f cpu + 1468 eeprom write library note 268/f cpu + 834 268/f cpu + 512 268/f cpu + 2061 268/f cpu + 873 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 31 jul 15, 2010 (2) expanded-specification products ( pd78f05xxa and 78f05xxda) (1/2) <1> when internal high-speed oscillation clock is used interrupt response time ( s (max.)) normal model of c compiler static model of c compiler/assembler library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 1100.9 431.9 1095.3 426.3 block erase library 1452.9 783.9 1447.3 778.3 word write library 1247.2 579.2 1239.2 571.2 block verify library 1125.9 455.9 1120.3 450.3 set information library 906.9 312.0 905.8 311.0 eeprom write library 1215.2 547.2 1213.9 545.9 remarks 1. the above interrupt response times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) <2> when high-speed system clock is used (normal model of c compiler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 179/f cpu + 567 179/f cpu + 246 179/f cpu + 1708 179/f cpu + 569 block erase library 179/f cpu + 780 179/f cpu + 459 179/f cpu + 1921 179/f cpu + 782 word write library 333/f cpu + 763 333/f cpu + 443 333/f cpu + 1871 333/f cpu + 767 block verify library 179/f cpu + 580 179/f cpu + 259 179/f cpu + 1721 179/f cpu + 582 set information library 80/f cpu + 456 80/f cpu + 200 80/f cpu + 1598 80/f cpu + 459 29/f cpu + 767 29/f cpu + 447 29/f cpu + 767 29/f cpu + 447 eeprom write library note 333/f cpu + 696 333/f cpu + 376 333/f cpu + 1838 333/f cpu + 700 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 32 jul 15, 2010 (2) expanded-specification products ( pd78f05xxa and 78f05xxda) (2/2) <3> when high-speed system clock is used (static model of c compiler/assembler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 136/f cpu + 567 136/f cpu + 246 136/f cpu + 1708 136/f cpu + 569 block erase library 136/f cpu + 780 136/f cpu + 459 136/f cpu + 1921 136/f cpu + 782 word write library 272/f cpu + 763 272/f cpu + 443 272/f cpu + 1871 272/f cpu + 767 block verify library 136/f cpu + 580 136/f cpu + 259 136/f cpu + 1721 136/f cpu + 582 set information library 72/f cpu + 456 72/f cpu + 200 72/f cpu + 1598 72/f cpu + 459 19/f cpu + 767 19/f cpu + 447 19/f cpu + 767 19/f cpuv + 447 eeprom write library note 268/f cpu + 696 268/f cpu + 376 268/f cpu + 1838 268/f cpu + 700 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 33 jul 15, 2010 1.2 features { minimum instruction execution time can be changed from high speed (0.1 p s: @ 20 mhz operation with high-speed system clock) to ultra low-speed (122 p s: @ 32.768 khz operatio n with subsystem clock) { general-purpose register: 8 bits u 32 registers (8 bits u 8 registers u 4 banks) { rom (flash memory), ram capacities 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 rom note high- speed ram note expansion ram note 30/36 pins 38/44 pins 48 pins 52 pins 64 pins 80 pins p pd78f0527d, 78f0527da p pd78f0537d, 78f0537da p pd78f0547d, 78f0547da 128 kb 1 kb 6 kb p pd78f0527, 78f0527a p pd78f0537, 78f0537a p pd78f0547 78f0547a 96 kb 1 kb 4 kb p pd78f0526, 78f0526a p pd78f0536, 78f0536a p pd78f0546, 78f0546a p pd78f0515d, 78f0515da 60 kb 1 kb 2 kb p pd78f0515, 78f0515a p pd78f0525, 78f0525a p pd78f0535, 78f0535a p pd78f0545, 78f0545a 48 kb 1 kb 1 kb p pd78f0514, 78f0514a p pd78f0524, 78f0524a p pd78f0534, 78f0534a p pd78f0544, 78f0544a p pd78f0503d, 78f0503da p pd78f0513d, 78f0513da 32 kb 1 kb p pd78f0503, 78f0503a p pd78f0513, 78f0513a p pd78f0513, 78f0513a p pd78f0523, 78f0523a p pd78f0533, 78f0533a 24 kb 1 kb p pd78f0502, 78f0502a p pd78f0512, 78f0512a p pd78f0512, 78f0512a p pd78f0522, 78f0522a p pd78f0532, 78f0532a 16 kb 768 b p pd78f0501, 78f0501a p pd78f0511, 78f0511a p pd78f0511, 78f0511a p pd78f0521, 78f0521a p pd78f0531, 78f0531a 8 kb 512 b p pd78f0500, 78f0500a note the internal flash memory, internal high-speed ram capacities, and internal expansion ram capacities can be changed using the internal memory size switching regist er (ims) and the internal expansion ram size switching register (ixs). for ims and ixs, see 27.1 internal memory size switching register and 27.2 internal expansion ram size switching register . { buffer ram: 32 bytes (can be used for transfer in csi wit h automatic transmit/receive function) (78k0/kf2 only) { on-chip single-power-supply flash memory { self-programming (with boot swap function) { on-chip debug function ( p pd78f05xxd and 78f05xxda only) note note the p pd78f05xxd and 78f05xxda have an on-chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceed ed when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 34 jul 15, 2010 { on-chip 10-bit resolution a/d converter (av ref = 2.3 to 5.5 v) { on-chip multiplier/divider (16 bits u 16 bits, 32 bits/16 bits), key interr upt function, clock output/buzzer output controller, i/o ports, timer, and serial interface { power supply voltage x standard products, (a) grade products: v dd = 1.8 to 5.5 v x (a2) grade products: v dd = 2.7 to 5.5 v { operating ambient temperature x standard products, (a) grade products: t a = ?40 to +85 q c x (a2) grade products: t a = ?40 to +125 q c remark the functions mounted de pend on the product. see 1.7 block diagram and 1.8 outline of functions . 1.3 applications { automotive equipment (compatible with (a) and (a2) grade products) x system control for body electricals (power windows, keyless entry reception, etc.) x sub-microcontrollers for control { car audio { av equipment, home audio { pc peripheral equipment (keyboards, etc.) { household electrical appliances x air conditioners x microwave ovens, electric rice cookers { industrial equipment x pumps x vending machines x fa (factory automation) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 35 jul 15, 2010 1.4 ordering information [part number] pd78f05xy x x xx (x) - xxx - xx a lead- free semiconductor ax, g product contains no lead in any area not mounted product contains no lead in any area (terminal finish is ni/pd/au plating) none standard (t a = ? 40 to + 85 c) special (t a = ? 40 to + 85 c) quality grade (a), a a expanded-specification products product type f flash memory version product type none mounted d on-chip debug function 50y (kb2) 51y (kc2) mc-cab fc-aa3 30-pin plastic ssop (7.62 mm (300)) 36-pin plastic flga (4x4) mc-gaa 38-pin plastic ssop (7.62 mm (300)) 52y (kd2) gb-gag 52-pin plastic lqfp (10x10) gb-gaf 44-pin plastic lqfp (10x10) ga-8eu 48-pin plastic lqfp (fine pitch) (7x7) 53y (ke2) gb-gah 64-pin plastic lqfp (fine pitch) (10x10) gc-gal 64-pin plastic lqfp (14x14) 54y (kf2) gc-gad 80-pin plastic lqfp (14x14) gk-gak 80-pin plastic lqfp (fine pitch) (12x12) gk-gaj 64-pin plastic lqfp (12x12) ga-hab 64-pin plastic tqfp (fine pitch) (7x7) fc-aa1 64-pin plastic flga (5x5) package type 5x0 5x1 5x2 5x3 5x4 5x5 5x6 5x7 512 bytes 768 bytes 1 kb 1 kb 1 kb 1 kb 1 kb 1 kb _ _ _ _ 1 kb 2 kb 4 kb 6 kb 8 kb 16 kb 24 kb 32 kb 48 kb 60 kb 96 kb 128 kb high-speed ram capacity expansion ram capacity flash memory capacity (a2), a2 special (t a = ? 40 to + 125 c) mc-5a4 gb-ues ga-gam gb-uet gb-ueu gc-ubs gk-uet ga-9ev f1-aa2 64-pin plastic fbga (4x4) gc-ubt gk-8eu none conventional-specification products please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by renesas electronics to know the specification of quality grade on the devices and its recommended applications. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 36 jul 15, 2010 [list of part number] (1/6) 78k0/kx2 microcontrollers package product type quality grace part number standard products pd78f0500mc-5a4-a, 78f0501mc-5a4-a, 78f0502mc-5a4-a, 78f0503mc-5a4-a, 78f0503dmc-5a4-a note (a) grade products pd78f0500mc(a)-cab-ax, 78f0501mc(a)-cab-ax, 78f0502mc(a)-cab-ax, 78f 0503mc(a)-cab-ax conventional- specification products (a2) grade products pd78f0500mc(a2)-cab-ax, 78f0501mc(a2)-cab-ax, 78f0502mc(a2)-cab-ax, 78 f0503mc(a2)-cab-ax standard products pd78f0500amc-cab-ax, 78f0501amc-cab-ax, 78f0502amc-cab-ax, 78f0503amc-cab-ax, 78f0503damc-cab-ax note (a) grade products pd78f0500amca-cab-g, 78f0501amca-cab-g, 78f0502amca-cab-g, 78f0503amca-cab-g 30-pin plastic ssop (7.62 mm (300)) expanded- specification products (a2) grade products pd78f0500amca2-cab-g, 78f0501amca2-cab-g, 78f0502amca2-cab-g, 78f0503amca2-cab-g conventional- specification products standard products pd78f0500fc-aa3-a, 78f0501fc-aa3-a, 78f0502fc-aa3-a, 78f0503fc-aa3-a, 78f0503dfc-aa3-a note 78k0/kb2 36-pin plastic flga (4x4) expanded- specification products standard products pd78f0500afc-aa3-a, 78f0501afc-aa3-a, 78f0502afc-aa3-a, 78f0503afc-aa3-a, 78f0503dafc-aa3-a note standard products pd78f0511amc-gaa-ax, 78f0512amc-gaa-ax, 78f0513amc-gaa-ax, 78f0513damc-gaa-ax note (a) grade products pd78f0511amca-gaa-g, 78f0512amca-gaa-g, 78f0513amca-gaa-g 38-pin plastic ssop (7.62 mm (300)) expanded- specification products (a2) grade products pd78f0511amca2-gaa-g, 78f0512amca2-gaa-g, 78f0513amca2-gaa-g standard products pd78f0511gb-ues-a, 78f0512gb-ues-a, 78f0513gb-ues-a, 78f0513dgb-ues-a note (a) grade products pd78f0511gb(a)-gaf-ax, 78f0512gb(a)-gaf-ax, 78f0513gb(a)-gaf-ax conventional- specification products (a2) grade products pd78f0511gb(a2)-gaf-ax, 78f0512gb(a2)-gaf-ax, 78f0513gb(a2)-gaf-ax standard products pd78f0511agb-gaf-ax, 78f0512agb-gaf-ax, 78f0513agb-gaf-ax, 78f0513dagb-gaf-ax note (a) grade products pd78f0511agba-gaf-g, 78f0512agba-gaf-g, 78f0513agba-gaf-g 78k0/kc2 44-pin plastic lqfp (10x10) expanded- specification products (a2) grade products pd78f0511agba2-gaf-g , 78f0512agba2-gaf-g, 78f0513agba2-gaf-g note the pd78f0503d, 78f0503da, 78f0513d, and 78f0513da have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewrit able times of the flash memory may be exceeded when this function is used, and product reliability theref ore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 37 jul 15, 2010 (2/6) 78k0/kx2 microcontrollers package product type quality grace part number standard products pd78f0511ga-8eu-a, 78f0512ga-8eu-a, 78f0513ga-8eu-a, 78f0514ga-8eu-a, 78f0515ga-8eu-a, 78f0515dga-8eu-a note (a) grade products pd78f0511ga(a)-gam-ax, 78f0512ga(a)-gam-ax, 78f0513ga(a)-gam-ax, 78f0514ga(a)-gam-ax, 78f0515ga(a)-gam-ax conventional- specification products (a2) grade products pd78f0511ga(a2)-gam-ax, 78f0512ga(a2)-gam-ax, 78f0513ga(a2)-gam-ax, 78f0514ga(a2)-gam-ax, 78f0515ga(a2)-gam-ax standard products pd78f0511aga-gam-ax, 78f0512aga-gam-ax, 78f0513aga-gam-ax, 78f0514aga-gam-ax, 78f0515aga-gam-ax, 78f0515daga-gam-ax note (a) grade products pd78f0511agaa-gam-g, 78f0512agaa-gam-g, 78f0513agaa-gam-g, 78 f0514agaa-gam-g, 78f0515agaa-gam-g 78k0/kc2 48-pin plastic lqfp (fine pitch) (7x7) expanded- specification products (a2) grade products pd78f0511agaa2-gam-g , 78f0512agaa2-gam-g, 78f0513agaa2-gam-g, 78 f0514agaa2-gam-g, 78f0515agaa2-gam-g standard products pd78f0521gb-uet-a, 78f0522gb-uet-a, 78f0523gb-uet-a, 78f0524gb-uet-a, 78f0525gb-uet-a, 78f0526gb-uet-a, 78f0527gb-uet-a, 78f0527dgb-uet-a note (a) grade products pd78f0521gb(a)-gag-ax, 78f0522gb(a)-gag-ax, 78f0523gb(a)-gag-ax, 78f0524gb(a)-gag-ax, 78f0525gb(a)-gag-ax, 78f0526gb(a)-gag-ax, 78f0527gb(a)-gag-ax conventional- specification products (a2) grade products pd78f0521gb(a2)-gag-ax, 78f0522gb(a2)-gag-ax, 78f0523gb(a2)-gag-ax, 78f0524gb(a2)-gag-ax, 78f0525gb(a2)-gag-ax, 78f0526gb(a2)-gag-ax, 78f0527gb(a2)-gag-ax standard products pd78f0521agb-gag-ax, 78f0522agb-gag-ax, 78f0523agb-gag-ax, 78f0524agb-gag-ax, 78f0525agb-gag-ax, 78f0526agb-gag-ax, 78f0527agb-gag-ax, 78f0527dagb-gag-ax note (a) grade products pd78f0521agba-gag-g, 78f0522agba-gag-g, 78f0523agba-gag-g, 78f 0524agba-gag-g, 78f0525agba-gag-g, 78f 0526agba-gag-g, 78f0527agba-gag-g 78k0/kd2 52-pin plastic lqfp (10x10) expanded- specification products (a2) grade products pd78f0521agba2-gag-g, 78f0522agba2-gag-g, 78f0523agba2-gag-g, 78f 0524agba2-gag-g, 78f0525agba2-gag-g, 78f 0526agba2-gag-g, 78f0527agba2-gag-g note the pd78f0515d, 78f0515da, 78f0527d, and 78f0527da have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewrit able times of the flash memory may be exceeded when this function is used, and product reliability theref ore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 38 jul 15, 2010 (3/6) 78k0/kx2 microcontrollers package product type quality grace part number standard products pd78f0531gb-ueu-a, 78f0532gb-ueu-a, 78f0533gb-ueu-a, 78f0534gb-ueu-a, 78f0535gb-ueu-a, 78f0536gb-ueu-a, 78f0537gb-ueu-a, 78f0537dgb-ueu-a note (a) grade products pd78f0531gb(a)-gah-ax, 78f0532gb(a)-gah-ax, 78f0533gb(a)-gah-ax, 78f0534gb(a)-gah-ax, 78f0535gb(a)-gah-ax, 78f0536gb(a)-gah-ax, 78f0537gb(a)-gah-ax conventional- specification products (a2) grade products pd78f0531gb(a2)-gah-ax, 78f0532gb(a2)-gah-ax, 78f0533gb(a2)-gah-ax, 78f0534gb(a2)-gah-ax, 78f0535gb(a2)-gah-ax, 78f0536gb(a2)-gah-ax, 78f0537gb(a2)-gah-ax standard products pd78f0531agb-gah-ax, 78f0532agb-gah-ax, 78f0533agb-gah-ax, 78f0534agb-gah-ax, 78f0535agb-gah-ax, 78f0536agb-gah-ax, 78f0537agb-gah-ax, 78f0537dagb-gah-ax note (a) grade products pd78f0531agba-gah-g, 78f0532agba-gah-g, 78f0533agba-gah-g, 78 f0534agba-gah-g, 78f0535agba-gah-g, 78 f0536agba-gah-g, 78f0537agba-gah-g 78k0/ke2 64-pin plastic lqfp (fine pitch) (10x10) expanded- specification products (a2) grade products pd78f0531agba2-gah-g, 78f0532agba2-gah-g, 78f0533agba2-gah-g, 78 f0534agba2-gah-g, 78f0535agba2-gah-g, 78 f0536agba2-gah-g, 78f0537agba2-gah-g note the pd78f0537d and 78f0537da have an on-chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceed ed when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 39 jul 15, 2010 (4/6) 78k0/kx2 microcontrollers package product type quality grace part number standard products pd 78f0531gc-ubs-a, 78f0532gc-ubs-a, 78f0533gc-ubs-a, 78f0534gc-ubs-a, 78f0535gc-ubs-a, 78f0536gc-ubs-a, 78f0537gc-ubs-a, 78f0537dgc-ubs-a note (a) grade products pd78f0531gc(a)-gal-ax, 78f0532gc(a)-gal-ax, 78f0533gc(a)-gal-ax, 78f0534gc(a)-gal-ax, 78f0535gc(a)-gal-ax, 78f0536gc(a)-gal-ax, 78f0537gc(a)-gal-ax conventional- specification products (a2) grade products pd78f0531gc(a2)-gal-ax, 78f0532gc(a2)-gal-ax, 78f0533gc(a2)-gal-ax, 78f0534gc(a2)-gal-ax, 78f0535gc(a2)-gal-ax, 78f0536gc(a2)-gal-ax, 78f0537gc(a2)-gal-ax standard products pd78f0531agc-gal-ax, 78f0532agc-gal-ax, 78f0533agc-gal-ax, 78f0534agc-gal-ax, 78f0535agc-gal-ax, 78f0536agc-gal-ax, 78f0537agc-gal-ax, 78f0537dagc-gal-ax note (a) grade products pd78f0531agca-gal-g, 78f0532agca-gal-g, 78f0533agca-gal-g, 78f0534agca-gal-g, 78f0535agca-gal-g, 78f0536agca-gal-g, 78f0537agca-gal-g 78k0/ke2 64-pin plastic lqfp (14x14) expanded- specification products (a2) grade products pd78f0531agca2-gal-g, 78f0532agca2-gal-g, 78f0533agca2-gal-g, 78f0534agca2-gal-g, 78f0535agca2-gal-g, 78f0536agca2-gal-g, 78f0537agca2-gal-g note the pd78f0537d and 78f0537da have an on-chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceed ed when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 40 jul 15, 2010 (5/6) 78k0/kx2 microcontrollers package product type quality grace part number standard products pd78f0531gk-uet-a, 78f0532gk-uet-a, 78f0533gk-uet-a, 78f0534gk-uet-a, 78f0535gk-uet-a, 78f0536gk-uet-a, 78f0537gk-uet-a, 78f0537dgk-uet-a note (a) grade products pd78f0531gk(a)-gaj-ax, 78f0532gk(a)-gaj-ax, 78f0533gk(a)-gaj-ax, 78f0534gk(a)-gaj-ax, 78f0535gk(a)-gaj-ax, 78f0536gk(a)-gaj-ax, 78f0537gk(a)-gaj-ax conventional- specification products (a2) grade products pd 78f0531gk(a2)-gaj-ax, 78f0532gk(a2)-gaj-ax, 78f0533gk(a2)-gaj-ax, 78f0534gk(a2)-gaj-ax, 78f0535gk(a2)-gaj-ax, 78f0536gk(a2)-gaj-ax, 78f0537gk(a2)-gaj-ax standard products pd78f0531agk-gaj-ax, 78f0532agk-gaj-ax, 78f0533agk-gaj-ax, 78 f0534agk-gaj-ax, 78f0535agk-gaj-ax, 78 f0536agk-gaj-ax, 78f0537agk-gaj-ax, 78f0537dagk-gaj-ax note (a) grade products pd78f0531agka-gaj-g, 78f0532agka-gaj-g, 78f0533agka-gaj-g, 78f0534agka-gaj-g, 78f0535agka-gaj-g, 78f0536agka-gaj-g, 78f0537agka-gaj-g 64-pin plastic lqfp (12x12) expanded- specification products (a2) grade products pd78f0531agka2-gaj-g, 78f0532agka2-gaj-g, 78f0533agka2-gaj-g, 78f 0534agka2-gaj-g, 78f0535agka2-gaj-g, 78f 0536agka2-gaj-g, 78f0537agka2-gaj-g conventional- specification products standard products pd78f0531ga-9ev-a, 78f0532ga-9ev-a, 78f0533ga-9ev-a, 78f0534ga-9ev-a, 78f0535ga-9ev-a, 78f0536ga-9ev-a, 78f0537ga-9ev-a, 78f0537dga-9ev-a note 78k0/ke2 64-pin plastic tqfp (fine pitch) (7x7) expanded- specification products standard products pd78f0531aga-hab-ax, 78f0532aga-hab-ax, 78f0533aga-hab-ax, 78f0534aga-hab-ax, 78f0535aga-hab-ax, 78f0536aga-hab-ax, 78f0537aga-hab-ax, 78f0537daga-hab-ax note note the pd78f0537d and 78f0537da have an on-chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceed ed when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 41 jul 15, 2010 (6/6) 78k0/kx2 microcontrollers package product type quality grace part number conventional- specification products standard products pd 78f0531fc-aa1-a, 78f0532fc-aa1-a, 78f0533fc-aa1-a, 78f0534fc-aa1-a, 78f0535fc-aa1-a, 78f0536fc-aa1-a, 78f0537fc-aa1-a, 78f0537dfc-aa1-a note 64-pin plastic flga (5x5) expanded- specification products standard products pd78f0531afc-aa1-a, 78f0532afc-aa1-a, 78f0533afc-aa1-a, 78f0534afc-aa1-a, 78f0535afc-aa1-a, 78f0536afc-aa1-a, 78f0537afc-aa1-a, 78f0537dafc-aa1-a note 78k0/ke2 64-pin plastic fbga (4x4) expanded- specification products standard products pd78f0531af1-aa2-a, 78f0532af1-aa2-a, 78f0533af1-aa2-a, 78f0534af1-aa2-a, 78f0535af1-aa2-a, 78f0536af1-aa2-a, 78f0537af1-aa2-a, 78f0537daf1-aa2-a note standard products pd78f0544gc-ubt-a, 78f0545gc-ubt-a, 78f0546gc-ubt-a, 78f0547gc-ubt-a, 78f0547dgc-ubt-a note (a) grade products pd78f0544gc(a)-gad-ax, 78f0545gc(a)-gad-ax, 78f0546gc(a)-gad-ax, 78f0547gc(a)-gad-ax conventional- specification products (a2) grade products pd78f0544gc(a2)-gad-ax, 78f0545gc(a2)-gad-ax, 78f0546gc(a2)-gad-ax, 78f0547gc(a2)-gad-ax standard products pd78f0544agc-gad-ax, 78f0545agc-gad-ax, 78f0546agc-gad-ax, 78f0547agc-gad-ax, 78f0547dagc-gad-ax note (a) grade products pd78f0544agca-gad-g, 78f0545agca-gad-g, 78f0546agca-gad-g, 78 f0547agca-gad-g 80-pin plastic lqfp (14x14) expanded- specification products (a2) grade products pd78f0544agca2-gad-g, 78f0545agca2-gad-g, 78f0546agca2-gad-g, 78f0547agca2-gad-g standard products pd78f0544gk-8eu-a, 78f0545gk-8eu-a, 78f0546gk-8eu-a, 78f0547gk-8eu-a, 78f0547dgk-8eu-a note (a) grade products pd78f0544gk(a)-gak-ax, 78f0545gk(a)-gak-ax, 78f0546gk(a)-gak-ax, 78f0547gk(a)-gak-ax conventional- specification products (a2) grade products pd78f0544gk(a2)-gak-ax, 78f0545gk(a2)-gak-ax, 78f0546gk(a2)-gak-ax, 78 f0547gk(a2)-gak-ax standard products pd78f0544agk-gak-ax, 78f0545agk-gak-ax, 78f0546agk-gak-ax, 78f 0547agk-gak-ax, 78f0547dagk-gak-ax note (a) grade products pd78f0544agka-gak-g, 78f0545agka-gak-g, 78f0546agka-gak-g, 78 f0547agka-gak-g 78k0/kf2 80-pin plastic lqfp (fine pitch) (12x12) expanded- specification products (a2) grade products pd78f0544agka2-gak-g, 78f0545agka2-gak-g, 78f0546agka2-gak-g, 78 f0547agka2-gak-g note the pd78f0537d, 78f0537da, 78f0547d, and 78f0547da have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability theref ore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 42 jul 15, 2010 1.5 pin configuration (top view) 1.5.1 78k0/kb2 ? 30-pin plastic ssop (7.62 mm (300)) ani1/p21 ani0/p20 p01/ti010/to00 p00/ti000 p120/intp0/exlvi reset flmd0 p121/x1/ocd0a note p122/x2/exclk/ocd0b note v ss regc v dd p60/scl0 p61/sda0 p33/ti51/to51/intp4 28 27 26 30 29 25 24 23 22 21 20 19 18 16 ani2/p22 ani3/p23 av ss av ref p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p16/toh1/intp5 p15/toh0 p17/ti50/to50 p30/intp1 p31/intp2/ocd1a note p32/intp3/ocd1b note 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 note products with on-chip debug function only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 3. ani0/p20 to ani3/p23 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 43 jul 15, 2010 ? 36-pin plastic flga (4x4) top view bottom view fedcba abcdef 6 5 4 3 2 1 index mark pin no. pin name pin no. pin name pin no. pin name a1 nc note 1 c1 p17/ti50/to50 e1 av ref a2 p32/intp3/ocd1b note 2 c2 p14/rxd6 e2 av ss a3 p30/intp1 c3 p13/txd6 e3 ani2/p22 a4 p61/sda0 c4 p00/ti000 e4 ani1/p21 a5 p33/ti51/to51/intp4 c5 v dd e5 flmd0 a6 nc note 1 c6 p121/x1/ocd0a note 2 e6 reset b1 p31/intp2/ocd1a note 2 d1 p11/si10/rxd0 f1 nc note 1 b2 p16/toh1/intp5 d2 p12/so10 f2 ani3/p23 b3 p15/toh0 d3 p10/sck10/txd0 f3 ani0/p20 b4 p60/scl0 d4 regc f4 p01/ti010/to00 b5 ev dd d5 v ss f5 p120/intp0/exlvi b6 ev ss d6 p122/x2/exclk/ ocd0b note 2 f6 nc note 1 notes 1. it is recommended to connect nc to v ss . 2. products with on-chip debug function only cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 4. ani0/p20 to ani3/p23 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 44 jul 15, 2010 1.5.2 78k0/kc2 ? 38-pin plastic ssop (7.62 mm (300)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ani1/p21 ani0/p20 p01/ti010/to00 p00/ti000 p120/intp0/exlvi reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note p121/x1/ocd0a note regc v ss v dd p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 ani2/p22 ani3/p23 ani4/p24 ani5/p25 av ss av ref p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p31/intp2/ocd1a note p32/intp3/ocd1b note p70/kr0 p71/kr1 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 note products with on-chip debug function only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 3. ani0/p20 to ani5/p25 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 45 jul 15, 2010 ? 44-pin plastic lqfp (10 10) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note p121/x1/ocd0a note regc v ss v dd av ss av ref p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p32/intp3/ocd1b note p31/intp2/ocd1a note p120/intp0/exlvi p00/ti000 p01/ti010/to00 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 note products with on-chip debug function only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 3. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 46 jul 15, 2010 ? 48-pin plastic lqfp (fine pitch) (7 7) p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p75 p74 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p32/intp3/ocd1b note 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 p140/pcl/intp6 p00/ti000 p01/ti010/to00 p130 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 p31/intp2/ocd1a note p30/intp1 p17/ti50/to50 p16/toh1/intp5 p15/toh0 p14/rxd6 p13/txd6 p12/so10 p11/sl10/rxd0 p10/sck10/txd0 av ref av ss v dd v ss regc p121/x1/ocd0a note p122/x2/exclk/ocd0b note flmd0 p123/xt1 p124/xt2/exclks reset p40 p41 p120/intp0/exlvi note products with on-chip debug function only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 3. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 47 jul 15, 2010 1.5.3 78k0/kd2 ? 52-pin plastic lqfp (10 10) p140/pcl/intp6 p120/intp0/exlvi p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note p121/x1/ocd0a note regc v ss v dd av ss av ref p10/sck10/t x d0 p11/si10/r x d0 p12/so10 p13/t x d6 p14/r x d6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p31/intp2/ocd1a note p32/intp3/ocd1b note p00/ti000 p01/ti010/to00 p02 p03 p130 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p77/kr7 p76/kr6 p75/kr5 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 note products with on-chip debug function only cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 3. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 48 jul 15, 2010 1.5.4 78k0/ke2 ? 64-pin plastic lqfp (fine pitch) (10 10) ? 64-pin plastic lqfp (14 14) ? 64-pin plastic lqfp (12 12) ? 64-pin plastic tqfp (fine pitch) (7 7) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p140/pcl/intp6 p141/buz/intp7 p00/ti000 p01/ti010/to00 p02/so11 note2 p03/si11 note2 p04/sck11 note2 p130 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p77/kr7 p76/kr6 p75/kr5 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p06/to01 note2 /ti011 note2 p05/ssi11 note2 /ti001 note2 p32/intp3/ocd1b note1 av ss av ref p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p53 p52 p51 p50 p31/intp2/ocd1a note1 p120/intp0/exlvi p43 p42 p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note1 p121/x1/ocd0a note1 regc v ss ev ss v dd ev dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 notes 1. products with on-chip debug function only 2. products whose flash memory is at least 48 kb only cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 4. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 49 jul 15, 2010 ? 64-pin plastic flga (5 5) ? 64-pin plastic fbga (4 4) top view bottom view index mark 1 2 hg f e dc ba 3 4 5 6 7 8 h g f e d c b a pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 av ss c1 ani4/p24 e1 p130 g1 p141/buz/intp7 a2 av ref c2 ani3/p23 e2 ani0/p20 g2 p140/pcl/intp6 a3 p11/si10/rxd0 c3 ani7/p27 e3 p03/si11 note 2 g3 p43 a4 p13/txd6 c4 p10/sck10/txd0 e4 p42 g4 reset a5 p16/toh1/intp5 c5 p17/ti50/to50 e5 p77/kr7 g5 regc a6 p53 c6 p30/intp1 e6 p33/ti51/to51/intp4 g6 v ss a7 p51 c7 p31/intp2/ ocd1a note 1 e7 p74/kr4 g7 v dd a8 p32/intp3/ ocd1b note 1 c8 p06/to01 note 2 / ti011 note 2 e8 p76/kr6 g8 p61/sda0 b1 ani5/p25 d1 ani1/p21 f1 p01/ti010/to00 h1 p120/intp0/exlvi b2 ani6/p26 d2 ani2/p22 f2 p00/ti000 h2 p124/xt2/exclks b3 p12/so10 d3 p04/sck11 note 2 f3 p02/so11 note 2 h3 p123/xt1 b4 p15/toh0 d4 p72/kr2 f4 p41 h4 flmd0 b5 p14/rxd6 d5 p70/kr0 f5 p40 h5 p122/x2/exclk/ ocd0b note 1 b6 p52 d6 p71/kr1 f6 p60/scl0 h6 p121/x1/ocd0a note 1 b7 p50 d7 p75/kr5 f7 p62/exscl0 h7 ev ss b8 p05/ssi11 note 2 / ti001 note 2 d8 p73/kr3 f8 p63 h8 ev dd notes 1. product with on-chip debug function only 2. products whose flash memory is at least 48 kb only cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 4. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 50 jul 15, 2010 1.5.5 78k0/kf2 ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p120/intp0/exlvi p47 p46 p45 p44 p43 p42 p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk/ocd0b note p121/x1/ocd0a note regc v ss ev ss v dd ev dd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ss av ref p57 p56 p55 p54 p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p53 p52 p51 p50 p31/intp2/ocd1a note p140/pcl/intp6 p141/buz/busy0/intp7 p142/scka0 p143/sia0 p144/soa0 p145/stb0 p00/ti000 p01/ti010/to00 p02/so11 p03/si11 p04/sck11 p130 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36 p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p64 p65 p66 p67 p77/kr7 p76/kr6 p75/kr5 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p06/ti011/to01 p05/ti001/ssi11 p32/intp3/ocd1b note note products with on-chip debug function only cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f). 4. ani0/p20 to ani7/p27 ar e set in the analog input mode after release of reset. remark for pin identification, see 1.6 pin identification . 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 51 jul 15, 2010 1.6 pin identification ani0 to ani7: analog input av ref : analog reference voltage av ss : analog ground busy0: serial busy input buz: buzzer output ev dd : power supply for port ev ss : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) exlvi: external potential input for low-voltage detector exscl0: external serial clock input flmd0: flash programming mode intp0 to intp7: external interrupt input kr0 to kr7: key return nc: non-connection ocd0a, ocd0b, ocd1a, ocd1b: on chip debug input/output p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p120 to p124: port 12 p130: port 13 p140 to p145: port 14 pcl: programmable clock output regc regulator capacitance reset: reset rxd0, rxd6: receive data sck10, sck11, scka0: se rial clock input/output scl0: serial clock input/output sda0: serial data input/output si10, si11, sia0: se rial data input so10, so11, soa0: serial data output ssi11: serial interface chip select input stb0: serial strobe ti000, ti010, ti001, ti011, ti50, ti51: timer input to00, to01, to50, to51, toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillat or (main system clock) xt1, xt2: crystal oscillator (subsystem clock) 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 52 jul 15, 2010 1.7 block diagram 1.7.1 78k0/kb2 port 0 p00, p01 2 port 1 p10 to p17 port 2 p20 to p23 4 port 3 p30 to p33 4 v ss , ev ss note 2 flmd0 v dd , ev dd note 2 8 power on clear/ low voltage indicator poc/lvi control reset control port 6 p60, p61 2 p120 to p122 3 port 12 exlvi/p120 system control reset x1/p121 x2/exclk/p122 internal high-speed oscillator ani0/p20 to ani3/p23 interrupt control 4 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 serial interface iic0 sda0/p61 scl0/p60 intp5/p16 internal high-speed ram 78k/0 cpu core flash memory 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 serial interface csi10 si10/p11 so10/p12 sck10/p10 internal low-speed oscillator 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 rxd6/p14 (linsel) rxd6/p14 (linsel) linsel on-chip debug note 1 voltage regulator regc ocd0a note 1 /x1, ocd1a note 1 /p31 ocd0b note 1 /x2, ocd1b note 1 /p32 notes 1. available only in the produc ts with on-chip debug function. 2. available only in the 36-pin products. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 53 jul 15, 2010 1.7.2 78k0/kc2 port 0 p00, p01 2 port 1 p10 to p17 port 2 p20 to p25, p26 note 1 , p27 note 1 8 port 3 p30 to p33 4 port 4 v ss flmd0 v dd 8 power-on-clear/ low-voltage indicator poc/lvi control reset control port 6 p60 to p63 4 port 7 p70, p71, p72 note 1 , p73 note 1 , p74 note 2 , p75 note 2 port 12 p120 to p124 port 13 note 2 p130 note 2 6 p40 note 1 , p41 note 1 2 port 14 note 2 p140 note 2 clock output control note 2 pcl/p140 note 2 key return 4 kr0/p70, kr1/p71, kr2/p72 note 1 , kr3/p73 note 1 exlvi/p120 system control reset x1/p121 x2/exclk/p122 xt1/p123 xt2/exclks/p124 ani0/p20 to ani5/p25, ani6/p26 note 1 , ani7/p27 note 1 interrupt control 8 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 serial interface iic0 exscl0/p62 sda0/p61 scl0/p60 intp5/p16 intp6/p140 note 2 internal high-speed ram internal expansion ram note 3 78k/0 cpu core flash memory 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi10 si10/p11 so10/p12 sck10/p10 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 multiplier & divider note 3 on-chip debug note 4 rxd6/p14 (linsel) rxd6/p14 (linsel) linsel 5 ocd0a note 4 /x1, ocd1a note 4 /p31 ocd0b note 4 /x2, ocd1b note 4 /p32 internal low-speed oscillator internal high-speed oscillator voltage regulator regc notes 1. available only in the 44-pin and 48-pin products. 2 available only in the 48-pin products. 3. available only in the products whose flash memory is at least 48 kb. 4. available only in the produc ts with on-chip debug function. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 54 jul 15, 2010 1.7.3 78k0/kd2 port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 v ss flmd0 v dd 8 power on clear/low voltage indicator poc/lvi control reset control port 6 p60 to p63 4 port 7 p70 to p77 port 12 p120 to p124 port 13 p130 8 p40, p41 2 port 14 p140 clock output control pcl/p140 key return 8 kr0/p70 to kr7/p77 exlvi/p120 system control reset x1/p121 x2/exclk/p122 xt1/p123 xt2/exclks/p124 ani0/p20 to ani7/p27 interrupt control 8 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120(linsel) serial interface iic0 exscl0/p62 sda0/p61 scl0/p60 intp5/p16 intp6/p140 internal high-speed ram internal expansion ram note 2 78k/0 cpu core flash memory bank note 1 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi10 si10/p11 so10/p12 sck10/p10 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 multiplier & divider note 2 on-chip debug note 3 rxd6/p14 (linsel) rxd6/p14 linsel 5 voltage regulator regc ocd0a note 3 /x1, ocd1a note 3 /p31 ocd0b note 3 /x2, ocd1b note 3 /p32 internal low-speed oscillator internal high-speed oscillator notes 1. available only in the products whose flash memory is at least 96 kb. 2. available only in the products whose flash memory is at least 48 kb. 3. available only in the produc ts with on-chip debug function. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 55 jul 15, 2010 1.7.4 78k0/ke2 port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 v ss , ev ss flmd0 v dd , ev dd 8 port 6 p60 to p63 4 port 7 p70 to p77 port 12 p120 to p124 port 13 p130 8 p40 to p43 4 p50 to p53 4 port 14 p140, p141 2 buzzer output buz/p141 clock output control pcl/p140 ani0/p20 to ani7/p27 interrupt control 8 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 serial interface iic0 exscl0/p62 sda0/p61 scl0/p60 intp5/p16 intp6/p140, intp7/p141 2 internal high-speed ram internal expansion ram note2 78k/0 cpu core flash memory bank note1 16-bit timer/ event counter 01 note2 to01 note2 /ti011 note2 /p06 ti001 note2 /p05 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi10 si10/p11 so10/p12 sck10/p10 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 serial interface csi11 note2 si11 note2 /p03 so11 note2 /p02 sck11 note2 /p04 ssi11 note2 /p05 power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 system control reset x1/p121 x2/exclk/p122 internal high-speed oscillator xt1/p123 xt2/exclks/p124 multiplier& divider note2 on-chip debug note3 rxd6/p14 (linsel) rxd6/p14 (linsel) linsel 5 ocd0a note3 /x1, ocd1a note3 /p31 ocd0b note3 /x2, ocd1b note3 /p32 internal low-speed oscillator voltage regulator regc notes 1. available only in the products whose flash memory is at least 96 kb. 2. available only in the products whose flash memory is at least 48 kb. 3. available only in the produc ts with on-chip debug function. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 56 jul 15, 2010 1.7.5 78k0/kf2 port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 v ss , ev ss flmd0 v dd , ev dd 8 port 6 p60 to p67 8 port 7 p70 to p77 port 12 p120 to p124 port 13 p130 8 p40 to p47 8 p50 to p57 8 port 14 p140 to p145 6 buzzer output buz/p141 clock output control pcl/p140 voltage regulator regc ani0/p20 to ani7/p27 interrupt control 8 a/d converter av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 serial interface iic0 exscl0/p62 sda0/p61 scl0/p60 intp5/p16 intp6/p140, intp7/p141 2 internal high-speed ram internal expansion ram 78k/0 cpu core flash memory bank note 1 16-bit timer/ event counter 01 to01/ti011/p06 ti001/p05 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi10 si10/p11 so10/p12 sck10/p10 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 serial interface csi11 si11/p03 so11/p02 sck11/p04 ssi11/p05 serial interface csia0 sia0/p143 soa0/p144 scka0/p142 stb0/p145 power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 system control reset x1/p121 ocd0a note 2 /x1, ocd1a note 2 /p31 ocd0b note 2 /x2, ocd1b note 2 /p32 x2/exclk/p122 internal high-speed oscillator xt1/p123 xt2/exclks/p124 multiplier & divider on-chip debug note 2 rxd6/p14 (linsel) rxd6/p14 (linsel) linsel 5 busy0/p141 internal low-speed oscillator notes 1. available only in the products whose flash memory is at least 96 kb. 2. available only in the produc ts with on-chip debug function. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 57 jul 15, 2010 1.8 outline of functions (1/2) 78k0/kb2 78k0/kc2 78k0/kx2 item 30/36 pins 38/44 pins 48 pins flash memory (kb) 8 16 24 32 16 24 32 16 24 32 48 60 high-speed ram (kb) 0.5 0.75 1 1 0.75 1 1 0.75 1 1 1 1 expansion ram (kb) ? ? ? ? ? ? ? ? ? ? 1 2 bank (flash memory) ? power supply voltage standard products, (a) grade products: v dd = 1.8 to 5.5 v, (a2) grade products: v dd = 2.7 to 5.5 v regulator provided minimum instruction execution time 0.1 s (20 mhz: v dd = 2.7 to 5.5 v)/0.4 s (5 mhz: v dd = 1.8 to 5.5 v) note 1 high-speed system 20 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v note 1 main internal high-speed oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v note 1 subsystem ? 32.768 khz (typ.): v dd = 1.8 to 5.5 v note 1 clock internal low-speed oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v note 1 total 23 31 (38 pins)/ 37 (44 pins) 41 port n-ch o.d. (6 v tolerance) 2 4 4 16 bits (tm0) 1 ch 8 bits (tm5) 2 ch 8 bits (tmh) 2 ch watch ? 1 ch timer wdt 1 ch 3-wire csi ? automatic transmit/ receive 3-wire csi ? uart/3-wire csi note 2 1 ch uart supporting lin-bus 1 ch serial interface i 2 c bus 1 ch 10-bit a/d 4 ch 6 ch (38 pins)/ 8 ch (44 pins) 8 ch external 6 7 8 interrupt internal 14 16 key interrupt ? 2 ch (38 pins)/ 4 ch (44 pins) 4 ch reset pin provided poc 1.59 v 0.15 v lvi the detection level of the supply voltage is selectable. reset wdt provided clock output/buzzer output ? clock output only multiplier/divider ? provided on-chip debug function pd78f0503d, 78f0503da only pd78f0513d, 78f0513da only pd78f0515d, 78f0515da only operating ambient temperature standard products, (a) grade products: t a = ?40 to +85 c, (a2) grade products: t a = ?40 to +125 c notes 1. this is applicable to a standar d expanded-specification product ( pd78f05xxa and 78f05xxda). see chapter 30 electrical specifi cations (standard products) to chapter 33 electrical specifications ((a2) grade products: t a : ? 40 to +125 c) for products with othe r specifications and grades. 2. select either of the functions of these alternate-function pins. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 58 jul 15, 2010 (2/2) 78k0/kd2 78k0/ke2 78k0/kf2 78k0/kx2 item 52 pins 64 pins 80 pins flash memory (kb) 16 24 32 48 60 96 128 16 24 32 48 60 96 128 48 60 96 128 high-speed ram (kb) 0.75 1 1 1 1 1 1 0.75 1 1 1 1 1 1 1 1 1 1 expansion ram (kb) ? ? ? 1 2 4 6 ? ? ? 1 2 4 6 1 2 4 6 bank (flash memory) ? 4 6 ? 4 6 ? 4 6 power supply voltage standard products, (a) grade products: v dd = 1.8 to 5.5 v, (a2) grade products: v dd = 2.7 to 5.5 v regulator provided minimum instruction execution time 0.1 s (20 mhz: v dd = 2.7 to 5.5 v)/0.4 s (5 mhz: v dd = 1.8 to 5.5 v) note 1 high-speed system 20 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v note 1 main internal high-speed oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v note 1 subsystem 32.768 khz (typ.): v dd = 1.8 to 5.5 v note 1 clock internal low-speed oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v note 1 total 45 55 71 port n-ch o.d. (6 v tolerance) 4 4 4 16 bits (tm0) 1 ch 2 ch 8 bits (tm5) 2 ch 8 bits (tmh) 2 ch watch 1 ch timer wdt 1 ch 3-wire csi ? 1 ch automatic transmit/ receive 3-wire csi ? 1 ch uart/3-wire csi note 1 ch uart supporting lin-bus 1 ch serial interface i 2 c bus 1 ch 10-bit a/d 8 ch external 8 9 interrupt internal 16 19 20 key interrupt 8 ch reset pin provided poc 1.59 v 0.15 v lvi the detection level of the supply voltage is selectable. reset wdt provided clock output/buzzer output clock output only provided multiplier/divider ? provided ? provided on-chip debug function pd78f0527d, 78f0527da only pd78f0537d, 78f0537da only pd78f0547d, 78f0547da only operating ambient temperature standard products, (a) grade products: t a = ?40 to +85 c, (a2) grade products: t a = ?40 to +125 c notes 1. this is applicable to a standar d expanded-specification product ( pd78f05xxa and 78f05xxda). see chapter 30 electrical specifi cations (standard products) to chapter 33 electrical specifications ((a2) grade products: t a : ? 40 to +125 c) for products with othe r specifications and grades. 2. select either of the functions of these alternate-function pins. 78k0/kx2 chapter 1 outline r01uh0008ej0401 rev.4.01 59 jul 15, 2010 an outline of the timer is shown below. 16-bit timer/ event counters 00 and 01 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 tm00 tm01 tm50 tm51 tmh0 tmh1 watch timer watchdog timer interval timer 1 channel 1 channel 1 c hannel 1 channel 1 channel 1 channel 1 c hannel note 1 ? external event counter 1 channel 1 channel 1 channel 1 channel ? ? ? ? ppg output 1 output 1 output ? ? ? ? ? ? pwm output ? ? 1 output 1 output 1 output 1 output ? ? pulse width measurement 2 inputs 2 inputs ? ? ? ? ? ? square-wave output 1 output 1 output 1 output 1 output 1 output 1 output ? ? carrier generator ? ? ? ? ? 1 output nore 2 ? ? timer output ? ? ? ? ? ? 1 channel nore 1 ? function watchdog timer ? ? ? ? ? ? ? 1 channel interrupt source 2 2 1 1 1 1 1 ? notes 1. in the watch timer, the watch timer function and interval timer function can be used simultaneously. 2. tm51 and tmh1 can be used in combination as a carrier generator mode. remark the timer mounted depends on the product. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 16-bit timer/event counter 00 16-bit timer/event counter 01 ? 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer h0 8-bit timer h1 watch timer ? watchdog timer : mounted, ? : not mounted 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 60 jul 15, 2010 chapter 2 pin functions 2.1 pin function list pin i/o buffer power supplies depend on the product. the relati onship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies (av ref , v dd ) ? 78k0/kb2: 30-pin plastic ssop (7.62 mm (300)) ? 78k0/kc2: 38-pin plastic ssop (7.62 mm (300)), 44-pin plastic lqfp (10x10), 48-pin plastic lqfp (fine pitch) (7x7) ? 78k0/kd2: 52-pin plastic lqfp (10x10) power supply corresponding pins av ref p20 to p27 v dd pins other than p20 to p27 table 2-2. pin i/o buffer power supplies (av ref , ev dd , v dd ) ? 78k0/kb2: 36-pin plastic flga (4x4) ? 78k0/ke2: 64-pin plastic lqfp (fine pitch) (10x10), 64-pi n plastic lqfp (14x14), 64-pin plastic lqfp (12x12), 64-pin plastic tqfp (fine pitch) (7x7), 64-pin plastic flga (5x5), 64-pin plastic fbga (4x4) ? 78k0/kf2: 80-pin plastic lqfp (14x14), 80- pin plastic lqfp (fine pitch) (12x12) power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 and p121 to p124 v dd ? p121 to p124 ? pins other than port 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 61 jul 15, 2010 2.1.1 78k0/kb2 (1) port functions: 78k0/kb2 function name i/o function after reset alternate function p00 ti000 p01 i/o port 0. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti010/to00 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p23 i/o port 2. 4-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani3 p30 intp1 p31 intp2/ocd1a note p32 intp3/ocd1b note p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port intp4/ti51/to51 p60 scl0 p61 i/o port 6. 2-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p120 intp0/exlvi p121 x1/ocd0a note p122 i/o port 12. 3-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port x2/exclk/ ocd0b note note pd78f0503d and 78f0503da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 62 jul 15, 2010 (2) non-port functions (1/2): 78k0/kb2 function name i/o function after reset alternate function ani0 to ani3 input a/d converter analog input analog input p20 to p23 exlvi input potential input for external low-voltage detection input port p120/intp0 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note intp3 p32/ocd1b note intp4 p33/ti51/to51 intp5 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p16/toh1 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? reset input system reset input ? ? rxd0 input serial data input to uart0 input port p11/si10 rxd6 input serial data input to uart6 input port p14 txd0 output serial data output from uart0 input port p10/sck10 txd6 output serial data output from uart6 input port p13 sck10 i/o clock input/output for csi10 p10/txd0 si10 input serial data input to csi10 p11/rxd0 so10 output serial data output from csi10 input port p12 scl0 clock input/output for i 2 c p60 sda0 i/o serial data i/o for i 2 c input port p61 ti000 input external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 input port p00 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input port p01/to00 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 to00 output 16-bit timer/event counter 00 output input port p01/ti010 to50 8-bit timer/event counter 50 output p17/ti50 to51 output 8-bit timer/event counter 51 output input port p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 x1 ? input port p121/ocd0a note x2 ? connecting resonator for main system clock input port p122/exclk/ocd0b note exclk input external clock input for ma in system clock input port p122/x2/ocd0b note note pd78f0503d and 78f0503da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 63 jul 15, 2010 (2) non-port functions (2/2): 78k0/kb2 function name i/o function after reset alternate function v dd ? for 30-pin products: positive power supply for pins other than p20 to p23 for 36-pin products: positive power supply for p121, p122, and non-port pins ? ? ev dd note 1 ? for 36-pin products: positive power supply for port pins other than p20 to p23, p121, and p122. make the same potential as v dd . ? ? av ref ? a/d converter reference voltage input and positive power supply for p20 to p23 and a/d converter ? ? v ss ? for 30-pin products: ground potential for pins other than p20 to p23 for 36-pin products: ground potential for p121, p122, and non-port pins ? ? ev ss note 1 ? for 36-pin products: ground potential for port pins other than p20 to p23, p121, and p122. make the same potential as v ss . ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? ocd0a note 2 p121/x1 ocd1a note 2 input p31/intp2 ocd0b note 2 p122/x2/exclk ocd1b note 2 ? connection for on-chip debug mode setting pins ( pd78f0503d and 78f0503da only) input port p32/intp3 notes 1. 36-pin products only 2. pd78f0503d and 78f0503da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 64 jul 15, 2010 2.1.2 78k0/kc2 (1) port functions (1/2): 78k0/kc2 function name i/o function after reset alternate function p00 ti000 p01 i/o port 0. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti010/to00 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p25 ani0 to ani5 p26 note 1 , p27 note 1 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani6 note 1 , ani7 note 1 p30 intp1 p31 intp2/ocd1a note 2 p32 intp3/ocd1b note 2 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti51/to51/intp4 p40 note 1 , p41 note 1 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 i/o port 6. 4-bit i/o port. output of p60 to p63 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? p70, p71 kr0, kr1 p72 note 1 , p73 note 1 kr2 note 1 , kr3 note 1 p74 note 3 , p75 note 3 i/o port 7. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? notes 1. 44-pin and 48-pin products only for the 38-pin products, be sure to set bits 6 and 7 of pm 2 to ?1?, and bits 0 and 1 of pm4, bits 2 and 3 of pm7, bits 6 and 7 of p2, bits 0 and 1 of p4, and bits 2 and 3 of p7 to ?0?. 2. pd78f0513d, 78f0513da, 78f0515d and 78f0515da (p roduct with on-chip debug function) only 3. 48-pin products only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 65 jul 15, 2010 (1) port functions (2/2): 78k0/kc2 function name i/o function after reset alternate function p120 intp0/exlvi p121 x1/ocd0a note 1 p122 x2/exclk/ocd0b note 1 p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks p130 note 2 output port 13. 1-bit output-only port. output port ? p140 note 2 i/o port 14. 1-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port pcl/intp6 note 2 notes 1. pd78f0513d, 78f0513da, 78f0515d and 78f0515da (p roduct with on-chip debug function) only 2. 48-pin products only (2) non-port functions (1/2): 78k0/kc2 function name i/o function after reset alternate function ani0 to ani5 p20 to p25 ani6 note 1 , ani7 note 1 input a/d converter analog input analog input p26 note 1 , p27 note 1 exlvi input potential input for external low-voltage detection input port p120/intp0 exscl0 input external clock input for serial interface. to input an external clock, input a clock of 6.4 mhz. input port p62 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note 2 intp3 p32/ocd1b note 2 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 note 3 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p140/pcl note 3 kr0, kr1 p70, p71 kr2 note 1 , kr3 note 1 input key interrupt input input port p72 note 1 , p73 note 1 pcl note 3 output clock output (for trimming of high-speed system clock, subsystem clock) input port p140/intp6 note 3 notes 1. 44-pin and 48-pin products only for the 38-pin products, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 2 and 3 of pm7, bits 6 and 7 of p2, and bits 2 and 3 of p7 to ?0?. 2. pd78f0513d, 78f0513da, 78f0515d and 78f0515da (p roduct with on-chip debug function) only 3. 48-pin products only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 66 jul 15, 2010 (2) non-port functions (2/2): 78k0/kc2 function name i/o function after reset alternate function regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? reset input system reset input ? ? rxd0 input serial data input to uart0 input port p11/si10 rxd6 input serial data input to uart6 input port p14 sck10 i/o clock input/output for csi10 input port p10/txd0 scl0 i/o clock input/output for i 2 c input port p60 sda0 i/o serial data i/o for i 2 c input port p61 si10 input serial data input to csi10 input port p11/rxd0 so10 output serial data output from csi10 input port p12 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input port p01/to00 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 to00 output 16-bit timer/event counter 00 output input port p01/ti010 to50 8-bit timer/event counter 50 output p17/ti50 to51 output 8-bit timer/event counter 51 output input port p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 txd0 output serial data output from uart0 input port p10/sck10 txd6 output serial data output from uart6 input port p13 x1 ? p121/ocd0a note x2 ? connecting resonator for main system clock input port p122/exclk/ ocd0b note exclk input external clock input for main system clock input port p122/x2/ ocd0b note xt1 ? input port p123 xt2 ? connecting resonator fo r subsystem clock input port p124/exclks exclks input external clock input fo r subsystem clock input port p124/xt2 v dd ? positive power supply for pins other than p20 to p27 ? ? av ref ? a/d converter reference voltage input and positive power supply for p20 to p27 and a/d converter ? ? v ss ? ground potential for pins other than p20 to p27 ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? ocd0a note p121/x1 ocd1a note input p31/intp2 ocd0b note p122/x2/exclk ocd1b note ? connection for on-chip debug mode setting pins ( pd78f0513d, 78f0513da, 78f0515d and 78f0515da only) input port p32/intp3 note pd78f0513d, 78f0513da, 78f0515d and 78f0515da (p roduct with on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 67 jul 15, 2010 2.1.3 78k0/kd2 (1) port functions (1/2): 78k0/kd2 function name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 ? p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani7 p30 intp1 p31 intp2/ocd1a note p32 intp3/ocd1b note p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti51/to51/intp4 p40, p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 i/o port 6. 4-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr0 to kr7 p120 intp0/exlvi p121 x1/ocd0a note p122 x2/exclk/ ocd0b note p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks note pd78f0527d and 78f0527da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 68 jul 15, 2010 (1) port functions (2/2): 78k0/kd2 function name i/o function after reset alternate function p130 output port 13. 1-bit output-only port. output port ? p140 i/o port 14. 1-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port pcl/intp6 (2) non-port functions (1/2): 78k0/kd2 function name i/o function after reset alternate function ani0 to ani7 input a/d converter analog input analog input p20 to p27 exlvi input potential input for external low-voltage detection input port p120/intp0 exscl0 input external clock input for i 2 c to input an external clock, input a clock of 6.4 mhz. input port p62 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note intp3 p32/ocd1b note intp4 p33/ti51/to51 intp5 p16/toh1 intp6 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p140/pcl kr0 to kr7 input key interrupt input input port p70 to p77 pcl output clock output (for trimming of high-speed system clock, subsystem clock) input port p140/intp6 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? reset input system reset input ? ? rxd0 serial data input to uart0 p11/si10 rxd6 input serial data input to uart6 input port p14 sck10 clock input/output for csi10 p10/txd0 scl0 i/o clock input/output for i 2 c input port p60 sda0 i/o serial data i/o for i 2 c input port p61 si10 input serial data input to csi10 input port p11/rxd0 so10 output serial data output from csi10 input port p12 txd0 serial data output from uart0 p10/sck10 txd6 output serial data output from uart6 input port p13 note pd78f0527d and 78f0527da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 69 jul 15, 2010 (2) non-port functions (2/2): 78k0/kd2 function name i/o function after reset alternate function ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input port p01/to00 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 to00 output 16-bit timer/event counter 00 output input port p01/ti010 to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 x1 ? p121/ocd0a note x2 ? connecting resonator for main system clock input port p122/exclk/ocd0b note exclk input external clock input for ma in system clock input port p122/x2/ocd0b note xt1 ? input port p123 xt2 ? connecting resonator fo r subsystem clock input port p124/exclks exclks input external clock input fo r subsystem clock input port p124/xt2 v dd ? positive power supply for pins other than p20 to p27 ? ? av ref ? a/d converter reference voltage input and positive power supply for p20 to p27 and a/d converter ? ? v ss ? ground potential for pins other than p20 to p27 ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? ocd0a note p121/x1 ocd1a note input p31/intp2 ocd0b note p122/x2/exclk ocd1b note ? connection for on-chip debug mode setting pins ( pd78f0527d and 78f0527da only) input port p32/intp3 note pd78f0527d and 78f0527da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 70 jul 15, 2010 2.1.4 78k0/ke2 (1) port functions (1/2): 78k0/ke2 function name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note 1 p03 si11 note 1 p04 sck11 note 1 p05 ti001 note 1 / ssi11 note 1 p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti011 note 1 / to01 note 1 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani7 p30 intp1 p31 intp2/ocd1a note 2 p32 intp3/ocd1b note 2 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti51/to51/intp4 p40 to p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 i/o port 6. 4-bit i/o port. output of p60 to p63 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? notes 1. available only in the products whose flash memory is at least 48 kb. 2. pd78f0537d and 78f0537da (product with on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 71 jul 15, 2010 (1) port functions (2/2): 78k0/ke2 function name i/o function after reset alternate function p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr0 to kr7 p120 intp0/exlvi p121 x1/ocd0a note p122 x2/exclk/ocd0b note p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks p130 output port 13. 1-bit output-only port. output port ? p140 pcl/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port buz/intp7 note pd78f0537d and 78f0537da (product wit h on-chip debug function) only (2) non-port functions (1/3): 78k0/ke2 function name i/o function after reset alternate function ani0 to ani7 input a/d converter analog input analog input p20 to p27 buz output buzzer output input port p141/intp7 exlvi input potential input for external low-voltage detection input port p120/intp0 exscl0 input external clock input for i 2 c. to input an external clock, input a clock of 6.4 mhz. input port p62 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note intp3 p32/ocd1b note intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p141/buz kr0 to kr7 input key interrupt input input port p70 to p77 pcl output clock output (for trimming of high-speed system clock, subsystem clock) input port p140/intp6 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? note pd78f0537d and 78f0537da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 72 jul 15, 2010 (2) non-port functions (2/3): 78k0/ke2 function name i/o function after reset alternate function reset input system reset input ? ? rxd0 serial data input to uart0 p11/si10 rxd6 input serial data input to uart6 input port p14 sck10 clock input/output for csi10 p10/txd0 sck11 note 1 i/o clock input/output for csi11 input port p04 scl0 i/o clock input/output for i 2 c input port p60 sda0 i/o serial data i/o for i 2 c input port p61 si10 serial data input to csi10 p11/rxd0 si11 note 1 input serial data input to csi11 input port p03 so10 serial data output from csi10 p12 so11 note 1 output serial data output from csi11 input port p02 ssi11 note 1 input chip select input to csi11 input port p05/ti001 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 note 1 external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 note 1 ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 note 1 input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input port p06/to01 note 1 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 to00 16-bit timer/event counter 00 output p01/ti010 to01 note 1 output 16-bit timer/event counter 01 output input port p06/ti011 note 1 to50 8-bit timer/event counter 50 output p17/ti50 to51 output 8-bit timer/event counter 51 output input port p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 txd0 serial data output from uart0 p10/sck10 txd6 output serial data output from uart6 input port p13 x1 ? p121/ocd0a note 2 x2 ? connecting resonator for main system clock input port p122/exclk/ ocd0b note 2 exclk input external clock input for main system clock input port p122/x2/ ocd0b note 2 xt1 ? input port p123 xt2 ? connecting resonator fo r subsystem clock input port p124/exclks exclks input external clock input fo r subsystem clock input port p124/xt2 notes 1. available only in the products whose flash memory is at least 48 kb. 2. pd78f0537d and 78f0537da (product with on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 73 jul 15, 2010 (2) non-port functions (3/3): 78k0/ke2 function name i/o function after reset alternate function v dd ? positive power supply for p121 to p124 and other than ports ? ? ev dd ? positive power supply for po rts other than p20 to p27 and p121 to p124. make ev dd the same potential as v dd . ? ? av ref ? a/d converter reference voltage input and positive power supply for p20 to p27 and a/d converter ? ? v ss ? ground potential for p121 to p124 and other than ports ? ? ev ss ? ground potential for ports other than p20 to p27 and p121 to p124. make ev ss the same potential as v ss . ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? ocd0a note p121/x1 ocd1a note input p31/intp2 ocd0b note p122/x2/exclk ocd1b note ? connection for on-chip debug mode setting pins ( pd78f0537d and 78f0537da only) input port p32/intp3 note pd78f0537d and 78f0537da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 74 jul 15, 2010 2.1.5 78k0/kf2 (1) port functions (1/2): 78k0/kf2 function name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 p03 si11 p04 sck11 p05 ti001/ssi11 p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti011/to01 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. analog input ani0 to ani7 p30 intp1 p31 intp2/ocd1a note p32 intp3/ocd1b note p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti51/to51/intp4 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 exscl0 p63 to p67 i/o port 6. 8-bit i/o port. output of p60 to p63 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. only for p64 to p67, use of an on-chip pull-up resistor can be specified by a software setting. input port ? note pd78f0547d and 78f0547da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 75 jul 15, 2010 (1) port functions (2/2): 78k0/kf2 function name i/o function after reset alternate function p70 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr0 to kr7 p120 intp0/exlvi p121 x1/ocd0a note p122 x2/exclk/ocd0b note p123 xt1 p124 i/o port 12. 5-bit i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks p130 output port 13. 1-bit output-only port. output port ? p140 pcl/intp6 p141 buz/busy0/intp7 p142 scka0 p143 sia0 p144 soa0 p145 i/o port 14. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port stb0 note pd78f0547d and 78f0547da (product wit h on-chip debug function) only (2) non-port functions (1/3): 78k0/kf2 function name i/o function after reset alternate function ani0 to ani7 input a/d converter analog input analog input p20 to p27 busy0 input csia0 busy input input port p141/buz/intp7 buz output buzzer output input port p141/busy0/intp7 exlvi input potential input for external low-voltage detection input port p120/intp0 exscl0 input external clock input for i 2 c. to input an external clock, input a clock of 6.4 mhz. input port p62 flmd0 ? flash memory programming mode setting ? ? intp0 p120/exlvi intp1 p30 intp2 p31/ocd1a note intp3 p32/ocd1b note intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p141/buz/busy0 kr0 to kr7 input key interrupt input input port p70 to p77 note pd78f0547d and 78f0547da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 76 jul 15, 2010 (2) non-port functions (2/3): 78k0/kf2 function name i/o function after reset alternate function pcl output clock output (for trimming of high-speed system clock, subsystem clock) input port p140/intp6 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? reset input system reset input ? ? rxd0 input serial data input to uart0 input port p11/si10 rxd6 input serial data input to uart6 input port p14 sck10 p10/txd0 sck11 i/o clock input/output for csi10, csi11 input port p04 scka0 i/o clock input/output for csia0 input port p142 scl0 i/o clock input/output for i 2 c input port p60 sda0 i/o serial data i/o for i 2 c input port p61 si10 p11/rxd0 si11 input serial data input to csi10, csi11 input port p03 sia0 input serial data input to csia0 input port p143 so10 p12 so11 output serial data output from csi10, csi11 input port p02 soa0 output serial data output from csia0 input port p144 ssi11 input chip select input to csi11 input port p05/ti001 stb0 output strobe output from csia0 input port p145 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 input external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 input port p05/ssi11 ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input port p06/to01 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input port p33/to51/intp4 to00 16-bit timer/event counter 00 output p01/ti010 to01 output 16-bit timer/event counter 01 output input port p06/ti011 to50 8-bit timer/event counter 50 output p17/ti50 to51 output 8-bit timer/event counter 51 output input port p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input port p16/intp5 txd0 output serial data output from uart0 input port p10/sck10 txd6 output serial data output from uart6 input port p13 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 77 jul 15, 2010 (2) non-port functions (3/3): 78k0/kf2 function name i/o function after reset alternate function x1 ? input port p121/ocd0a note x2 ? connecting resonator for main system clock input port p122/exclk/ocd0b note exclk input external clock input for ma in system clock input port p122/x2/ocd0b note xt1 ? input port p123 xt2 ? connecting resonator fo r subsystem clock input port p124/exclks exclks input external clock input fo r subsystem clock input port p124/xt2 v dd ? positive power supply for p121 to p124 and other than ports ? ? ev dd ? positive power supply for po rts other than p20 to p27 and p121 to p124. make ev dd the same potential as v dd . ? ? av ref ? a/d converter reference voltage input and positive power supply for p20 to p27 and a/d converter ? ? v ss ? ground potential for p121 to p124 and other than ports ? ? ev ss ? ground potential for ports other than p20 to p27 and p121 to p124. make ev ss the same potential as v ss . ? ? av ss ? a/d converter ground potential. make the same potential as v ss . ? ? ocd0a note p121/x1 ocd1a note input p31/intp2 ocd0b note p122/x2/exclk ocd1b note ? connection for on-chip debug mode setting pins ( pd78f0547d and 78f0547da only) input port p32/intp3 note pd78f0547d and 78f0547da (product wit h on-chip debug function) only 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 78 jul 15, 2010 2.2 description of pin functions remark the pins mounted depend on the product. see 1.4 ordering information and 2.1 pin function list . 2.2.1 p00 to p06 (port 0) p00 to p06 function as an i/o port. these pins also function as timer i/o, serial interf ace data i/o, clock i/o, and chip select input. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p00/ti000 p01/ti010/to00 p02/so11 ? p02 note p02 note p03/si11 ? p03 note p03 note p04/sck11 ? ? p04 note p05/ti001/ssi11 ? ? p05 note p06/ti011/to01 ? ? p06 note note the 78k0/ke2 products whose flash memory is less than 32 kb and 78k0/kd2 products are only provided with port functions and not alternate functions. remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as an i/o port. p00 to p06 can be set to input or output port in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o, serial inte rface data i/o, clock i/o, and chip select input. (a) ti000, ti001 these are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture regist ers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 these are the pins for inputting a capture trigger signa l to the capture register (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 these are timer output pins of 16- bit timer/event counters 00 and 01. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 79 jul 15, 2010 (d) si11 this is a serial data input pi n of serial interface csi11. (e) so11 this is a serial data output pin of serial interface csi11. (f) sck11 this is a serial clock i/o pin of serial interface csi11. (g) ssi11 this is a chip select input pin of serial interface csi11. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an i/o port. these pins also function as pins for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an i/o port. p10 to p17 can be set to input or output port in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial data input pi n of serial interface csi10. (b) so10 this is a serial data output pin of serial interface csi10. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 80 jul 15, 2010 (c) sck10 this is a serial clock i/o pin of serial interface csi10. (d) rxd0 this is a serial data input pi n of serial interface uart0. (e) rxd6 this is a serial data input pi n of serial interface uart6. (f) txd0 this is a serial data output pin of serial interface uart0. (g) txd6 this is a serial data output pin of serial interface uart6. (h) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (i) to50 this is a timer output pin of 8-it timer/event counter 50. (j) toh0, toh1 these are the timer output pins of 8-bit timers h0 and h1. (k) intp5 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 81 jul 15, 2010 2.2.3 p20 to p27 (port 2) p20 to p27 function as an i/o port. these pins also function as pins for a/d converter analog input. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 ? p25/ani5 ? p26/ani6 ? note p27/ani7 ? note note this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin pr oducts, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an i/o port. p20 to p27 can be set to input or output port in 1-bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as a/d converter analog input pins (ani 0 to ani7). when using these pins as analog input pins, see (5) ani0/p20 to ani7/p27 in 13.6 cautions for a/d converter . caution ani0/p20 to ani 7/p27 are set in the analog in put mode after release of reset. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 82 jul 15, 2010 2.2.4 p30 to p33 (port 3) p30 to p33 function as an i/o port. these pins also function as pins for external interrupt request input and timer i/o. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p30/intp1 p31/intp2/ ocd1a note p32/intp3/ ocd1b note p33/intp4/ti51/ to51 note ocd1a and ocd1b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as an i/o port. p30 to p33 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interrupt request input and timer i/o. (a) intp1 to intp4 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (c) to51 this is a timer output pin from 8-bit timer/event counter 51. caution 1. in the product with an on-chip debug function ( pd78f05xxd and 78f05xxda), be sure to pull the p31/intp2/ocd1a pin down before a reset release, to prevent malfunction. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 83 jul 15, 2010 caution 2. process the p31/intp2/ocd1a pin of the products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory progra mmer or an on-chip debug emulator. p31/intp2/ocd1a flash memory programmer connection during reset connect to ev ss note via a resistor. on-chip debug emulator connection (when it is not used as an on-chip debug mode setting pin) during reset released input: connect to ev dd note or ev ss note via a resistor. output: leave open. note with products without an ev ss pin, connect them to v ss . with products without an ev dd pin, connect them to v dd . remark p31 and p32 of the product wit h an on-chip debug function ( pd78f05xxd and 78f05xxda) can be used as on-chip debug mode setting pins (ocd1a and ocd1b) when the on-chip debug function is used. for how to connect an on-c hip debug emulator (qb-mini2), see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only). 2.2.5 p40 to p47 (port 4) p40 to p47 function as an i/o port. p40 to p47 can be set to input or output port in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be sp ecified by pull-up resistor option register 4 (pu4). 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p40 ? note p41 ? note p42 ? ? p43 ? ? p44 ? ? ? p45 ? ? ? p46 ? ? ? p47 ? ? ? note this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin pr oducts, be sure to set bits 0 and 1 of pm4 and p4 to ?0?. remark : mounted, ? : not mounted 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 84 jul 15, 2010 2.2.6 p50 to p57 (port 5) p50 to p57 function as an i/o port. p50 to p57 can be set to input or output port in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be sp ecified by pull-up resistor option register 5 (pu5). 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p50 ? p51 ? p52 ? p53 ? p54 ? ? p55 ? ? p56 ? ? p57 ? ? remark : mounted, ? : not mounted 2.2.7 p60 to p67 (port 6) p60 to p67 function as an i/o port. these pins also function as pins for serial interface data i/o, clock i/ o, and external clock input. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p60/scl0 p61/sda0 p62/exscl0 ? p63 ? p64 ? ? p65 ? ? p66 ? ? p67 ? ? remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 85 jul 15, 2010 (1) port mode p60 to p67 function as an i/o port. p60 to p67 can be set to input port or output port in 1-bit units using port mode register 6 (pm6). only for p64 to p67, use of an on-chi p pull-up resistor can be specif ied by pull-up resistor option register 6 (pu6). output of p60 to p63 is n-ch open-drain output (6 v tolerance). (2) control mode p60 to p67 function as serial interface dat a i/o, clock i/o, and external clock input. (a) sda0 this is a serial data i/o pin for serial interface iic0. (b) scl0 this is a serial clock i/o pi n for serial interface iic0. (c) exscl0 this is an external clock input pin to serial interface iic0. to input an external clock, input a clock of 6.4 mhz. 2.2.8 p70 to p77 (port 7) p70 to p77 function as an i/o port. these pins also function as key interrupt input pins. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p70/kr0 ? p71/kr1 ? p72/kr2 ? note 1 p73/kr3 ? note 1 p74/kr4 ? p74 note 2 p75/kr5 ? p75 note 2 p76/kr6 ? ? p77/kr7 ? ? notes 1. this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin products, be sure to set bits 2 and 3 of pm7 and p7 to ?0?. 2. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. the 48-pin products are only provided with port functions and not alternate functions. remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 86 jul 15, 2010 (1) port mode p70 to p77 function as an i/o port. p70 to p77 can be set to input or output port in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input pins. (a) kr0 to kr7 these are the key interrupt input pins. 2.2.9 p120 to p124 (port 12) p120 to p124 function as an i/o port. these pins also func tion as pins for external in terrupt request input, potential input for external low-voltage detection, connecting resonato r for main system clock, connecting resonator for subsystem clock, external clock input for ma in system clock, and external clo ck input for subsystem clock. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p120/intp0/exlvi p121/x1/ocd0a note p122/x2/exclk/ ocd0b note p123/xt1 ? p124/xt2/exclks ? note ocd0a and ocd0b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. (1) port mode p120 to p124 function as an i/o port. p 120 to p124 can be set to input or output port using port mode register 12 (pm12). only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 to p124 function as pins for external interrupt reques t input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonat or for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. (a) intp0 this functions as an external interrupt request input (int p0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 87 jul 15, 2010 (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. (d) exclk this is an external clock inpu t pin for main system clock. (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. (f) exclks this is an external clock in put pin for subsystem clock. caution process the p121/x1/ocd0a pin of the pr oducts mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. p121/x1/ocd0a flash memory programmer connection during reset connect to v ss via a resistor. on-chip debug emulator connection (when it is not used as an on-chip debug mode setting pin) during reset released input: connect to v dd or v ss via a resistor. output: leave open. remark x1 and x2 of the product with an on-chip debug function ( pd78f05xxd and 78f05xxda) can be used as on-chip debug mode setting pins (ocd0a and ocd0b) when the on-chip debug function is used. for how to connect an on-c hip debug emulator (qb-mini2), see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only). 2.2.10 p130 (port 13) p130 functions as an output-only port. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p130 ? note note this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. remarks 1. when the device is reset, p130 outputs a low level. therefore, to output a high level from p130 before the device is reset, the output signal of p130 can be used as a pseudo reset signal of the cpu (see the figure for remark in 5.2.10 port 13 ). 2. : mounted, ? : not mounted 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 88 jul 15, 2010 2.2.11 p140 to p145 (port 14) p140 to p145 function as an i/o port. these pins also func tion as external interrupt re quest input, clock output, buzzer output, serial interface data i/o, clock i/o, busy input, and strobe output pins. 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p140/pcl/intp6 ? note 1 p141/buz/busy0/ intp7 ? ? ? p141/buz/intp7 note 2 p142/scka0 ? ? ? ? p143/sia0 ? ? ? ? p144/soa0 ? ? ? ? p145/stb0 ? ? ? ? notes 1. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. 2. the 78k0/ke2 products are not prov ided with the busy0 input function. remark : mounted, ? : not mounted the following operation modes can be specified in 1-bit units. (1) port mode p140 to p145 function as an i/o port. p140 to p145 can be set to input or output port in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor ca n be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 to p145 function as external interrupt request inpu t, clock output, buzzer output, se rial interface data i/o, clock i/o, busy input, and strobe output pins. (a) intp6, intp7 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pcl this is a clock output pin. (c) buz this is a buzzer output pin. (d) busy0 this is a serial interface csia0 busy input pin. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 89 jul 15, 2010 (e) sia0 this is a serial interface csia0 serial data input pin. (f) soa0 this is a serial interface csia0 serial data output pin. (g) scka0 this is a serial interface csia0 serial clock i/o pin. (h) stb0 this is a serial interface csia0 strobe output pin. 2.2.12 av ref , av ss , v dd , ev dd , v ss , ev ss 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 av ref av ss v dd ev dd note ? v ss ev ss note ? note this is not mounted onto 30- pin products of the 78k0/kb2. remark : mounted, ? : not mounted (a) av ref this is the a/d converter reference voltage input pin and the positive power supply pin of p20 to p27 and a/d converter. when the a/d converter is not used, connect this pin directly to ev dd or v dd note . note make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. (b) av ss this is the a/d converter ground potent ial pin. even when the a/d converter is not used, always use this pin with the same potential as the v ss pin. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 90 jul 15, 2010 (c) v dd and ev dd v dd is the positive power supply pin for p121 to p124 and other than ports note . ev dd is the positive power supply pin for ports other than p20 to p27 and p121 to p124. always make ev dd the same potential as v dd . note with products that are not mounted with an ev dd pin, use v dd as a positive power supply pin other than p20 to p27. (d) v ss and ev ss v ss is the ground potential pin for p121 to p124 and other than ports. ev ss is the ground potential pin for ports ot her than p20 to p27 and p121 to p124. always make ev ss the same potential as v ss . note with products that ar e not mounted with an ev ss pin, use v ss as a ground potential pin other than p20 to p27. 2.2.13 reset this is the active-low system reset input pin. 2.2.14 regc this is the pin for connecting regulator output (2.5 v) stab ilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f). regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.15 flmd0 this is a pin for setting flash memory programming mode. connect flmd0 to ev ss or v ss in the normal operation mode. in flash memory programming mode, connect this pin to the flash memory programmer. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 91 jul 15, 2010 2.3 pin i/o circuits and recomme nded connection of unused pins table 2-3 shows the types of pin i/o circuits and the recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuit of each type. remark the pins mounted depend on the product. see 1.5 ordering information (top view) and 2.1 pin function list . table 2-3. pin i/o circuit types (1/3) pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 5-aq p02/so11 5-ag p03/si11 p04/sck11 p05/ti001/ssi11 p06/ti011/to01 note 1 p10/sck10/txd0 p11/si10/rxd0 5-aq p12/so10 p13/txd6 5-ag p14/rxd6 5-aq p15/toh0 5-ag p16/toh1/intp5 p17/ti50/to50 5-aq input: independently connect to ev dd or ev ss via a resistor. output: leave open. ani0/p20 to ani7/p27 note 2 11-g i/o < digital input setting and analog input setting> independently connect to av ref or av ss via a resistor. 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 92 jul 15, 2010 table 2-3. pin i/o circuit types (2/3) pin name i/o circuit type i/o recommended connection of unused pins p30/intp1 p31/intp2/ocd1a note 1 p32/intp3/ocd1b p33/ti51/to51/intp4 5-aq p40 to p47 p50 to p57 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p60/scl0 p61/sda0 p62/exscl0 13-ai p63 13-p input: independently connect to ev dd or ev ss via a resistor, or connect directly to ev ss . output: leave this pin open at low-level output after clearing the output latch of the port to 0. p64 to p67 5-ag p70/kr0 to p77/kr7 p120/intp0/exlvi 5-aq input: independently connect to ev dd or ev ss via a resistor. output: leave open. p121/x1/ocd0a notes 1, 2 p122/x2/exclk/ ocd0b notes 2 p123/xt1 note 2 p124/xt2/exclks note 2 37 i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p130 3-c output leave open. notes 1. process the p31/intp2/ocd1a and p121/x1/ocd0a pi ns of the products mount ed with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. p31/intp2/ocd1a p121/x1/ocd0a flash memory programmer connection during reset connect to ev ss via a resistor. connect to v ss via a resistor. on-chip debug emulator connection (when it is not used as an on-chip debug mode setting pin) during reset released input: connect to ev dd or ev ss via a resistor. output: leave open. input: connect to v dd or v ss via a resistor. output: leave open. 2. use recommended connection above in i/o port mode (see figure 6-3 and figure 6-4 format of clock operation mode select register (oscctl) ) when these pins are not used. remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 93 jul 15, 2010 table 2-3. pin i/o circuit types (3/3) pin name i/o circuit type i/o recommended connection of unused pins p140/pcl/intp6 p141/buz/busy0/intp7 p142/scka0 p143/sia0 5-aq p144/soa0 p145/stb0 5-ag i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. av ref ? ? 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 94 jul 15, 2010 figure 2-1. pin i/o circuit list (1/2) type 2 type 5-ag schmitt-triggered input with hysteresis characteristics in pull-up enable data output disable input enable ev dd p-ch ev dd p-ch in/out n -ch ev ss type 3-c type 5-aq ev dd p-ch n-ch data out ev ss pullup enable data output disable input enable ev dd p-ch ev dd p-ch in/out n -ch ev ss remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 2 pin functions r01uh0008ej0401 rev.4.01 95 jul 15, 2010 figure 2-1. pin i/o circuit list (2/2) type 11-g type 37 data output disable av ref p-ch in/out n-ch p-ch n-ch series resistor string voltage comparator input enable + _ av ss av ss reset reset data output disable input enable v dd p-ch x1, xt1 n -ch v ss data output disable input enable v dd p-ch n -ch v ss p-ch n-ch x2, xt2 type 13-p type 38-a data output disable input enable in/out n-ch ev ss input enable in type 13-ai data output disable input enable in/out n-ch ev ss remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 96 jul 15, 2010 chapter 3 cpu architecture 3.1 memory space products in the 78k0/kx2 microcontrollers can access a 64 kb memory space. figures 3-1 to 3-11 show the memory maps. cautions 1. regardless of the inte rnal memory capacity, the initial val ues of the intern al memory size switching register (ims) and internal expansion ram size switching register (ixs) of all products in the 78k0/kx2 microcontrollers are fixed (ims = cfh, ixs = 0 ch). therefore, set the value corresponding to each produc t as indicated below. 2. to set the memory size, set ims and then ixs. set the memory si ze so that the internal rom and internal expansion ram areas do not overlap. table 3-1. set values of internal me mory size switching register (ims) (78k0/kb2, and 38-pin products and 44-pin products of the 78k0/kc2) 78k0/kb2 38-pin products and 44-pin products of the 78k0/kc2 ims rom capacity internal high-speed ram capacity pd78f0500, 78f0500a ? 42h 8 kb 512 bytes pd78f0501, 78f0501a pd78f0511, 78f0511a 04h 16 kb 768 bytes pd78f0502, 78f0502a pd78f0512, 78f0512a c6h 24 kb 1 kb pd78f0503, 78f0503a, 78f0503d note , 78f0503da note pd78f0513, 78f0513a, 78f0513d note , 78f0513da note c8h 32 kb 1 kb note the rom and ram capacities of the products with the on-ch ip debug function can be debugged by setting ims, according to the debug target products. set ims according to the debug target products. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 97 jul 15, 2010 table 3-2. set values of internal me mory size switching register (ims ) and internal expansion ram size switching register (ixs) (48-pin products of the 78k0/kc2, 78k0/kd2, 78k 0/ke2, and 78k0/kf2) 48-pin products of the 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 ims ixs rom capacity internal high- speed ram capacity internal expansion ram capacity pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? 04h 0ch 16 kb 768 bytes ? pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? c6h 0ch 24 kb 1 kb ? pd78f0513, 78f0513a pd78f0523, 78f0523a pd78f0533, 78f0533a ? c8h 0ch 32 kb 1 kb ? pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a cch 0ah 48 kb 1 kb pd78f0515, 78f0515a, 78f0515d note 1 , 78f0515da note 1 pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a cfh 08h 60 kb 2 kb ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a cch note 2 04h 96 kb note 2 4 kb ? pd78f0527, 78f0527a, 78f0527d note 1 , 78f0527da note 1 pd78f0537, 78f0537a, 78f0537d note 1 , 78f0537da note 1 pd78f0547, 78f0547a, 78f0547d note 1 , 78f0547da note 1 cch note 2 00h 128 kb note 2 1 kb 6 kb notes 1. the rom and ram capacities of t he products with the on-chip debug function can be debugged according to the debug target products. set ims and ixs according to the debug target products. 2. the pd78f05x6 and 78f05x6a (x = 2 to 4) have internal roms of 96 kb, and the pd78f05x7, 78f05x7a, 78f05x7d and 78f05x7da (x = 2 to 4) have th ose of 128 kb. however, the set value of ims of these devices is the same as thos e of the 48 kb product because memory banks are used. for how to set the memory banks, see 4.3 memory bank select register (bank) . 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 98 jul 15, 2010 figure 3-1. memory map ( pd78f0500 and 78f0500a) ffffh ff00h feffh fee0h fedfh fd00h fcffh 2000h 1fffh 0000h 1fffh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h 0080h 007fh 1085h 1084h 1080h 107fh program memory space data memory space flash memory 8192 8 bits reserved internal high-speed ram 512 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits boot cluster 1 boot cluster 0 note 2 vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits program area 1915 8 bits callf entry area 2048 8 bits program area option byte area note 1 5 8 bits program area notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 07h 1 kb 1fffh 07ffh 0000h 0400h 03ffh 1c00h 1bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 99 jul 15, 2010 figure 3-2. memory map ( pd78f0501, 78f0501a, 78f0511, 78f05 11a, 78f0521, 78f0521a, 78f0531, and 78f0531a) 0000h 4000h 3fffh fc00h fbffh ffffh ff00h feffh fee0h fedfh data memory space program memory space flash memory 16384 8 bits reserved internal high-speed ram 768 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits 3fffh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h 0080h 007fh 1085h 1084h 1080h 107fh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits program area 1915 8 bits callf entry area 2048 8 bits program area option byte area note 1 5 8 bits program area boot cluster 1 boot cluster 0 note 2 1fffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 0fh 1 kb 3fffh 07ffh 0000h 0400h 03ffh 3c00h 3bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 100 jul 15, 2010 figure 3-3. memory map ( pd78f0502, 78f0502a, 78f0512, 78f05 12a, 78f0522, 78f0522a, 78f0532, and 78f0532a) 0000h 6000h 5fffh program memory space data memory space flash memory 24576 8 bits reserved fb00h faffh ffffh ff00h feffh fee0h fedfh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits 5fffh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0080h 007fh 1085h 1084h 1080h 107fh callt table area 64 8 bits option byte area note 1 5 8 bits program area 1915 8 bits callf entry area 2048 8 bits program area option byte area note 1 5 8 bits program area vector table area 64 8 bits 1fffh boot cluster 1 boot cluster 0 note 2 0085h 0084h notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 17h 1 kb 5fffh 07ffh 0000h 0400h 03ffh 5c00h 5bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 101 jul 15, 2010 figure 3-4. memory map ( pd78f0503, 78f0503a, 78f0513, 78f05 13a, 78f0523, 78f0523a, 78f0533 and 78f0533a) data memory space program memory space flash memory 32768 8 bits 0000h 8000h 7fffh fb00h faffh ffffh ff00h feffh fee0h fedfh reserved internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits 7fffh callt table area 64 8 bits option byte area note 1 5 8 bits program area 1915 8 bits callf entry area 2048 8 bits program area option byte area note 1 5 8 bits program area 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h 0080h 007fh 1085h 1084h 1080h 107fh vector table area 64 8 bits boot cluster 1 boot cluster 0 note 2 1fffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 1fh 1 kb 7fffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 102 jul 15, 2010 figure 3-5. memory map ( pd78f0503d, 78f0503da, 78f0513d, and 78f0513da) data memory space program memory space 0000h 8000h 7fffh fb00h faffh ffffh ff00h feffh fee0h fedfh flash memory 32768 8 bits reserved internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits 7fffh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh program area 1905 8 bits program area vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits on-chip debug security id setting area note 1 10 8 bits 1fffh boot cluster 1 boot cluster 0 note 2 program area notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 1fh 1 kb 7fffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 103 jul 15, 2010 figure 3-6. memory map ( pd78f0514, 78f0514a, 78f0524, 78f0524 a, 78f0534, 78f0534a, 78f0544, and 78f0544a) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 1024 8 bits buffer ram 32 8 bits note 3 reserved general-purpose registers 32 8 bits reserved reserved ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh fa00h f9ffh fa20h fa1fh f400h f3ffh c000h bfffh 0000h program memory space data memory space flash memory 49152 8 bits ram space in which instruction can be fetched program ram area 0800h 07ffh 1000h 0fffh vector table area 64 8 bits 0040h 003fh 0000h callt table area 64 8 bits 0085h 0084h program area 1915 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits program area bfffh program area 0080h 007fh 1085h 1084h 1080h 107fh option byte area note 1 5 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). 3. the buffer ram is incorporated only in the pd78f0544 and 78f0544a (78k0/ kf2). the area from fa00h to fa1fh cannot be used with the pd78f0514, 78f0514a, 78f0524, 78f 0524a, 78f0534, and 78f0534a. remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 2fh 1 kb bfffh 07ffh 0000h 0400h 03ffh bc00h bbffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 104 jul 15, 2010 figure 3-7. memory map ( pd78f0515, 78f0515a, 78f0525, 78f0525 a, 78f0535, 78f0535a, 78f0545, and 78f0545a) buffer ram 32 8 bits note 3 reserved reserved fa00h f9ffh fa20h fa1fh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 2048 8 bits general-purpose registers 32 8 bits flash memory 61440 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh f000h efffh 0000h program memory space data memory space 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area efffh program area 0080h 007fh 1085h 1084h 1080h 107fh program ram area vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits option byte area note 1 5 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 ram space in which instruction can be fetched notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). 3. the buffer ram is incorporated only in the pd78f0545 and 78f0545a (78k0/ kf2). the area from fa00h to fa1fh cannot be used with the pd78f0515, 78f0515a, 78f0525, 78f 0525a, 78f0535, and 78f0535a. remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 3bh 1 kb efffh 07ffh 0000h 0400h 03ffh ec00h ebffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 105 jul 15, 2010 figure 3-8. memory map ( pd78f0515d and 78f0515da) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh f000h efffh 0000h program memory space ram space in which instruction can be fetched data memory space special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 2048 8 bits general-purpose registers 32 8 bits reserved flash memory 61440 8 bits vector table area 64 x 8 bits callt table area 64 x 8 bits program area 1905 x 8 bits option byte area note 1 5 x 8 bits callf entry area 2048 x 8 bits program area program area option byte area note 1 5 x 8 bits boot cluster 0 note 2 boot cluster 1 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 1085h 1084h 1080h 107fh 0085h 0084h efffh 1fffh 108fh 108eh 008fh 008eh on-chip debug security id setting area note 1 10 x 8 bits on-chip debug security id setting area note1 10 x 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 3bh 1 kb efffh 07ffh 0000h 0400h 03ffh ec00h ebffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 106 jul 15, 2010 figure 3-9. memory map ( pd78f0526, 78f0526a, 78f0536, 78f0536a, 78f0546, and 78f0546a) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 4096 8 bits general-purpose registers 32 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e800h e7ffh 8000h 7fffh 0000h data memory space flash memory 32768 8 bits c000h bfffh reserved flash memory 16384 8 bits (memory bank 0) (memory bank 1) (memory bank 2) buffer ram 32 8 bits note 3 reserved reserved fa00h f9ffh fa20h fa1fh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 7fffh program area 0080h 007fh 1085h 1084h 1080h 107fh program ram area program memory space common area bank area (memory bank 3) vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits option byte area note 1 5 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 ram space in which instruction can be fetched notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). 3. the buffer ram is incorporated only in the pd78f0546 and 78f0546a (78k0/kf 2). the area from fa00h to fa1fh cannot be used with the pd78f0526, 78f0526a, 78f0536, and 78f0536a. remark the flash memory is divided into blocks (one block = 1 kb). for the address valu es and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 1fh block 20h block 2fh 1 kb common area bank area (memory bank 0) block 30h block 3fh (memory bank 1) block 40h block 4fh (memory bank 2) block 50h block 5fh (memory bank 3) bfffh 8000h 7fffh 84ffh 83ffh bc00h bbffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 107 jul 15, 2010 figure 3-10. memory map ( pd78f0527, 78f0527a, 78f0537, 78f 0537a, 78f0547, and 78f0547a) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 6144 8 bits general-purpose registers 32 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e000h dfffh 8000h 7fffh 0000h data memory space flash memory 32768 8 bits c000h bfffh reserved flash memory 16384 8 bits (memory bank 0) (memory bank 1) buffer ram 32 8 bits note 3 reserved reserved fa00h f9ffh fa20h fa1fh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 7fffh program area 0080h 007fh 1085h 1084h 1080h 107fh program memory space common area bank area (memory bank 2) (memory bank 3) (memory bank 4) (memory bank 5) program ram area vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits option byte area note 1 5 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 ram space in which instruction can be fetched notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). 3. the buffer ram is incorporated only in the pd78f0547 and 78f0547a (78k0/kf 2). the area from fa00h to fa1fh cannot be used with the pd78f0527, 78f0527a, 78f0537 and 78f0537a. remark the flash memory is divided into blocks (one block = 1 kb). for the address valu es and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 1fh block 20h block 2fh 1 kb common area bank area (memory bank 0) block 30h block 3fh (memory bank 1) block 40h block 4fh (memory bank 2) block 70h block 7fh (memory bank 5) . . . bfffh 8000h 7fffh 84ffh 83ffh bc00h bbffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 108 jul 15, 2010 figure 3-11. memory map ( pd78f0527d, 78f0527da, 78f0537d, 78 f0537da, 78f0547d, and 78f0547da) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 6144 8 bits general-purpose registers 32 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e000h dfffh 8000h 7fffh 0000h data memory space flash memory 32768 8 bits c000h bfffh reserved flash memory 16384 8 bits (memory bank 0) (memory bank 1) buffer ram 32 8 bits note 3 reserved reserved fa00h f9ffh fa20h fa1fh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 7fffh program area 0080h 007fh 1080h 107fh program memory space common area bank area (memory bank 2) (memory bank 3) (memory bank 4) (memory bank 5) program ram area 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits ram space in which instruction can be fetched notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 security settings ). 3. the buffer ram is incorporated only in the pd78f0547d and 78f0547da (78k 0/kf2). the area from fa00h to fa1fh cannot be used with the pd78f0527d, 78f0527da, 78 f0537d and 78f0537da. remark the flash memory is divided into blocks (one block = 1 kb). for the address valu es and block numbers, see table 3-3 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 1fh block 20h block 2fh 1 kb common area bank area (memory bank 0) block 30h block 3fh (memory bank 1) block 40h block 4fh (memory bank 2) block 70h block 7fh (memory bank 5) . . . bfffh 8000h 7fffh 84ffh 83ffh bc00h bbffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 109 jul 15, 2010 correspondence between the address values and block numbers in the flash memory are shown below. table 3-3. correspondence betw een address values and block nu mbers in flash memory (1/2) (1) products whose flash me mory is less than 60 kb (without memory bank) address value block number address value block number address value block number address value block number 0000h to 03ffh 00h 4000h to 43ffh 10h 8000h to 83ffh 20h c000h to c3ffh 30h 0400h to 07ffh 01h 4400h to 47ffh 11h 8400h to 87ffh 21h c400h to c7ffh 31h 0800h to 0bffh 02h 4800h to 4bffh 12h 8800h to 8bffh 22h c800h to cbffh 32h 0c00h to 0fffh 03h 4c00h to 4fffh 13h 8c00h to 8fffh 23h cc00h to cfffh 33h 1000h to 13ffh 04h 5000h to 53ffh 14h 9000h to 93ffh 24h d000h to d3ffh 34h 1400h to 17ffh 05h 5400h to 57ffh 15h 9400h to 97ffh 25h d400h to d7ffh 35h 1800h to 1bffh 06h 5800h to 5bffh 16h 9800h to 9bffh 26h d800h to dbffh 36h 1c00h to 1fffh 07h 5c00h to 5fffh 17h 9c00h to 9fffh 27h dc00h to dfffh 37h 2000h to 23ffh 08h 6000h to 63ffh 18h a000h to a3ffh 28h e000h to e3ffh 38h 2400h to 27ffh 09h 6400h to 67ffh 19h a400h to a7ffh 29h e400h to e7ffh 39h 2800h to 2bffh 0ah 6800h to 6bffh 1ah a800h to abffh 2ah e800h to ebffh 3ah 2c00h to 2fffh 0bh 6c00h to 6fffh 1bh ac00h to afffh 2bh ec00h to efffh 3bh 3000h to 33ffh 0ch 7000h to 73ffh 1ch b000h to b3ffh 2ch 3400h to 37ffh 0dh 7400h to 77ffh 1dh b400h to b7ffh 2dh 3800h to 3bffh 0eh 7800h to 7bffh 1eh b800h to bbffh 2eh 3c00h to 3fffh 0fh 7c00h to 7fffh 1fh bc00h to bfffh 2fh remark pd78f0500, 78f0500a: block numbers 00h to 07h pd78f05x1, 78f05x1a (x = 0 to 3): block numbers 00h to 0fh pd78f05x2, 78f05x2a (x = 0 to 3): block numbers 00h to 17h pd78f05x3, 78f05x3a (x = 0 to 3), 78f0503d, 78f0503da, 78f0513d, 78f0513da: block numbers 00h to 1fh pd78f05x4, 78f05x4a (x = 1 to 4): block numbers 00h to 2fh pd78f05x5, 78f05x5a (x = 1 to 4), 78f0515d , 78f0515da: block numbers 00h to 3bh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 110 jul 15, 2010 table 3-3. correspondence betw een address values and block nu mbers in flash memory (2/2) (2) products whose flash memory is at least 96 kb (with memory bank) address value block number address value memory bank block number address value memory bank block number address value memory bank block number 0000h to 03ffh 00h 8000h to 83ffh 20h 8000h to 83ffh 40h 8000h to 83ffh 60h 0400h to 07ffh 01h 8400h to 87ffh 21h 8400h to 87ffh 41h 8400h to 87ffh 61h 0800h to 0bffh 02h 8800h to 8bffh 22h 8800h to 8bffh 42h 8800h to 8bffh 62h 0c00h to 0fffh 03h 8c00h to 8fffh 23h 8c00h to 8fffh 43h 8c00h to 8fffh 63h 1000h to 13ffh 04h 9000h to 93ffh 24h 9000h to 93ffh 44h 9000h to 93ffh 64h 1400h to 17ffh 05h 9400h to 97ffh 25h 9400h to 97ffh 45h 9400h to 97ffh 65h 1800h to 1bffh 06h 9800h to 9bffh 26h 9800h to 9bffh 46h 9800h to 9bffh 66h 1c00h to 1fffh 07h 9c00h to 9fffh 27h 9c00h to 9fffh 47h 9c00h to 9fffh 67h 2000h to 23ffh 08h a000h to a3ffh 28h a000h to a3ffh 48h a000h to a3ffh 68h 2400h to 27ffh 09h a400h to a7ffh 29h a400h to a7ffh 49h a400h to a7ffh 69h 2800h to 2bffh 0ah a800h to abffh 2ah a800h to abffh 4ah a800h to abffh 6ah 2c00h to 2fffh 0bh ac00h to afffh 2bh ac00h to afffh 4bh ac00h to afffh 6bh 3000h to 33ffh 0ch b000h to b3ffh 2ch b000h to b3ffh 4ch b000h to b3ffh 6ch 3400h to 37ffh 0dh b400h to b7ffh 2dh b400h to b7ffh 4dh b400h to b7ffh 6dh 3800h to 3bffh 0eh b800h to bbffh 2eh b800h to bbffh 4eh b800h to bbffh 6eh 3c00h to 3fffh 0fh bc00h to bfffh 0 2fh bc00h to bfffh 2 4fh bc00h to bfffh 4 6fh 4000h to 43ffh 10h 8000h to 83ffh 30h 8000h to 83ffh 50h 8000h to 83ffh 70h 4400h to 47ffh 11h 8400h to 87ffh 31h 8400h to 87ffh 51h 8400h to 87ffh 71h 4800h to 4bffh 12h 8800h to 8bffh 32h 8800h to 8bffh 52h 8800h to 8bffh 72h 4c00h to 4fffh 13h 8c00h to 8fffh 33h 8c00h to 8fffh 53h 8c00h to 8fffh 73h 5000h to 53ffh 14h 9000h to 93ffh 34h 9000h to 93ffh 54h 9000h to 93ffh 74h 5400h to 57ffh 15h 9400h to 97ffh 35h 9400h to 97ffh 55h 9400h to 97ffh 75h 5800h to 5bffh 16h 9800h to 9bffh 36h 9800h to 9bffh 56h 9800h to 9bffh 76h 5c00h to 5fffh 17h 9c00h to 9fffh 37h 9c00h to 9fffh 57h 9c00h to 9fffh 77h 6000h to 63ffh 18h a000h to a3ffh 38h a000h to a3ffh 58h a000h to a3ffh 78h 6400h to 67ffh 19h a400h to a7ffh 39h a400h to a7ffh 59h a400h to a7ffh 79h 6800h to 6bffh 1ah a800h to abffh 3ah a800h to abffh 5ah a800h to abffh 7ah 6c00h to 6fffh 1bh ac00h to afffh 3bh ac00h to afffh 5bh ac00h to afffh 7bh 7000h to 73ffh 1ch b000h to b3ffh 3ch b000h to b3ffh 5ch b000h to b3ffh 7ch 7400h to 77ffh 1dh b400h to b7ffh 3dh b400h to b7ffh 5dh b400h to b7ffh 7dh 7800h to 7bffh 1eh b800h to bbffh 3eh b800h to bbffh 5eh b800h to bbffh 7eh 7c00h to 7fffh 1fh bc00h to bfffh 1 3fh bc00h to bfffh 3 5fh bc00h to bfffh 5 7fh remark pd78f05x6, 78f05x6a (x = 2 to 4): block numbers 00h to 5fh pd78f05x7, 78f05x7a, 78f05x7d, 78f05x7da (x = 2 to 4): block numbers 00h to 7fh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 111 jul 15, 2010 3.1.1 internal program memory space the internal program memory space st ores the program and table data. norma lly, it is addressed with the program counter (pc). 78k0/kx2 microcontrollers incorporate intern al rom (flash memory), as shown below. table 3-4. intern al rom capacity 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 30/36 pins 38/44 pins 48 pins 52 pins 64 pins 80 pins internal rom (flash memory) pd78f0500, pd78f0500a ? ? ? ? ? 8192 8 bits (0000h to 1fffh) pd78f0501, 78f0501a pd78f0511, 78f0511a pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? 16384 8 bits (0000h to 3fffh) pd78f0502, 78f0502a pd78f0512, 78f0512a pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? 24576 8 bits (0000h to 5fffh) pd78f0503d, 78f0503da pd78f0513d, 78f0513da pd78f0503, 78f0503a pd78f0513, 78f0513a pd78f0513, 78f0513a pd78f0523, 78f0523a pd78f0533, 78f0533a ? 32768 8 bits (0000h to 7fffh) ? ? pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a 49152 8 bits (0000h to bfffh) pd78f0515d, 78f0515da ? ? pd78f0515, 78f0515a pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a 61440 8 bits (0000h to efffh) ? ? ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a 98304 8 bits (0000h to 7fffh (common area: 32 kb) + 8000h to bfffh (bank area: 16 kb) 4) pd78f0527d, 78f0527da pd78f0537d, 78f0537da pd78f0547d, 78f0547da ? ? ? pd78f0527, 78f0527a pd78f0537, 78f0537a pd78f0547, 78f0547a 131072 8 bits (0000h to 7fffh (common area: 32 kb) + 8000h to bfffh (bank area: 16 kb) 6) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is re served as a vector table area. the program start addresses for branch upon reset or generation of each interrupt reques t are stored in the vector table area. of the 16-bit address, the lower 8 bits ar e stored at even addresses and the higher 8 bits are stored at odd addresses. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 112 jul 15, 2010 table 3-5. vector table vector table address interrupt source kb2 kc2 kd2 ke2 kf2 0000h reset input, poc, lvi, wdt 0004h intlvi 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intp4 0010h intp5 0012h intsre6 0014h intsr6 0016h intst6 0018h intcsi10/intst0 001ah inttmh1 001ch inttmh0 001eh inttm50 0020h inttm000 0022h inttm010 0024h intad 0026h intsr0 0028h intwti ? 002ah inttm51 002ch intkr ? 002eh intwt ? 0030h intp6 ? note 1 0032h intp7 ? ? ? 0034h intiic0/ntdmu note 2 note 2 note 2 note 2 0036h intcsi11 ? ? ? note 3 0038h inttm001 ? ? ? note 3 003ah inttm011 ? ? ? note 3 003ch intacsi ? ? ? ? 003eh brk notes 1. 48-pin products only. 2. intiic0: products whose flash memory is less than 32 kb intiic/intdmu: products whose flash memory is at least 48 kb 3. products whose flash memory is at least 48 kb only. remark : mounted, ? : not mounted 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 113 jul 15, 2010 (2) callt instruction table area the 64-byte area 0040h to 007fh can st ore the subroutine entry address of a 1-byte call instruction (callt). (3) option byte area a 5-byte area of 0080h to 0084h and 1080h to 1084h can be used as an option byte area. set the option byte at 0080h to 0084h when the boot swap is not used, and at 0080h to 0084h and 1080h to 1084h when the boot swap is used. for details, see chapter 26 option byte . (4) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). (5) on-chip debug security id setting area ( pd78f05xxd and 78f05xxda only) a 10-byte area of 0085h to 008eh and 1085h to 108eh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 0085h to 008eh when the boot swap is not used and at 0085h to 008eh and 1085h to 108eh when the boot swap is used. for details, see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only) . 3.1.2 memory bank (pro ducts whose flash memory is at least 96 kb only) the 16 kb area 8000h to bfffh is assigned to memory banks 0 to 3 in the pd78f05x6 and 78f05x6a (x = 2 to 4), and assigned to memory banks 0 to 5 in the pd78f05x7, 78f05x7a, 78f05x7d a nd 78f05x7da (x = 2 to 4). the banks are selected by using a memory bank select register (bank). for details, see chapter 4 memory bank select function (products whose flash memory is at least 96 kb only) . cautions 1. instructions cannot be fe tched between different memory banks. 2. branch and access cannot be directly execute d between different memo ry banks. execute branch or access between different memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 114 jul 15, 2010 3.1.3 internal data memory space 78k0/kx2 microcontrollers incorporate the following rams. (1) internal high-speed ram the 32-byte area fee0h to feffh is assigned to four gen eral-purpose register banks consisting of eight 8-bit registers per bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. table 3-6. internal high-speed ram capacity 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 30/36 pins 38/44 pins 48 pins 52 pins 64 pins 80 pins internal high-speed ram pd78f0500, pd78f0500a ? ? ? ? ? 512 8 bits (fd00h to feffh) pd78f0501, 78f0501a pd78f0511, 78f0511a pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? 768 8 bits (fc00h to feffh) pd78f0502, 78f0502a pd78f0512, 78f0512a pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? pd78f0503d, 78f0503da pd78f0513d, 78f0513da pd78f0503, 78f0503a pd78f0513, 78f0513a pd78f0513, 78f0513a pd78f0523, 78f0523a pd78f0533, 78f0533a ? ? ? pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a pd78f0515d, 78f0515da ? ? pd78f0515, 78f0515a pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a ? ? ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a pd78f0527d, 78f0527da pd78f0537d, 78f0537da pd78f0547d, 78f0547da ? ? ? pd78f0527, 78f0527a pd78f0537, 78f0537a pd78f0547, 78f0547a 1024 8 bits (fb00h to feffh) 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 115 jul 15, 2010 (2) internal expansion ram the internal expansion ram can also be used as a normal data area similar to the internal high-speed ram, as well as a program area in which instruct ions can be written and executed. the internal expansion ram cannot be used as a stack memory. table 3-7. internal expansion ram capacity 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 30/36 pins 38/44 pins 48 pins 52 pins 64 pins 80 pins internal expansion ram pd78f0500, pd78f0500a ? ? ? ? ? pd78f0501, 78f0501a pd78f0511, 78f0511a pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? pd78f0502, 78f0502a pd78f0512, 78f0512a pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? pd78f0503d, 78f0503da pd78f0513d, 78f0513da pd78f0503, 78f0503a pd78f0513, 78f0513a pd78f0513, 78f0513a pd78f0523, 78f0523a pd78f0533, 78f0533a ? ? ? ? pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a 1024 8 bits (f400h to f7ffh) pd78f0515d, 78f0515da ? ? pd78f0515, 78f0515a pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a 2048 8 bits (f000h to f7ffh) ? ? ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a 4096 8 bits (e800h to f7ffh) pd78f0527d, 78f0527da pd78f0537d, 78f0537da pd78f0547d, 78f0547da ? ? ? pd78f0527, 78f0527a pd78f0537, 78f0537a pd78f0547, 78f0547a 6144 8 bits (e000h to f7ffh) (3) buffer ram (78k0/kf2 only) the 78k0/kf2 products incorpor ate 32 bytes (fa00h to fa1fh) of buffe r ram. the buffer ram can be used for transfer in csi with automatic transmit/receive function. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 116 jul 15, 2010 3.1.4 special function register (sfr) area on-chip peripheral hardware special function register s (sfrs) are allocated in the area ff00h to ffffh (see table 3- 8 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.5 data memory addressing addressing refers to the method of spec ifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executio n of instructions for the 78k0/kx2 microcontrollers, based on operabilit y and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of s pecial function registers (sfr ) and general-purpose registers are available for use. figures 3-12 to 3-19 show corresp ondence between data memory and ad dressing. for details of each addressing mode, see 3.4 operand address addressing . 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 117 jul 15, 2010 figure 3-12. correspondence between data memory and addressing ( pd78f0500 and 78f0500a) flash memory 8192 8 bits 2000h 1fffh 0000h ffffh ff00h feffh fd00h fcffh fe20h fe1fh fee0h fedfh ff20h ff1fh internal high-speed ram 512 8 bits general-purpose registers 32 8 bits special function registers (sfr) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing reserved 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 118 jul 15, 2010 figure 3-13. correspondence between data memory and addressing ( pd78f0501, 78f0501a, 78f0511, 78f0511a, 78f0521, 78f0521a , 78f0531, and 78f0531a) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits ffffh ff00h feffh fee0h fedfh fc00h fbffh 4000h 3fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 119 jul 15, 2010 figure 3-14. correspondence between data memory and addressing ( pd78f0502, 78f0502a, 78f0512, 78f0512a, 78f0522, 78f0522a , 78f0532, and 78f0532a) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 24576 x 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 120 jul 15, 2010 figure 3-15. correspondence between data memory and addressing ( pd78f0503, 78f0503a, 78f0513, 78f0513a, 78f0523, 78f05 23a, 78f0533, 78f0533a, 78f0503d, 78f0503da, 78f0513d, and 78f0513da) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh 8000h 7fffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 121 jul 15, 2010 figure 3-16. correspondence between data memory and addressing ( pd78f0514, 78f0514a, 78f0524, 78f0524a, 78f0534, 78f0534a , 78f0544, and 78f0544a) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh c000h bfffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits note reserved reserved flash memory 49152 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh f400h f3ffh fb00h faffh fa20h fa1fh internal expansion ram 1024 8 bits reserved note the buffer ram is incorporated only in the pd78f0544 and 78f0544a (78k0/kf2) . the area from fa00h to fa1fh cannot be used with the pd78f0514, 78f0514a, 78f0524, 78f0524a, 78f0534, and 78f0534a. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 122 jul 15, 2010 figure 3-17. correspondence between data memory and addressing ( pd78f0515, 78f0515a, 78f0525, 78f05 25a, 78f0535, 78f0535a, 78f0545, 78f0545a, 78f0515d and 78f0515da) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits note reserved reserved flash memory 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh fb00h faffh fa20h fa1fh internal expansion ram 2048 8 bits note the buffer ram is incorporated only in the pd78f0545 and 78f0545a (78k0/kf2) . the area from fa00h to fa1fh cannot be used with the pd78f0515, 78f0515a, 78f0525, 78f0525a, 78f0535, 78f0535a, 78f0515d, and 78f0515da. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 123 jul 15, 2010 figure 3-18. correspondence between data memory and addressing ( pd78f0526, 78f0526a, 78f0536, 78f0536a, 78f0546, and 78f0546a) 16384 8 bits (memory bank 1) note 2 16384 8 bits (memory bank 3) note 2 16384 8 bits (memory bank 2) note 2 special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh 8000h 7fffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits note 1 reserved reserved flash memory 32768 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh e800h e7ffh fb00h faffh fa20h fa1fh internal expansion ram 4096 8 bits reserved c000h bfffh flash memory 16384 8 bits (memory bank 0) note 2 notes 1. the buffer ram is incorporated only in the pd78f0546 and 78f0546a (78k0/ kf2). the area from fa00h to fa1fh cannot be used with the pd78f0526, 78f0526a, 78f0536 and 78f0536a. 2. to branch to or address a memory ba nk that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 124 jul 15, 2010 figure 3-19. correspondence between data memory and addressing ( pd78f0527, 78f0527a, 78f0537, 78f05 37a, 78f0547, 78f0547a, 78f0527d, 78f0527da, 78f0537d, 78f0537da, 78f0547d and 78f0547da) 16384 8 bits (memory bank 1) note 2 16384 8 bits (memory bank 4) note 2 16384 8 bits (memory bank 3) note 2 16384 8 bits (memory bank 5) note 2 16384 8 bits (memory bank 2) note 2 special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh 8000h 7fffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved reserved buffer ram 32 8 bits note 1 flash memory 32768 8 bits register addressing f800h f7ffh fa00h f9ffh e000h dfffh fb00h faffh fa20h fa1fh internal expansion ram 6144 8 bits reserved c000h bfffh flash memory 16384 8 bits (memory bank 0) note 2 direct addressing register indirect addressing based addressing based indexed addressing notes 1. the buffer ram is incorporated only in the pd78f0547, 78f0547a, 78f0547d and 78f0547da (78k0/kf2). the area from fa00h to fa1fh cannot be used with the pd78f0527, 78f0527a, 78f0537, 78f0537a, 78f0527d, 78f0527da, 78f0537d and 78f0537da. 2. to branch to or address a memory ba nk that is not set by the memory bank select register (bank), change the setting of the memory bank by using bank. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 125 jul 15, 2010 3.2 processor registers the 78k0/kx2 microcontrollers incorporat e the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, imme diate data and register contents are set. reset signal generation sets the reset vector table val ues at addresses 0000h and 0001h to the program counter. figure 3-20. format of program counter 15 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are st ored in the stack area upon vectored in terrupt request acknowledgement or push psw instruction execution and are restored upon ex ecution of the retb, reti and pop psw instructions. reset signal generation sets psw to 02h. figure 3-21. format of program status word ie z rbs1 ac rbs0 isp cy 70 0 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request a cknowledgment is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executio n or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates the re gister bank selected by sel rbn instruction execution is stored. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 126 jul 15, 2010 (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskab le vectored interrupts. when this flag is 0, low-level vectored interrupt requests specified by a priority spec ification flag register (pr0l, pr0h, pr1l, pr1h) (see 20.3 (3) priority specification flag registers (pr0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgment is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit a ccumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the st art address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-22. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (s ave) to the stack memory and is incr emented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-23 and 3-24. caution since reset signal generation makes the sp contents undefined, be sure to in itialize the sp before using the stack. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 127 jul 15, 2010 figure 3-23. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 128 jul 15, 2010 figure 3-24. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 129 jul 15, 2010 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to fe ffh) of the data memory. the general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit regi sters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x , a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction ( sel rbn). because of the 4- register bank configuration, an efficient program can be created by switching betwe en a register for normal processing and a register for interrupts for each bank. figure 3-25. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 130 jul 15, 2010 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like general- purpose registers, using operation, transfer, and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-8 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a spec ial function register. it is a reserv ed word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc 78k0. when using the ra78k0, id78k0-qb, sm+ for 78k0, and sm+ for 78k0/kx2, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 131 jul 15, 2010 table 3-8. special function register list (1/5) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset k b 2 k c 2 k d 2 k e 2 k f 2 ff00h port register 0 p0 r/w ? 00h ff01h port register 1 p1 r/w ? 00h ff02h port register 2 p2 r/w ? 00h ff03h port register 3 p3 r/w ? 00h ff04h port register 4 p4 r/w ? 00h ? ff05h port register 5 p5 r/w ? 00h ? ? ? ff06h port register 6 p6 r/w ? 00h ff07h port register 7 p7 r/w ? 00h ? ff08h 10-bit a/d conversion result register adcr r ? ? 0000h ff09h 8-bit a/d conversion result register adcrh r ? ? 00h ff0ah receive buffer register 6 rxb6 r ? ? ffh ff0bh transmit buffer register 6 txb6 r/w ? ? ffh ff0ch port register 12 p12 r/w ? 00h ff0dh port register 13 p13 r/w ? 00h ? note ff0eh port register 14 p14 r/w ? 00h ? note ff0fh serial i/o shift register 10 sio10 r ? ? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ? ? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ? ? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ? ? 0000h ff16h 8-bit timer counter 50 tm50 r ? ? 00h ff17h 8-bit timer compare register 50 cr50 r/w ? ? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ? ? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ? ? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ? ? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff1fh 8-bit timer counter 51 tm51 r ? ? 00h ff20h port mode register 0 pm0 r/w ? ffh ff21h port mode register 1 pm1 r/w ? ffh ff22h port mode register 2 pm2 r/w ? ffh ff23h port mode register 3 pm3 r/w ? ffh ff24h port mode register 4 pm4 r/w ? ffh ? ff25h port mode register 5 pm5 r/w ? ffh ? ? ? ff26h port mode register 6 pm6 r/w ? ffh ff27h port mode register 7 pm7 r/w ? ffh ? ff28h a/d converter mode register adm r/w ? 00h ff29h analog input channel specification register ads r/w ? 00h ff2ch port mode register 12 pm12 r/w ? ffh ff2eh port mode register 14 pm14 r/w ? ffh ? note ff2fh a/d port configuration register adpc r/w ? 00h note this register is incorporated only in 48-pin products. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 132 jul 15, 2010 table 3-8. special function register list (2/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset k b 2 k c 2 k d 2 k e 2 k f 2 ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff34h pull-up resistor option register 4 pu4 r/w ? 00h ? ff35h pull-up resistor option register 5 pu5 r/w ? 00h ? ? ? ff36h pull-up resistor option register 6 pu6 r/w ? 00h ? ? ? ? ff37h pull-up resistor option register 7 pu7 r/w ? 00h ? ff3ch pull-up resistor option register 12 pu12 r/w ? 00h ff3eh pull-up resistor option register 14 pu14 r/w ? 00h ? note 1 ff40h clock output selection register cks r/w ? 00h ? note 1 ff41h 8-bit timer compare register 51 cr51 r/w ? ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff48h external interrupt risi ng edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h ff4ah serial i/o shift register 11 sio11 r ? ? 00h ? ? ? note 2 ff4ch transmit buffer register 11 sotb11 r/w ? ? 00h ? ? ? note 2 ff4fh input switch control register isc r/w ? 00h ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff53h asynchronous serial inte rface reception error status register 6 asis6 r ? ? 00h ff55h asynchronous serial in terface transmission status register 6 asif6 r ? ? 00h ff56h clock selection register 6 cksr6 r/w ? ? 00h ff57h baud rate generator control register 6 brgc6 r/w ? ? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ? 16h ff60h sdr0l ? 00h ? note 2 note 2 note 2 ff61h remainder data register 0 sdr0 sdr0h r ? 00h ? note 2 note 2 note 2 ff62h mda0ll ? 00h ? note 2 note 2 note 2 ff63h mda0l mda0lh r/w ? 00h ? note 2 note 2 note 2 ff64h mda0hl ? 00h ? note 2 note 2 note 2 ff65h multiplication/division data register a0 mda0h mda0hh r/w ? 00h ? note 2 note 2 note 2 ff66h mdb0l ? 00h ? note 2 note 2 note 2 ff67h multiplication/division data register b0 mdb0 mdb0h r/w ? 00h ? note 2 note 2 note 2 ff68h multiplier/divider control register 0 dmuc0 r/w ? 00h ? note 2 note 2 note 2 ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h notes 1. this register is incorporated only in 48-pin products. 2. this register is incorporated only in pr oducts whose flash memory is at least 48 kb. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 133 jul 15, 2010 table 3-8. special function register list (3/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset k b 2 k c 2 k d 2 k e 2 k f 2 ff6ah timer clock selection register 50 tcl50 r/w ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ? 00h ff6dh 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h ff6eh key return mode register krm r/w ? 00h ? ff6fh watch timer operation mode register wtm r/w ? 00h ? ff70h asynchronous serial interface operation mode register 0 asim0 r/w ? 01h ff71h baud rate generator control register 0 brgc0 r/w ? ? 1fh ff72h receive buffer register 0 rxb0 r ? ? ffh ff73h asynchronous serial inte rface reception error status register 0 asis0 r ? ? 00h ff74h transmit shift register 0 txs0 w ? ? ffh ff80h serial operation mode register 10 csim10 r/w ? 00h ff81h serial clock selection register 10 csic10 r/w ? 00h ff84h transmit buffer register 10 sotb10 r/w ? ? 00h ff88h serial operation mode register 11 csim11 r/w ? 00h ? ? ? note 1 ff89h serial clock selection register 11 csic11 r/w ? 00h ? ? ? note 1 ff8ch timer clock selection register 51 tcl51 r/w ? 00h ff90h serial operation mode specification register 0 csima0 r/w ? 00h ? ? ? ? ff91h serial status register 0 csis0 r/w ? 00h ? ? ? ? ff92h serial trigger register 0 csit0 r/w ? 00h ? ? ? ? ff93h division value selecti on register 0 brgca0 r/w ? ? 03h ? ? ? ? ff94h automatic data transfer address point specification register 0 adtp0 r/w ? ? 00h ? ? ? ? ff95h automatic data transfer interval specification register 0 adti0 r/w ? ? 00h ? ? ? ? ff96h serial i/o shift register 0 sioa0 r/w ? ? 00h ? ? ? ? ff97h automatic data transfer address count register 0 adtc0 r ? ? 00h ? ? ? ? ff99h watchdog timer enable register wdte r/w ? ? 1ah/ 9ah note 2 ff9fh clock operation mode select register oscctl r/w ? 00h ffa0h internal oscillation mode register rcm r/w ? 80h note 3 ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 80h ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? ? 05h notes 1. this register is incorporated only in pr oducts whose flash memory is at least 48 kb. 2. the reset value of wdte is determined by setting of option byte. 3 the value of this register is 00h immediately after a reset release but automatically changes to 80h after oscillation accuracy stabilization of high-s peed internal oscillator has been waited. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 134 jul 15, 2010 table 3-8. special function register list (4/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset k b 2 k c 2 k d 2 k e 2 k f 2 ffa5h iic shift register 0 iic0 r/w ? ? 00h ffa6h iic control register 0 iicc0 r/w ? 00h ffa7h slave address register 0 sva0 r/w ? ? 00h ffa8h iic clock selection register 0 iiccl0 r/w ? 00h ffa9h iic function expansion register 0 iicx0 r/w ? 00h ffaah iic status register 0 iics0 r ? 00h ffabh iic flag register 0 iicf0 r/w ? 00h ffach reset control flag register resf r ? ? 00h note 1 ffb0h ffb1h 16-bit timer counter 01 tm01 r ? ? 0000h ? ? ? note 2 ffb2h ffb3h 16-bit timer capture/compare register 001 cr001 r/w ? ? 0000h ? ? ? note 2 ffb4h ffb5h 16-bit timer capture/compare register 011 cr011 r/w ? ? 0000h ? ? ? note 2 ffb6h 16-bit timer mode control register 01 tmc01 r/w ? 00h ? ? ? note 2 ffb7h prescaler mode register 01 prm01 r/w ? 00h ? ? ? note 2 ffb8h capture/compare control register 01 crc01 r/w ? 00h ? ? ? note 2 ffb9h 16-bit timer output control register 01 toc01 r/w ? 00h ? ? ? note 2 ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h note 3 ffbfh low-voltage detection level selection register lvis r/w ? 00h note 3 ffe0h interrupt request flag register 0l if0 if0l r/w 00h ffe1h interrupt request flag register 0h if0h r/w 00h ffe2h interrupt request flag register 1l if1 if1l r/w 00h ffe3h interrupt request flag register 1h if1h r/w 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ffh ffe7h interrupt mask flag register 1h mk1h r/w ffh notes 1. the reset value of resf varies depending on the reset source. 2. this register is incorporated only in pr oducts whose flash memory is at least 48 kb. 3. the reset values of lvim and lvis vary depending on the reset source. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 135 jul 15, 2010 table 3-8. special function register list (5/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset k b 2 k c 2 k d 2 k e 2 k f 2 ffe8h priority specification flag register 0l pr0 pr0l r/w ffh ffe9h priority specification flag register 0h pr0h r/w ffh ffeah priority specification flag register 1l pr1 pr1l r/w ffh ffebh priority specification flag register 1h pr1h r/w ffh fff0h internal memory size switching register notes 3,4 ims r/w ? ? cfh fff3h memory bank select register bank r/w ? ? 00h ? ? note 1 note 1 note 1 fff4h internal expansion ram size switching register notes 3,4 ixs r/w ? ? 0ch note 2 note 2 note 2 note 2 fffbh processor clock control register pcc r/w ? 01h notes 1. this register is incorporated only in pr oducts whose flash memory is at least 96 kb. 2. set this register only in products with internal expansion ram. 3. regardless of the internal memory c apacity, the initial values of the internal memory size switching register (ims) and internal expansion ram size switching re gister (ixs) of all pr oducts in the 78k0/kx2 microcontrollers are fixed (ims = cfh, ixs = 0ch). t herefore, set the value corresponding to each product as indicated in tables 3-1 and 3-2. 4. the rom and ram capacities of the products with the on-chip debug func tion can be debugged by setting ims and ixs, according to the debug target products . set ims and ixs according to the debug target products. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 136 jul 15, 2010 3.3 instruction address addressing an instruction address is determined by co ntents of the program counter (pc) and memory bank select register (bank), and is normally incremented (+1 for each byte) automatically acco rding to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instructi on is executed, the branch destination information is set to pc and branched by the following addressing (for details of instructions, refer to the 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediat e data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (p c) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relative br anching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 137 jul 15, 2010 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructi ons can be branched to the entire me mory space. however, before branching to a memory bank that is not set by the memo ry bank select register (bank), change the setting of the memory bank by using bank. the callf !addr11 instruction is br anched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 138 jul 15, 2010 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address that is indicated by addr5 and is stor ed in the memory table from 0040h to 007fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 15 1 addr5 01 00000000 65 0 0 ta 4?0 ... the value of the effective address is the same as that of addr5. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 139 jul 15, 2010 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are transfe rred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 3.4 operand address addressing the following methods are available to specify the regist er and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/kx2 microcontroller instruction words, t he following instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the produc t of the a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 140 jul 15, 2010 3.4.2 register addressing [function] the general-purpose register to be specif ied is accessed as an operand with the r egister bank select flags (rbs0 to rbs1) and the register specify codes of an operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of t he eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp 0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 141 jul 15, 2010 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed wit h immediate data in an instruction word becoming an operand address. this addressing can be carried out for all of the memory spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank) , change the setting of the memory bank by using bank. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 142 jul 15, 2010 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of th e overall sfr area. ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing sfrs to be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effectiv e address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] shown below. [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] lb1 equ 0fe30h ; defines fe30h by lb1. : mov lb1, a ; when lb1 indicates fe30h of the saddr area and the value of register a is transferred to that address operation code 1 1110010 op c ode 0 0110000 30h (s addr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 143 jul 15, 2010 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240- byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special func tion register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1110110 op c ode 0 0100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 144 jul 15, 2010 3.4.6 register indirect addressing [function] register pair contents specifi ed by a register pair specify code in an instru ction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all of the memory spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank) , change the setting of the memory bank by using bank. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 145 jul 15, 2010 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of t he base register, that is, t he hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memory spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank) , change the setting of the memory bank by using bank. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory + 10 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 146 jul 15, 2010 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the bas e register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by ex panding the b or c register c ontents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memory spaces. however, before addressing a memory bank that is not set by the memory bank select register (bank) , change the setting of the memory bank by using bank. [operand format] identifier description ? [hl + b], [hl + c] [description example] mov a, [hl +b]; when selecting b register operation code 10101011 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory 78k0/kx2 chapter 3 cpu architecture r01uh0008ej0401 rev.4.01 147 jul 15, 2010 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when t he push, pop, subroutine call and return instructions are executed or the register is saved/rese t upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] push de; when saving de register operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 148 jul 15, 2010 chapter 4 memory bank select function (products whose flash memory is at least 96 kb only) 4.1 memory bank the pd78f05x6, 78f05x6a, 78f05x7, 78f 05x7a, 78f05x7d and 78f05x7da of 78k0/kd2, 78k0/ke2, and 78k0/kf2 implement a rom capacit y of 96 kb or 128 kb by selecting a memory bank from a memory space of 8000h to bfffh. the pd78f05x6 and 78f05x6a have memory banks 0 to 3, and the pd78f05x7, 78f05x7a, 78f05x7d and 78f05x7da have memory banks 0 to 5, as shown below. the memory banks are selected by using a memory bank select register (bank). figure 4-1. internal rom (f lash memory) configuration (a) pd78f05x6 and 78f05x6a (products whose flash memory is 96 kb) 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) (memory bank 2) common area bank area (memory bank 3) (b) pd78f05x7, 78f05x7a, 78f 05x7d, and 78f05x7da (products whose flash memory is 128 kb) 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) common area bank area (memory bank 3) (memory bank 4) (memory bank 5) (memory bank 2) remark x = 2 to 4 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 149 jul 15, 2010 4.2 difference in representation of memory space with the 78k0/kx2 microcontroller products which support the memory bank, addresses can be viewed in the following two different ways. ? memory bank number + cpu address ? flash memory real address (hex format [bank]) figure 4-2. address view (a) memory bank number + cpu address (b) flash memory real address (hex format [bank]) 0000h common (32 kb) memory bank 0 (16 kb) memory bank 1 memory bank 2 common area bank area memory bank 3 memory bank 4 memory bank 5 bfffh 8000h 7fffh memory bank 5 (16 kb) memory bank 4 (16 kb) memory bank 3 (16 kb) memory bank 2 (16 kb) memory bank 1 (16 kb) memory bank 0 (16 kb) common (32 kb) 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 00000h ?memory bank number + cpu address? is represented with a vacancy in the address space, while the flash memory real address is shown with no vacancy in the address space. ?memory bank number + cpu address? is used for addressi ng in the user program. for on-board programming and self programming not using the self programming sample library note 1 , the flash memory real address is used. note that the hex file that is output by the assembler (ra78k0) by default uses the flash memory real address. for address representation of t he other tools such as the simulator and the debugger note 2 , see table 4-1 . notes 1. ?memory bank number + cpu address? can be used when performing self programming, using the self programming sample library, because the addresses are automatically translated. 2. sm+ for 78k0, sm+ for 78k0/kx2, and id78k0-qb 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 150 jul 15, 2010 table 4-1. memory bank address representation memory bank number cpu address flash memo ry real address address representation in simulator and debugger note 1 memory bank 0 08000h-0bfffh 08000h-0bfffh memory bank 1 0c000h-0ffffh 18000h-1bfffh memory bank 2 10000h-13fffh 28000h-2bfffh memory bank 3 14000h-17fffh 38000h-3bfffh memory bank 4 18000h-1bfffh 48000h-4bfffh memory bank 5 08000h-0bfffh note 2 1c000h-1ffffh 58000h-5bfffh notes 1. sm+ for 78k0, sm+ for 78k0/kx2, and id78k0-qb 2. set the memory bank to be used by the memory bank select register (bank) (see figure 4-3 ). for details, see the ra78k0 ver. 3.80 assembler package operation user?s manual (u17199e) and the 78k0 microcontrollers self programming library type01 user?s manual (u18274e) . 4.3 memory bank select register (bank) the memory bank select register (bank) is used to select a memory bank to be used. bank can be set by an 8-bit memory manipulation instruction. reset signal generation clears bank to 00h. figure 4-3. format of memory bank select register (bank) address: fff3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bank 0 0 0 0 0 bank2 bank1 bank0 bank setting bank2 bank1 bank0 pd78f05x6 and 78f05x6a pd78f05x7, 78f05x7a, 78f05x7d, and 78f05x7da 0 0 0 common area (32 kb) + memory bank 0 (16 kb) 0 0 1 common area (32 kb) + memory bank 1 (16 kb) 0 1 0 common area (32 kb) + memory bank 2 (16 kb) 0 1 1 common area (32 kb) + memory bank 3 (16 kb) 1 0 0 common area (32 kb) + memory bank 4 (16 kb) 1 0 1 setting prohibited common area (32 kb) + memory bank 5 (16 kb) other than above setting prohibited caution be sure to change the value of the bank register in the common area (0000h to 7fffh). if the value of the bank register is changed in the bank area (8000h to bfffh), an inadvertent program loop occurs in the cpu. therefore, never ch ange the value of the bank register in the bank area. remark x = 2 to 4 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 151 jul 15, 2010 4.4 selecting memory bank the memory bank selected by the memory bank select r egister (bank) is reflected on the bank area and can be addressed. therefore, to access a memory bank different fr om the one currently selected, that memory bank must be selected by using the bank register. the value of the bank r egister must not be changed in the bank area (8000h to bfffh). t herefore, to change the memory bank, branch an instruction to the common area (0000h to 7fffh) and change the val ue of the bank register in that area. cautions 1. instructions cannot be fe tched between different memory banks. 2. branching and accessing cannot be directly execu ted between different memory banks. execute branching or accessing between differen t memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. 4.4.1 referencing valu es between memory banks values cannot be directly referenced from one memory bank to another. to access another memory bank from one memory bank, branc h once to the common area (0000h to 7fffh), change the setting of the bank register t here, and then reference a value. memory bank m common area bank area memory bank n referencing value common area bank area referencing value memory bank m memory bank n 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 152 jul 15, 2010 ? software example (to store a value to be referenced in register a) ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng an address at the reference destination. r_bnkn: ds 1 ; secures ram for specifying a me mory bank number at the reference destination. r_bnkrn: ds 1 ; secures ram for saving a me mory bank number at the reference source. etrc cseg unit entry: mov r_bnkn,#banknum data1 ; stores the memory bank number at the reference destination. movw r_bnka,#data1 ; stores the address at the reference destination. call !bnkrd ; calls a subroutine for referencing between memory banks. : : bnkc cseg at 7000h bnkrd: ; subroutine for referencing between memory banks. push hl ; saves the contents of the hl register. mov a,r_bnkn ; acquires the memory bank number at the reference destination. xch a,bank ; swaps the memory bank number at the reference source for that at the reference ; destination mov r_bnkrn,a ; saves the memory bank number at the reference source. xchw ax,hl ; saves the contents of the x register. movw ax,r_bnka ; acquires the address at the reference destination. xchw ax,hl ; specifies the address at the reference destination. mov a,[hl] ; reads the target value. xch a,r_bnkrn ; acquires the memory bank number at the reference source. mov bank,a ; specifies the memory bank number at the reference source. mov a,r_bnkrn ; write the target value to the a register. pop hl ; restores the contents of the hl register. ret ; return data cseg bank3 data1: db 0aah end 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 153 jul 15, 2010 4.4.2 branching instruct ion between memory banks instructions cannot branch directly from one memory bank to another. to branch an instruction from one memory bank to anot her, branch once to the common area (0000h to 7fffh), change the setting of the bank r egister there, and then execute the branch instruction again. memory bank m common area bank area memory bank n instruction branch common area bank area instruction branch memory bank m memory bank n 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 154 jul 15, 2010 ? software example 1 (to branch from all areas) ? software example 2 (to branch from common area to any bank area) ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng a memory bank at the branch destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the branch destination. rsaveax: ds 2 ; secures ram for saving the ax register. etrc cseg unit entry: mov r_bnkn,#banknum test ; stores the memory bank number at the branch destination in ram. movw r_bnka,#test ; stores the addr ess at the branch destination in ram. br !bnkbr ; branches to inte r-memory bank branch processing. : : bnkc cseg at 7000h bnkbr: movw rsaveax,ax ; saves the ax register. mov a,r_bnkn ; acquires the memory bank number at the branch destination. mov bank,a ; specifies the memory bank number at the branch destination. movw ax,r_bnka ; specifies the address at the branch destination. push ax ; sets the address at the branch destination to stack. movw rsaveax,ax ; restores the ax register. ret ; branch bn3 cseg bank3 test: mov ??? : : end etrc cseg at 2000h entry: mov r_bnkn,#banknum test ; stores the memory bank number at the branch destination in ram. br !test ; stores the address at the branch destination in ram. bn3 cseg bank3 test: mov ??? : : end 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 155 jul 15, 2010 4.4.3 subroutine call between memory banks subroutines cannot be directly called between memory banks. to call a subroutine between memory banks, branch once to the common area (0000 h to 7fffh), specify the memory bank at the calling destination by using the bank register there, execute the call instruction, and branch to the call destination by that instruction. at this time, save the current value of the bank register to ram. restore the value of the bank register before executing the ret instruction. memory bank m common area bank area memory bank n br instruction common area bank area call instruction memory bank m memory bank n call inst- ruction call instruction change bank and save memory bank number at calling source. ret instruction ret instruction 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 156 jul 15, 2010 ? software example remark in the software example above, multiplexed processing is not supported. ramd dseg saddr r_bnka: ds 2 ; secures ram for specif ying an address at the calling destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the calling destination. r_bnkrn: ds 1 ; secures ram for saving a memory bank number at the calling source. rsaveax: ds 2 ; secures ram for saving the ax register. etrc cseg unit entry: mov r_bnkn,#banknum test ; store the memory bank number at the calling destination in ram. movw r_bnka,#test ; stores the addr ess at the calling destination in ram. call !bnkcal ; branches to an inter-memory bank calling processing routine. : : bnkc cseg at 7000h bnkcal: ; inter-memory bank calling processing routine movw rsaveax,ax ; saves the ax register. mov a,r_bnkn ; acquires the memory bank number at the calling destination. xch a,bank ; changes the bank and acquires the memory bank number at the calling source. mov r_bnkrn,a ; saves the memory bank number at the calling source to ram. call !bnkcals ; calls a subroutine to branch to the calling destination. movw rsaveax,ax ; saves the ax register. xch a,r_bnkrn ; acquires the memory bank number at the calling source. mov bank,a ; specifies the memory bank number at the calling source. movw ax,rsaveax ; restores the ax register. ret ; returns to the calling source. bnkcals: movw ax,r_bnka ; specifies the address at the calling destination. push ax ; sets the address at the calling destination to stack. movw ax,rsaveax ; restores source ax register. ret ; branches to the calling destination. bn3 cseg bank3 test: ; mov ??? : : ret end 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 157 jul 15, 2010 4.4.4 instruction branch to bank area by interrupt when an interrupt occurs, instructions can branch to the me mory bank specified by the bank register by using the vector table, but it is difficult to identif y the bank register when the interrupt occurs. therefore, specify the branch destinati on address specified by the vector table in the common area (0000h to 7fffh), specify the memory bank at the branch de stination by using the bank register in the common area, and execute the call instruction. at this time, save the bank register value before the change to ram, and re store the value of the bank register before executi ng the reti instruction. remark allocate interrupt servicing that requires a quick response in the common area. memory bank m common area bank area memory bank n instruction branch save the original memory bank number. specify the address and memory bank at the destination, and execute the call instruction. vector table ? software example (when using interrupt request of 16-bit timer/event counter 00) vctbl cseg at 0020h dw bnkitm000 ; specifies an addre ss at the timer interrupt destination. ramd dseg saddr r_bnkrn: ds 1 ; secures ram for saving the memory bank number before the interrupt occurs. bnkc cseg at 7000h bnkitm000: ; inter-memory ban k interrupt servicing routine push ax ; saves the contents of the ax register. mov a,bank mov r_bnkrn,a ; saves the memory bank number before the interrupt to ram. mov bank,#banknum test ; specifies the memo ry bank number of the interrupt routine. call !test ; calls the interrupt routine. mov a,r_bnkrn ; restores the memory bank number before the interrupt. mov bank,a pop ax ; restores the contents of the ax register. reti bn3 cseg bank3 test: ; interrupt servicing routine mov ??? : : ret end 78k0/kx2 chapter 4 memory bank select function r01uh0008ej0401 rev.4.01 158 jul 15, 2010 remark note the following points to use the memory bank select function efficiently. ? allocate a routine that is used often in the common area. ? if a value that is planned to be referenced is placed in ram, it can be referenced from all of the areas. ? if the reference destination and the branch destination of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. ? allocate interrupt servicing that requires a quick response in the common area. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 159 jul 15, 2010 chapter 5 port functions 5.1 port functions pin i/o buffer power supplies depend on the product. the relati onship between these power supplies and the pins is shown below. table 5-1. pin i/o buffer power supplies (av ref , v dd ) ? 78k0/kb2: 30-pin plastic ssop (7.62 mm (300)) ? 78k0/kc2: 38-pin plastic ssop (7.62 mm (300)), 44-pin plastic lqfp (10x10), 48-pin plastic lqfp (fine pitch) (7x7) ? 78k0/kd2: 52-pin plastic lqfp (10x10) power supply corresponding pins av ref p20 to p27 v dd pins other than p20 to p27 table 5-2. pin i/o buffer power supplies (av ref , ev dd , v dd ) ? 78k0/kb2: 36-pin plastic flga (4x4) ? 78k0/ke2: 64-pin plastic lqfp (fine pi tch) (10x10), 64-pin plastic lqfp (14x 14), 64-pin plastic lqfp (12x12), 64- pin plastic tqfp (fine pitch) (7x7), 64-pin pl astic flga (5x5) , 64-pin plastic fbga (4x4) ? 78k0/kf2: 80-pin plastic lqfp (14x14), 80- pin plastic lqfp (fine pitch) (12x12) power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 and p121 to p124 v dd ? p121 to p124 ? non-port pins 78k0/kx2 microcontrollers are pr ovided with digital i/o ports, which enable vari ety of control operatio ns. the functions of each port are shown in table 5-3. in addition to the function as digital i/o ports, these ports have several alternate fu nctions. for details of the alternate functions, see chapter 2 pin functions . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 160 jul 15, 2010 table 5-3. port functions (1/3) kb2 kc2 kd2 kes kf2 function name i/o function after reset alternate function p00 ti000 p01 ti010/to00 ? ? note 1 note 2 p02 so11 ? ? note 1 note 2 p03 si11 ? ? ? note 2 p04 sck11 ? ? ? note 2 p05 ti001/ssi11 ? ? ? note 2 p06 i/o port 0. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti011/to01 p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti50/to50 p20 ani0 p21 ani1 p22 ani2 p23 ani3 ? p24 ani4 ? p25 ani5 ? note 3 p26 ani6 ? note 3 p27 i/o port 2. i/o port. input/output can be specified in 1-bit units. analog input ani7 p30 intp1 p31 intp2/ ocd1a note 4 p32 intp3/ ocd1b note 4 p33 i/o port 3. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. analog input ti51/to51/ intp4 notes 1. the 78k0/kd2 products are only provided with port functions (p02 and p03) and not alternate functions. 2. the 78k0/ke2 products whose flash memory is less th an 32 kb are only provided with port functions (p02 to p06) and not alternate functions. the 78k0/ke2 products whose flas h memory is at least 48 kb are provided with port functions (p02 to p06) and alternate functions. 3. this is not mounted onto 38-pin pro ducts of the 78k0/kc2. for the 38-pin products, be sure to set bits 6 and 7 of pm2 to ?1? and bits 6 and 7 of p2 to ?0?. 4. ocd1a and ocd1b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted, ? : not mounted 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 161 jul 15, 2010 table 5-3. port functions (2/3) kb2 kc2 kd2 kes kf2 function name i/o function after reset alternate function ? note 1 p40 ? ? note 1 p41 ? ? ? ? p42 ? ? ? ? p43 ? ? ? ? ? p44 ? ? ? ? ? p45 ? ? ? ? ? p46 ? ? ? ? ? p47 i/o port 4. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? ? ? ? p50 ? ? ? ? p51 ? ? ? ? p52 ? ? ? ? p53 ? ? ? ? ? p54 ? ? ? ? ? p55 ? ? ? ? ? p56 ? ? ? ? ? p57 i/o port 5. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 ? p62 exscl0 ? p63 ? ? ? ? ? p64 ? ? ? ? ? p65 ? ? ? ? ? p66 ? ? ? ? ? p67 i/o port 6. i/o port. output of p60 to p63 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. only for p64 to p67, use of an on-chip resistor can be specified by a software setting. input port ? ? p70 kr0 ? p71 kr1 ? note 1 p72 kr2 ? note 1 p73 kr3 ? note 2 p74 kr4 ? note 2 p75 kr5 ? ? p76 kr6 ? ? p77 i/o port 7. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr7 notes 1. this is not mounted onto 38-pin pro ducts of the 78k0/kc2. for the 38-pin products, be sure to set bits 0 and 1 of pm4, bits 2 and 3 of pm7, bits 0 an d 1 of p4, and bits 2 and 3 of p7 to ?0?. 2. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. the 48- pin products are only provided with port functions (p74 to p75) and not alternate functions. remark : mounted, ? : not mounted 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 162 jul 15, 2010 table 5-3. port functions (3/3) kb2 kc2 kd2 kes kf2 function name i/o function after reset alternate function p120 intp0/exlvi p121 x1/ocd0a note 3 p122 x2/exclk/ ocd0b note 3 ? p123 xt1 ? p124 i/o port 12. i/o port. input/output can be specified in 1-bit units. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2/exclks ? note 1 p130 output port 13. output-only port. output port ? ? note 1 p140 pcl/intp6 ? ? ? note 2 p141 buz/busy0/ intp7 ? ? ? ? p142 scka0 ? ? ? ? p143 sia0 ? ? ? ? p144 soa0 ? ? ? ? p145 i/o port 14. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port stb0 notes 1. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. 2. the 78k0/ke2 products are not prov ided with the busy0 input function. 3. ocd0a and ocd0b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted, ? : not mounted 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 163 jul 15, 2010 5.2 port configuration ports include the following hardware. table 5-4. port configuration item configuration control registers ? 78k0/kb2 port mode register (pmxx): pm0 to pm3, pm6, pm12 port register (pxx): p0 to p3, p6, p12 pull-up resistor option register (puxx): pu0, pu1, pu3, pu12 a/d port configuration register (adpc) ? 38-pin and 44-pin products of 78k0/kc2 port mode register (pmxx): pm0 to pm4, pm6, pm7, pm12 port register (pxx): p0 to p4, p6, p7, p12 pull-up resistor option register (puxx): pu0, pu1, pu3, pu4, pu7, pu12 a/d port configuration register (adpc) ? 48-pin products of 78k0/kc2, 78k0/kd2 port mode register (pmxx): pm0 to pm4, pm6, pm7, pm12, pm14 port register (pxx): p0 to p4, p6, p7, p12 to p14 pull-up resistor option register (puxx): pu0, pu1, pu3, pu4, pu7, pu12, pu14 a/d port configuration register (adpc) ? 78k0/ke2 port mode register (pmxx): pm0 to pm7, pm12, pm14 port register (pxx): p0 to p7, p12 to p14 pull-up resistor option register (puxx): pu0, pu1, pu3 to pu5, pu7, pu12, pu14 a/d port configuration register (adpc) ? 78k0/kf2 port mode register (pmxx): pm0 to pm7, pm12, pm14 port register (pxx): p0 to p7, p12 to p14 pull-up resistor option register (puxx): pu0, pu1, pu3 to pu7, pu12, pu14 a/d port configuration register (adpc) port ? 78k0/kb2: total: 23 (cmos i/o: 21, n-ch open drain i/o: 2) ? 38-pin products of 78k0/kc2: total: 31 (cmos i/o: 27, n-ch open drain i/o: 4) ? 44-pin products of 78k0/kc2: total: 37 (cmos i/o: 33, n-ch open drain i/o: 4) ? 48-pin products of 78k0/kc2: total: 41 (cmos i/o: 36, cmos output: 1, n-ch open drain i/o: 4) ? 78k0/kd2: total: 45 (cmos i/o: 40, cmos output: 1, n-ch open drain i/o: 4) ? 78k0/ke2: total: 55 (cmos i/o: 50, cmos output: 1, n-ch open drain i/o: 4) ? 78k0/kf2: total: 71 (cmos i/o: 66, cmos output: 1, n-ch open drain i/o: 4) pull-up resistor ? 78k0/kb2: total: 15 ? 38-pin products of 78k0/kc2: total: 17 ? 44-pin products of 78k0/kc2: total: 21 ? 48-pin products of 78k0/kc2: total: 24 ? 78k0/kd2: total: 28 ? 78k0/ke2: total: 38 ? 78k0/kf2: total: 54 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 164 jul 15, 2010 5.2.1 port 0 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p00/ti000 p01/ti010/to00 p02/so11 ? p02 note p02 note p03/si11 ? p03 note p03 note p04/sck11 ? ? p04 note p05/ti001/ssi11 ? ? p05 note p06/ti011/to01 ? ? p06 note note the 78k0/ke2 products whose flash memory is less than 32 kb and 78k0/kd2 products are only provided with port functions and not alternate functions. remark : mounted, ? : not mounted port 0 is an i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o, serial in terface data i/o, clock i/o, and chip select input. reset signal generation sets port 0 to input mode. figures 5-1 to 5-6 show block diagrams of port 0. caution to use p02/so11 and p04/sck11 as general-purpo se ports, set serial operati on mode register 11 (csim11) and serial clock selection register 11 (csic11) to the default status (00h). 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 165 jul 15, 2010 figure 5-1. block diagram of p00 p00/ti000 wr pu rd wr port wr pm pu00 alternate function output latch (p00) pm00 ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 166 jul 15, 2010 figure 5-2. block diagram of p01 p01/ti010/to00 wr pu rd wr port wr pm pu01 alternate function output latch (p01) pm01 alternate function ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 167 jul 15, 2010 figure 5-3. block diagram of p02 (1/2) (1) 78k0/ke2 products whose flash memory is less than 32 kb and 78k0/kd2 p02 wr pu rd wr port wr pm pu02 pm02 ev dd p-ch pu0 pm0 p0 internal bus output latch (p02) selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 168 jul 15, 2010 figure 5-3. block diagram of p02 (2/2) (2) 78k0/ke2 products whose flash memory is at least 48 kb and 78k0/kf2 p02/so11 wr pu rd wr port wr pm pu02 output latch (p02) pm02 alternate function ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 169 jul 15, 2010 figure 5-4. block diagram of p03 and p05 (1/2) (1) 78k0/ke2 products whose flash memo ry is less than 32 kb and 78k0/kd2 p03, p05 wr pu rd wr port wr pm pu03, pu05 pm03, pm05 p-ch pu0 pm0 p0 internal bus output latch (p03, p05) selector ev dd p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remarks 1. 78k0/kd2: p03 (not mounted with p05) 78k0/ke2 products whose flash memory is less than 32 kb: p03 and p05 2. with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 170 jul 15, 2010 figure 5-4. block diagram of p03 and p05 (2/2) (2) 78k0/ke2 products whose flash memo ry is at least 48 kb and 78k0/kf2 p03/si11, p05/ssi11/ti001 wr pu rd wr port wr pm pu03, pu05 alternate function output latch (p03, p05) pm03, pm05 ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 171 jul 15, 2010 figure 5-5. block diagram of p04 (1/2) (1) 78k0/ke2 products whose flash memory is less than 32 kb p04 wr pu rd wr port wr pm pu04 pm04 ev dd p-ch pu0 pm0 p0 internal bus output latch (p04) selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 172 jul 15, 2010 figure 5-5. block diagram of p04 (2/2) (2) 78k0/ke2 products whose flash memo ry is at least 48 kb and 78k0/kf2 p04/sck11 wr pu rd wr port wr pm pu04 alternate function output latch (p04) pm04 alternate function ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 173 jul 15, 2010 figure 5-6. block diagram of p06 (1/2) (1) 78k0/ke2 products whose flash memory is less than 32 kb p06 wr pu rd wr port wr pm pu06 pm06 ev dd p-ch pu0 pm0 p0 internal bus output latch (p06) selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 174 jul 15, 2010 figure 5-6. block diagram of p06 (2/2) (2) 78k0/ke2 products whose flash memo ry is at least 48 kb and 78k0/kf2 p06/ti011/to01 wr pu rd wr port wr pm pu06 alternate function output latch (p06) pm06 alternate function ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 175 jul 15, 2010 5.2.2 port 1 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p10/sck10/txd0 p11/si10/rxd0 p12/so10 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 remark : mounted port 1 is an i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset signal generation sets port 1 to input mode. figures 5-7 to 5-11 show block diagrams of port 1. cautions 1. to use p10/sck10/txd0 and p12/so10 as general-purpose ports, set serial operation mode register 10 (csim10) and serial clock selection regi ster 10 (csic10) to the default status (00h). 2. to use p13/txd6 as general-purpose port, clear bit 0 (txdlv6) of asynchronous serial interface control register 6 (asicl6) to 0 (normal output of txd6). 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 176 jul 15, 2010 figure 5-7. block diagram of p10 p10/sck10/txd0 wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 177 jul 15, 2010 figure 5-8. block diagram of p11 and p14 p11/si10/rxd0, p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 178 jul 15, 2010 figure 5-9. block diagram of p12 and p15 p12/so10 p15/toh0 wr pu rd wr port wr pm pu12, pu15 output latch (p12, p15) pm12, pm15 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 179 jul 15, 2010 figure 5-10. blo ck diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function ev dd p-ch internal bus selector pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 180 jul 15, 2010 figure 5-11. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 181 jul 15, 2010 5.2.3 port 2 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 ? p25/ani5 ? p26/ani6 ? note p27/ani7 ? note note this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin pr oducts, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. remark : mounted, ? : not mounted port 2 is an i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for a/d converter analog input. to use p20/ani0 to p27/ani7 as digita l input pins, set them in the digital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm 2. use these pins starting from the lower bit. to use p20/ani0 to p27/ani7 as digital output pins, set them in the digital i/o mode by using adpc and in the output mode by using pm2. table 5-5. setting functions of p20/ani0 to p27/ani7 pins adpc pm2 ads p20/ani0 to p27/ani7 pin input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p20/ani0 to p27/ani7 are set in the anal og input mode when the reset signal is generated. figure 5-12 shows a block diagram of port 2. caution make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 182 jul 15, 2010 figure 5-12. block di agram of p20 to p27 internal bus p20/ani0 to p27/ani7 rd wr port wr pm output latch (p20 to p27) pm20 to pm27 selector pm2 a/d converter p2 p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal caution for the 38-pin products of 78k0/k c2, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 183 jul 15, 2010 5.2.4 port 3 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p30/intp1 p31/intp2/ ocd1a note p32/intp3/ ocd1b note p33/intp4/ti51/ to51 note ocd1a and ocd1b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted port 3 is an i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input and timer i/o. reset signal generation sets port 3 to input mode. figures 5-13 and 5-14 show block diagrams of port 3. cautions 1. in the product wit h an on-chip debug function ( p78f05xxd and d78f05xxda), be sure to pull the p31/intp2/ocd1a pin down before a rese t release, to prevent malfunction. 2. process the p31/intp2/ocd1a pin of the pr oducts mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. p31/intp2/ocd1a flash memory programmer connection during reset connect to ev ss note via a resistor. on-chip debug emulator connection (when it is not used as an on-chip debug mode setting pin) during reset released input: connect to ev dd note or ev ss note via a resistor. output: leave open. note with products without an ev ss pin, connect them to v ss . with products without an ev dd pin, connect them to v dd . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 184 jul 15, 2010 remark p31 and p32 of the product with an on-chip debug function ( pd78f05xxd and 78f05xxda) can be used as on-chip debug mode setting pins (ocd1a, ocd1b) when the on-chip debug function is used. for how to connect an on-chip debug em ulator (qb-mini2), see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only). figure 5-13. block di agram of p30 to p32 p30/intp1, p31/intp2/ocd1a, p32/intp3/ocd1b wr pu rd wr port wr pm pu30 to pu32 alternate function output latch (p30 to p32) pm30 to pm32 ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 185 jul 15, 2010 figure 5-14. blo ck diagram of p33 p33/intp4/ti51/to51 wr pu rd wr port wr pm pu33 alternate function output latch (p33) pm33 alternate function ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 186 jul 15, 2010 5.2.5 port 4 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p40 ? note p41 ? note p42 ? ? p43 ? ? p44 ? ? ? p45 ? ? ? p46 ? ? ? p47 ? ? ? note this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin pr oducts, be sure to set bits 0 and 1 of pm4 and p4 to ?0?. remark : mounted, ? : not mounted port 4 is an i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 to p47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (pu4). reset signal generation sets port 4 to input mode. figure 5-15 shows a block diagram of port 4. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 187 jul 15, 2010 figure 5-15. block diag ram of p40 to p47 rd p-ch wr pu wr port wr pm ev dd p40 to p47 pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector internal bus pu4 pm4 p4 p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal caution for the 38-pin products of 78k0/kc2, be sure to set bits 0 and 1 of pm4 and p4 to ?0?. remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 188 jul 15, 2010 5.2.6 port 5 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p50 ? p51 ? p52 ? p53 ? p54 ? ? p55 ? ? p56 ? ? p57 ? ? remark : mounted, ? : not mounted port 5 is an i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). when the p50 to p57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (pu5). reset signal generation sets port 5 to input mode. figure 5-16 shows a block diagram of port 5. figure 5-16. block diag ram of p50 to p57 rd p-ch wr pu wr port wr pm ev dd p50 to p57 pu50 to pu57 output latch (p50 to p57) pm50 to pm57 selector internal bus pu5 pm5 p5 p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 189 jul 15, 2010 5.2.7 port 6 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p60/scl0 p61/sda0 p62/exscl0 ? p63 ? p64 ? ? p65 ? ? p66 ? ? p67 ? ? remark : mounted, ? : not mounted port 6 is an i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). when the p64 to p67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (pu6). the output of the p60 to p63 pins is n- ch open-drain output (6 v tolerance). this port can also be used for serial interf ace data i/o, clock i/o, and external clock input. reset signal generation sets port 6 to input mode. figures 5-17 to 5-20 show block diagrams of port 6. remark when using p62/exscl0 as an external clock input pin of t he serial interface, input a clock of 6.4 mhz to it. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 190 jul 15, 2010 figure 5-17. block diagram of p60 and p61 p60/scl0, p61/sda0 rd wr port wr pm alternate function output latch (p60, p61) pm60, pm61 alternate function internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal caution a through current flows thr ough p60 and p61 if an intermediate potential is input to these pins, because the input buffer is also tu rned on when p60 and p61 are in output mode. consequently, do not input an intermediate potential when p60 and p61 are in output mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 191 jul 15, 2010 figure 5-18. block diagram of p62 p62/exscl0 rd wr port wr pm alternate function output latch (p62) pm62 internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal caution a through current flows through p62 if an intermediate potential is input to this pin, because the input buffer is also turned on when p62 is in output mode. consequently, do not input an intermediate potential when p62 is in output mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 192 jul 15, 2010 figure 5-19. block diagram of p63 p63 rd wr port wr pm output latch (p63) pm63 internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 193 jul 15, 2010 figure 5-20. block di agram of p64 to p67 p64 to p67 rd wr port wr pm output latch (p64 to p67) pm64 to pm67 pm6 wr pu pu64 to pu67 ev dd p-ch pu6 selector internal bus p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 194 jul 15, 2010 5.2.8 port 7 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p70/kr0 ? p71/kr1 ? p72/kr2 ? note 1 p73/kr3 ? note 1 p74/kr4 ? p74 note 2 p75/kr5 ? p75 note 2 p76/kr6 ? ? p77/kr7 ? ? notes 1. this is not mounted onto 38-pin produc ts of the 78k0/kc2. for the 38-pin products, be sure to set bits 2 and 3 of pm7 and p7 to ?0?. 2. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. the 48-pin products are only provided with port functions and not alternate functions. remark : mounted, ? : not mounted port 7 is an i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). this port can also be used for key return input. reset signal generation sets port 7 to input mode. figure 5-21 shows a block diagram of port 7. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 195 jul 15, 2010 figure 5-21. block di agram of p70 to p77 p70/kr0 to p77/kr7 wr pu rd wr port wr pm pu70 to pu77 alternate function output latch (p70 to p77) pm70 to pm77 ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal caution for the 38-pin products of 78k0/kc2, be sure to set bits 2 and 3 of pm7 and p7 to ?0?. remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 196 jul 15, 2010 5.2.9 port 12 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p120/intp0/exlvi p121/x1/ocd0a note p122/x2/exclk/ ocd0b note p123/xt1 ? p124/xt2/exclks ? note ocd0a and ocd0b are provided to the pr oducts with an on-chip debug function ( pd78f05xxd and 78f05xxda) only. remark : mounted, ? : not mounted port 12 is an i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input port only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used as pins for external interrupt re quest input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resona tor for subsystem clock, exte rnal clock input for main system clock, and external clock input for subsystem clock. reset signal generation sets port 12 to input mode. figures 5-22 and 5-23 show block diagrams of port 12. caution 1. when using the p121 to p 124 pins to connect a resonator for the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an exter nal clock for the main system clock (exclk) or subsystem clock (exclks), the x1 oscillation mode, xt1 oscillation mo de, or external clock input mode must be set by using the clock operati on mode select register (oscctl) (for details, see 6.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin). the reset value of oscctl is 00h (all of th e p121 to p124 pins are i/o port pins). at this time, setting of the pm121 to pm124 and p121 to p124 pins is not necessary. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 197 jul 15, 2010 caution 2. process the p121/x1/oc d0a pin of the products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. p121/x1/ocd0a flash memory programmer connection during reset connect to v ss via a resistor. on-chip debug emulator connection (when it is not used as an on-chip debug mode setting pin) during reset released input: connect to v dd or v ss via a resistor. output: leave open. remark x1 and x2 of the product with an on-chip debug function ( pd78f05xxd and 78f05xxda) can be used as on-chip debug mode setting pins (ocd0a, ocd0b) when the on-chip debug function is used. for how to connect an on-chip debug em ulator (qb-mini2), see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only). figure 5-22. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch pu12 pm12 p12 selector internal bus p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 198 jul 15, 2010 figure 5-23. block di agram of p121 to p124 p122/x2/exclk/ocd0b, p124/xt2/exclks rd wr port wr pm output latch (p122/p124) pm122/pm124 pm12 p12 rd wr port wr pm output latch (p121/p123) pm121/pm123 pm12 p12 exclk, oscsel/ exclks, oscsels oscctl oscsel/ oscsels oscctl p121/x1/ocd0a, p123/xt1 oscsel/ oscsels oscctl oscsel/ oscsels oscctl internal bus selector selector p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 oscctl: clock operation mode select register rd: read signal wr : write signal 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 199 jul 15, 2010 5.2.10 port 13 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p130 ? note note this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. remark : mounted, ? : not mounted port 13 is an output-only port. figure 5-24 shows a block diagram of port 13. figure 5-24. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus p13 p13: port register 13 rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be dummy -output as the cpu reset signal. p130 set by software reset signal 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 200 jul 15, 2010 5.2.11 port 14 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 p140/pcl/intp6 ? note 1 p141/buz/busy0/ intp7 ? ? ? p141/buz/intp7 note 2 p142/scka0 ? ? ? ? p143/sia0 ? ? ? ? p144/soa0 ? ? ? ? p145/stb0 ? ? ? ? notes 1. this is not mounted onto 38-pin and 44-pin products of the 78k0/kc2. 2. the 78k0/ke2 products are not prov ided with the busy0 input function. remark : mounted, ? : not mounted port 14 is an i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 to p145 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for external interrupt request input, buzzer output, clock out put, serial interface data i/o, clock i/o, busy input, and strobe output. reset signal generation sets port 14 to input mode. figures 5-25 to 5-28 shows a block diagram of port 14. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 201 jul 15, 2010 figure 5-25. block di agram of p140 and p141 p140/pcl/intp6, p141/buz/busy0/intp7 wr pu rd wr port wr pm pu140, pu141 alternate function output latch (p140, p141) pm140, pm141 alternate function ev dd p-ch selector internal bus pu14 pm14 p14 p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 202 jul 15, 2010 figure 5-26. blo ck diagram of p142 p142/scka0 wr pu rd wr port wr pm pu142 pm142 ev dd p-ch pu14 pm14 alternate function output latch (p142) alternate function selector internal bus p14 p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 203 jul 15, 2010 figure 5-27. blo ck diagram of p143 p143/sia0 wr pu rd wr port wr pm pu143 pm143 ev dd p-ch pu14 pm14 alternate function output latch (p143) selector internal bus p14 p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 204 jul 15, 2010 figure 5-28. block di agram of p144 and p145 p144/soa0, p145/stb0 wr pu rd wr port wr pm pu144, pu145 pm144, pm145 ev dd p-ch pu14 pm14 output latch (p144, p145) alternate function selector internal bus p14 p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . 5.3 registers controlling port function port functions are controlled by the following four types of registers. ? port mode registers (pmxx) ? port registers (pxx) ? pull-up resistor option registers (puxx) ? a/d port configuration register (adpc) 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 205 jul 15, 2010 (1) port mode registers (pmxx) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. when port pins are used as alternate-function pins , set the port mode register by referencing 5.5 settings of port mode register and output latc h when using alternate function . figure 5-29. format of port mode register (78k0/kb2) 7 1 symbol pm0 6 1 5 1 4 1 3 1 2 1 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w 1 pm2 1 1 1 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w 1 pm6 1 1 1 1 1 pm61 pm60 ff26h ffh r/w 1 pm12 1 1 1 1 pm122 pm121 pm120 ff2ch ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 3, 6, 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm6, bits 3 to 7 of pm12 to 1. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 206 jul 15, 2010 figure 5-30. format of port mode register (78k0/kc2) 7 1 symbol pm0 6 1 5 1 4 1 3 1 2 1 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w 1 pm4 1 1 1 1 1 pm41 pm40 ff24h ffh r/w 1 pm6 1 1 1 pm63 pm62 pm61 pm60 ff26h ffh r/w 1 pm7 1 pm75 note pm74 note pm73 pm72 pm71 pm70 ff27h ffh r/w 1 pm12 1 1 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w 1 pm14 note 111111 pm140 note ff2eh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 4, 6, 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) note 48-pin products only caution for the 38-pin products, be sure to set bits 2 to 7 of pm0, bits 6 and 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 4 to 7 of pm7, and bits 5 to 7 of pm12 to ?1?. also, be sure to set bits 0 and 1 of pm4, and bits 2 and 3 of pm7 to ?0?. for the 44-pin products, be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 4 to 7 of pm 7, and bits 5 to 7 of pm12 to ?1?. for the 48-pin products, be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 6 and 7 of pm7, bits 5 to 7 of pm12, and bits 1 to 7 of pm14 to ?1?. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 207 jul 15, 2010 figure 5-31. format of port mode register (78k0/kd2) 7 1 symbol pm0 6 1 5 1 4 1 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm4 1 1 pm41 pm40 ff24h ffh r/w 1111 pm6 pm63 pm62 pm61 pm60 ff26h ffh r/w pm77 pm7 pm76 pm75 pm74 pm73 pm72 pm71 pm70 ff27h ffh r/w 1 pm12 1 1 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w 1 pm14 1 1 pm140 ff2eh ffh r/w 1111 1111 pmmn pmn pin i/o mode selection (m = 0 to 4, 6, 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 4 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 5 to 7 of pm12, and bits 1 to 7 of pm14 to 1. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 208 jul 15, 2010 figure 5-32. format of port mode register (78k0/ke2) 7 1 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm4 pm43 pm42 pm41 pm40 ff24h ffh r/w pm5 pm53 pm52 pm51 pm50 ff25h ffh r/w pm6 pm63 pm62 pm61 pm60 ff26h ffh r/w pm77 pm7 pm76 pm75 pm74 pm73 pm72 pm71 pm70 ff27h ffh r/w 1 pm12 1 1 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w 1 pm14 1 pm141 pm140 ff2eh ffh r/w 1111 1111 1111 1111 pmmn pmn pin i/o mode selection (m = 0 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bit 7 of pm0, bi ts 4 to 7 of pm3, bits 4 to 7 of pm 4, bits 4 to 7 of pm5, bits 4 to 7 of pm6, bits 5 to 7 of pm12, a nd bits 2 to 7 of pm14 to ?1?. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 209 jul 15, 2010 figure 5-33. format of port mode register (78k0/kf2) 7 1 symbol pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w pm17 pm1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm27 pm2 pm26 pm25 pm24 pm47 pm46 pm45 pm44 pm57 pm56 pm55 pm54 pm67 pm66 pm65 pm64 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm4 pm43 pm42 pm41 pm40 ff24h ffh r/w pm5 pm53 pm52 pm51 pm50 ff25h ffh r/w pm6 pm63 pm62 pm61 pm60 ff26h ffh r/w pm77 pm7 pm76 pm75 pm74 pm73 pm72 pm145 pm144 pm143 pm142 pm71 pm70 ff27h ffh r/w 1 pm12 1 1 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w 1 pm14 1 pm141 pm140 ff2eh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bit 7 of pm0, bits 4 to 7 of pm3, bits 5 to 7 of pm12, and bits 6 and 7 of pm14 to ?1?. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 210 jul 15, 2010 (2) port registers (pxx) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the output latch value is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 5-34. format of port register (78k0/kb2) 7 0 symbol p0 6 0 5 0 4 0 3 0 2 0 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w 0 p2 0 0 0 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w 0 p6 0 0 0 0 0 p61 p60 ff06h 00h (output latch) r/w 0 p12 0 0 0 0 p120 ff0ch 00h (output latch) r/w p122 note p121 note m = 0 to 3, 6, 12; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note ?0? is always read from the output latch of p121 and p122 if the pin is in the external clock input mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 211 jul 15, 2010 figure 5-35. format of port register (78k0/kc2) 7 0 symbol p0 6 0 5 0 4 0 3 0 2 0 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w 0 p4 0 0 0 0 0 p41 p40 ff04h 00h (output latch) r/w 0 p6 0 0 0 p63 p62 p61 p60 ff06h 00h (output latch) r/w 0 p7 0 p75 note 1 p74 note 1 p73 p72 p71 p70 ff07h 00h (output latch) r/w 0 p12 0 0 p124 note 2 p123 note 2 p122 note 2 p121 note 2 p120 ff0ch 00h (output latch) r/w 0 p13 note 1 0 0 0 0 0 0 p130 note 1 ff0dh 00h (output latch) r/w 0 p14 note 1 0 0 0 0 0 0 p140 note 1 ff0eh 00h (output latch) r/w m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level notes 1. 48-pin products only 2. ?0? is always read from the output latch of p121 to p1 24 if the pin is in the external clock input mode. caution for the 38-pin products, be sure to set bits 6 a nd 7 of p2, bits 0 and 1 of p4, and bits 2 and 3 of p7 to ?0?. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 212 jul 15, 2010 figure 5-36. format of port register (78k0/kd2) 7 0 symbol p0 6 0 5 0 4 0 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w 0 p4 0 0 0 0 0 p41 p40 ff04h 00h (output latch) r/w 0 p6 0 0 0 p63 p62 p61 p60 ff06h 00h (output latch) r/w p77 p7 p76 p75 p74 p73 p72 p71 p70 ff07h 00h (output latch) r/w 0 p12 0 0 p124 note p123 note p122 note p121 note p120 ff0ch 00h (output latch) r/w 0 p13 0 0 0 0 0 0 p130 ff0dh 00h (output latch) r/w 0 p14 0 0 0 0 0 0 p140 ff0eh 00h (output latch) r/w m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note ?0? is always read from the output latch of p121 to p1 24 if the pin is in the external clock input mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 213 jul 15, 2010 figure 5-37. format of port register (78k0/ke2) 7 0 symbol p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w p4 p43 p42 p41 p40 ff04h 00h (output latch) r/w p5 p53 p52 p51 p50 ff05h 00h (output latch) r/w p6 p63 p62 p61 p60 ff06h 00h (output latch) r/w p77 p7 p76 p75 p74 p73 p72 p71 p70 ff07h 00h (output latch) r/w 0 p12 0 0 p124 note p123 note p122 note p121 note p120 ff0ch 00h (output latch) r/w 0 p13 0 0 0 0 0 0 p130 ff0dh 00h (output latch) r/w 0 p14 0 p141 p140 ff0eh 00h (output latch) r/w 0000 0000 0000 0000 m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note ?0? is always read from the output latch of p121 to p1 24 if the pin is in the external clock input mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 214 jul 15, 2010 figure 5-38. format of po rt register (78k0/kf2) 7 0 symbol p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w p17 p1 p16 p15 p14 p13 p12 p11 p10 ff01h 00h (output latch) r/w r/w p27 p2 p26 p25 p24 p47 p46 p45 p44 p57 p56 p55 p54 p67 p66 p65 p64 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 0 p33 p32 p31 p30 ff03h 00h (output latch) r/w p4 p43 p42 p41 p40 ff04h 00h (output latch) r/w p5 p53 p52 p51 p50 ff05h 00h (output latch) r/w p6 p63 p62 p61 p60 ff06h 00h (output latch) r/w p77 p7 p76 p75 p74 p73 p72 p145 p144 p143 p142 p71 p70 ff07h 00h (output latch) r/w 0 p12 0 0 p124 note p123 note p122 note p121 note p120 ff0ch 00h (output latch) r/w 0 p13 0 0 0 0 0 0 p130 ff0dh 00h (output latch) r/w 0 p14 0 p141 p140 ff0eh 00h (output latch) r/w m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note ?0? is always read from the output latch of p121 to p1 24 if the pin is in the external clock input mode. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 215 jul 15, 2010 (3) pull-up resistor option registers (puxx) these registers specify whether the on-ch ip pull-up resistors are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers. on-chip pull-up resistor s cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardl ess of the settings of these registers. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 5-39. format of pull-up resist or option register (78k0/kb2) 7 0 symbol pu0 6 0 5 0 4 0 3 0 2 0 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 12; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 216 jul 15, 2010 figure 5-40. format of pull-up resist or option register (78k0/kc2) 7 0 symbol pu0 6 0 5 0 4 0 3 0 2 0 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w 0 pu4 0 0 0 0 0 pu41 pu40 ff34h 00h r/w 0 pu7 0 pu75 note pu74 note pu73 pu72 pu71 pu70 ff37h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 note 000000 pu140 note ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 4, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected note 48-pin products only 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 217 jul 15, 2010 figure 5-41. format of pull-up resist or option register (78k0/kd2) 7 0 symbol pu0 6 0 5 0 4 0 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w 0 pu4 0 0 0 0 0 pu41 pu40 ff34h 00h r/w pu77 pu7 pu76 pu75 pu74 pu73 pu72 pu71 pu70 ff37h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 0 0 0 0 0 0 pu140 ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 4, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 218 jul 15, 2010 figure 5-42. format of pull-up resist or option register (78k0/ke2) 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w pu4 pu43 pu42 pu41 pu40 ff34h 00h r/w pu5 pu53 pu52 pu51 pu50 ff35h 00h r/w pu77 pu7 pu76 pu75 pu74 pu73 pu72 pu71 pu70 ff37h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 0 pu141 pu140 ff3eh 00h r/w 0000 0000 0000 pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 219 jul 15, 2010 figure 5-43. format of pull-up resist or option register (78k0/kf2) 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w pu17 pu1 pu16 pu15 pu14 pu47 pu46 pu45 pu44 pu57 pu56 pu55 pu54 pu67 pu66 pu65 pu64 pu13 pu12 pu11 pu10 ff31h 00h r/w 0 pu3 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w pu4 pu43 pu42 pu41 pu40 ff34h 00h r/w pu5 pu53 pu52 pu51 pu50 ff35h 00h r/w pu6 00 00 ff36h 00h r/w pu77 pu7 pu76 pu75 pu74 pu73 pu72 pu145 pu144 pu143 pu142 pu71 pu70 ff37h 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 0 pu141 pu140 ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected (4) a/d port configuration register (adpc) this register switches the p20/ani0 to p27/ani7 pins to digital i/o of port or anal og input of a/d converter. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark p20/ani0 to p23/ani3 pins: 78k0/kb2 p20/ani0 to p25/ani5 pins: 38-pin products of 78k0/kc2 p20/ani0 to p27/ani7 pins: products other than above 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 220 jul 15, 2010 figure 5-44. format of a/d port configuration register (adpc) adpc0 adpc1 adpc2 adpc3 0 0 0 0 digital i/o (d)/analog input (a) switching setting prohibited adpc3 0 1 2 3 4 5 6 7 adpc kb2 38-pin products of kc2 products other than the right address: ff2fh after reset: 00h r/w symbol p27/ ani7 a a a a a a a a d p26/ ani6 a a a a a a a d d p25/ ani5 a a a a a a d d d p24/ ani4 a a a a a d d d d p23/ ani3 a a a a d d d d d p22/ ani2 a a a d d d d d d p21/ ani1 a a d d d d d d d p20/ ani0 a d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc2 0 0 0 0 1 1 1 1 0 adpc1 0 0 1 1 0 0 1 1 0 adpc0 0 1 0 1 0 1 0 1 0 other than above note 1 note 1 note 2 note 1 note 2 notes 1. setting permitted 2. setting prohibited cautions 1. set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). 2. if data is written to adpc, a wait cycle is generated. do not write data to adpc when the peripheral hardware clock is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 221 jul 15, 2010 5.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 5.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch conten ts are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 5.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 5.4.3 operations on i/o port (1) output mode an operation is performed on the output latc h contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its contents. the result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated. 5.5 settings of port mode register and output latch when using alternate function to use the alternate function of a por t pin, set the port mode register and output latch as shown in table 5-6. remark the port pins mounted depend on the product. see table 5-3. port functions . 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 222 jul 15, 2010 table 5-6. settings of port mode register a nd output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 p02 so11 output 0 0 p03 si11 input 1 input 1 p04 sck11 output 0 1 ssi11 input 1 p05 ti001 input 1 ti011 input 1 p06 to01 output 0 0 input 1 sck10 output 0 1 p10 txd0 output 0 1 si10 input 1 p11 rxd0 input 1 p12 so10 output 0 0 p13 txd6 output 0 1 p14 rxd6 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 p20 to p27 note ani0 to ani7 note input 1 note the function of the ani0/p20 to ani7/p27 pins can be se lected by using the a/d po rt configuration register (adpc), the analog input channel spec ification register (ads), and pm2. adpc pm2 ads ani0/p20 to ani7/p27 pins selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited input mode ? digital input digital i/o selection output mode ? digital output remark : don?t care pm : port mode register p : port output latch 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 223 jul 15, 2010 table 5-6. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm p p30 to p32 intp1 to intp3 input 1 intp4 input 1 ti51 input 1 p33 to51 output 0 0 p60 scl0 i/o 0 0 p61 sda0 i/o 0 0 p62 exscl0 input 1 p70 to p77 kr0 to kr7 input 1 intp0 input 1 p120 exlvi input 1 p121 x1 note ? x2 note ? p122 exclk note input p123 xt1 note ? xt2 note ? p124 exclks note input pcl output 0 0 p140 intp6 input 1 buz output 0 0 intp7 input 1 p141 busy0 input 1 input 1 p142 scka0 output 0 1 p143 sia0 input 1 p144 soa0 output 0 0 p145 stb0 output 0 0 note when using the p121 to p124 pins to connect a resona tor for the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an external clock fo r the main system clock (exclk) or subsystem clock (exclks), the x1 oscillation mode, xt1 oscillation mode, or external clock input mode must be set by using the clock operation mode select regist er (oscctl) (for details, see 6.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin ). the reset value of oscctl is 00h (all of the p121 to p124 are i/o port pins). at this time, setting of pm121 to pm124 and p121 to p124 is not necessary. remarks 1. : don?t care pm : port mode register p : port output latch 2. x1, x2, p31, and p32 of the produc t with an on-chip debug function ( pd78f05xxd and 78f05xxda) can be used as on-chip debug mode setting pins (ocd0 a, ocd0b, ocd1a, and ocd1b) when the on-chip debug function is used. for how to connect an on-chip debug emulator (qb-mini2), see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only). 78k0/kx2 chapter 5 port functions r01uh0008ej0401 rev.4.01 224 jul 15, 2010 5.6 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to mani pulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 225 jul 15, 2010 chapter 6 clock generator 6.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 1 to 20 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop instruction or using the main osc control register (moc). <2> internal high-speed oscillator this circuit oscillates a clock of f rh = 8 mhz (typ.). after a reset rel ease, the cpu always starts operating with this internal high-speed oscillation clock. osc illation can be stopped by exec uting the stop instruction or using the internal oscill ation mode register (rcm). an external main system clock (f exclk = 1 to 20 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be disabled by executing the stop in struction or using rcm. as the main system clock, a high-speed system clock (x1 clock or external main system clock) or internal high- speed oscillation clock can be selected by using the main clock mode register (mcm). (2) subsystem clock note ? subsystem clock oscillator this circuit oscillates at a frequency of f xt = 32.768 khz by connecting a 32.76 8 khz resonator across xt1 and xt2. oscillation can be st opped by using the processor clock control register (pcc) and clock operation mode select register (oscctl). an external subsystem clock (f exclks = 32.768 khz) can also be supplied from the exclks/xt2/p124 pin. an external subsystem clock input can be disabled by setting pcc and oscctl. note the 78k0/kb2 is not provi ded with a subsystem clock. remark f x : x1 clock oscillation frequency f rh : internal high-speed oscillation clock frequency f exclk : external main system clock frequency f xt : xt1 clock oscillation frequency f exclks : external subsystem clock frequency 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 226 jul 15, 2010 (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f rl = 240 khz (typ.). after a reset release, the internal low-speed oscillation clock always starts operating. oscillation can be stopped by using the internal osci llation mode register (rcm) when ?internal low-speed oscillator can be stopped by software? is set by option byte. the internal low-speed oscillation clock cannot be used as the cpu clock. the fo llowing hardware operates with the internal low-speed oscillation clock. ? watchdog timer ? tmh1 (when f rl , f rl /2 7 , or f rl /2 9 is selected) remark f rl : internal low-speed oscillation clock frequency 6.2 configuration of clock generator the clock generator includes the following hardware. table 6-1. configuration of clock generator item configuration control registers clock operation mode select register (oscctl) processor clock control register (pcc) internal oscillation mode register (rcm) main osc control register (moc) main clock mode register (mcm) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillators x1 oscillator xt1 oscillator note internal high-speed oscillator internal low-speed oscillator note the 78k0/kb2 is not provided with an xt1 oscillator (subsystem clock). 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 227 jul 15, 2010 figure 6-1. block diagram of clock generator (78k0/kb2) option byte 1: cannot be stopped 0: can be stopped lsrstop rsts rstop f rl peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1 cpu clock (f cpu ) processor clock control register (pcc) pcc2 pcc1 pcc0 f xp x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) mcm0 xsel mcs mstop stop exclk oscsel amph clock operation mode select register (oscctl) 3 f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) f rh internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk /p122 f xh f x f exclk system clock switch peripheral hardware clock switch controller prescaler selector internal oscillation mode register (rcm) internal low- speed oscillator (240 khz (typ.)) internal high- speed oscillator (8 mhz (typ.)) 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 228 jul 15, 2010 figure 6-2. block diagram of clock generator (78k0/kc2, 78k 0/kd2, 78k0/ke2, and 78k0/kf2) option byte 1: cannot be stopped 0: can be stopped internal oscillation mode register (rcm) lsrstop rsts rstop internal high- speed oscillator (8 mhz (typ.)) internal low- speed oscillator (240 khz (typ.)) f rl clock operation mode select register (oscctl) oscsels exclks xt1/p123 xt2/exclks/ p124 f sub peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1 watch timer, clock output 1/2 cpu clock (f cpu ) processor clock control register (pcc) css pcc2 cls pcc1 pcc0 prescaler main system clock switch f xp peripheral hardware clock switch x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) controller mcm0 xsel mcs mstop exclk oscsel amph clock operation mode select register (oscctl) 4 f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) f rh internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk/ p122 f xh f sub 2 crystal oscillation external input clock subsystem clock oscillator f x f exclk f xt f exclks xtstart to subsystem clock oscillator xtstart processor clock control register (pcc) selector stop 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 229 jul 15, 2010 remark f x : x1 clock oscillation frequency f rh : internal high-speed oscillation clock frequency f exclk : external main system clock frequency f xh : high-speed system clock frequency f xp : main system clock frequency f prs : peripheral hardware clock frequency f cpu : cpu clock frequency f xt : xt1 clock oscillation frequency f exclks : external subsystem clock frequency f sub : subsystem clock frequency f rl : internal low-speed oscillation clock frequency 6.3 registers controlling clock generator the following seven registers are used to control the clock generator. ? clock operation mode sele ct register (oscctl) ? processor clock control register (pcc) ? internal oscillation mode register (rcm) ? main osc control register (moc) ? main clock mode register (mcm) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) (1) clock operation mode select register (oscctl) this register selects the operation mo des of the high-speed system and sub system clocks, and the gain of the on- chip oscillator. oscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 230 jul 15, 2010 figure 6-3. format of clock operation mode select register (oscctl) (78k0/kb2) address: ff9fh after reset: 00h r/w symbol <7> <6> 5 4 3 2 1 <0> oscctl exclk oscsel 0 0 0 0 0 amph exclk oscsel high-speed system clock pin operation mode p121/x1 pin p122/x2/exclk pin 0 0 i/o port mode i/o port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input amph operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz cautions 1. be sure to set amph to 1 if the high-speed system cl ock oscillation frequency exceeds 10 mhz. 2. set amph before setting the main clock mode register (mcm). 3. set amph before setting th e peripheral functions after a r eset release. the value of amph can be changed only once after a reset release. when th e high-speed system clock (x1 oscillation) is selected as the cpu clock, supply of the cpu clock is stopped for 4.06 to 16.12 s after amph is set to 1. when the high -speed system clock (external cl ock input) is selected as the cpu clock, supply of the cpu clock is stopped for the duration of 160 external clocks after amph is set to 1. 4. if the stop instruction is executed wh en amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is rel eased when the internal high- speed oscillation clock is sel ected as the cpu clock, or for the duration of 160 external clocks when the high- speed system clock (externa l clock input) is selected as the cpu clock. when th e high-speed system clock (x 1 oscillation) is selected as the cpu clock, the oscillation stabilization time is counted after the stop mode is released. 5. to change the value of exclk and oscsel , be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). 6. be sure to clea r bits 1 to 5 to 0. remark f xh : high-speed system clock oscillation frequency 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 231 jul 15, 2010 figure 6-4. format of clock operati on mode select register (oscctl) (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) address: ff9fh after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 <0> oscctl exclk oscsel exclks note oscsels note 0 0 0 amph exclk oscsel high-speed system clock pin operation mode p121/x1 pin p122/x2/exclk pin 0 0 i/o port mode i/o port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input amph operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note exclks and oscsels are used in combination with xtstart (bit 6 of the processor clock control register (pcc)). see (3) setting of operation mode for subsystem clock pin . cautions 1. be sure to set amph to 1 if the high-speed system cl ock oscillation frequency exceeds 10 mhz. 2. set amph before setting the main clock mode register (mcm). 3. set amph before setting th e peripheral functions after a r eset release. the value of amph can be changed only once after a reset release. when th e high-speed system clock (x1 oscillation) is selected as the cpu clock, supply of the cpu clock is stopped for 4.06 to 16.12 s after amph is set to 1. when the high -speed system clock (external cl ock input) is selected as the cpu clock, supply of the cpu clock is stopped for the duration of 160 external clocks after amph is set to 1. 4. if the stop instruction is executed wh en amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is rel eased when the internal high- speed oscillation clock is sel ected as the cpu clock, or for the duration of 160 external clocks when the high- speed system clock (externa l clock input) is selected as the cpu clock. when th e high-speed system clock (x 1 oscillation) is selected as the cpu clock, the oscillation stabilization time is counted after the stop mode is released. 5. to change the value of exclk and oscsel , be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). 6. be sure to clear bits 1 to 3 to 0. remark f xh : high-speed system clock oscillation frequency 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 232 jul 15, 2010 (2) processor clock control register (pcc) this register is used to select t he cpu clock, the division ratio, and operation mode for subsystem clock. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pcc to 01h. figure 6-5. format of processor clo ck control register (pcc) (78k0/kb2) address: fffbh after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 pcc 0 0 0 0 0 pcc2 pcc1 pcc0 cautions 1. be sure to clear bits 3 to 7 to 0. 2. the peripheral hardware clock (f prs ) is not divided when the division ratio of the pcc is set. remark f xp : main system clock oscillation frequency pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 other than above setting prohibited 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 233 jul 15, 2010 figure 6-6. format of processor clock control register (pcc) (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) address: fffbh after reset: 01h r/w note 1 symbol 7 6 <5> <4> 3 2 1 0 pcc 0 xtstart note2 cls css 0 pcc2 pcc1 pcc0 cls cpu clock status 0 main system clock 1 subsystem clock notes 1. bit 5 is read-only. 2. xtstart is used in combination with excl ks and oscsels (bits 5 and 4 of the clock operation mode select regi ster (oscctl)). see (3) setting of operation mode for subsystem clock pin . cautions 1. be sure to clear bits 3 and 7 to ?0?. 2. the peripheral hardware clock (f prs ) is not divided when the division ratio of the pcc is set. remark f xp : main system clock oscillation frequency f sub : subsystem clock oscillation frequency the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k 0/kx2 microcontrollers . therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 6-2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 0 1 0 0 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f sub /2 other than above setting prohibited 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 234 jul 15, 2010 table 6-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu main system clock high-speed system clock note 1 internal high-speed oscillation clock note 1 subsystem clock note 2 cpu clock (f cpu ) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f xp 0.2 s 0.1 s 0.25 s (typ.) ? f xp /2 0.4 s 0.2 s 0.5 s (typ.) ? f xp /2 2 0.8 s 0.4 s 1.0 s (typ.) ? f xp /2 3 1.6 s 0.8 s 2.0 s (typ.) ? f xp /2 4 3.2 s 1.6 s 4.0 s (typ.) ? f sub /2 note 2 ? ? 122.1 s notes 1. the main clock mode register (mcm) is used to set the main system clock supplied to cpu clock (high- speed system clock/internal high- speed oscillation clock) (see figure 6-9 ). 2. the 78k0/kb2 is not provi ded with a subsystem clock. (3) setting of operation mode for subsystem clock pin the operation mode for the subsystem clock pin note can be set by using bit 6 (xtstart) of the processor clock control register (pcc) and bits 5 and 4 (exclks, oscsels) of the clock operation mode select register (oscctl) in combination. note the 78k0/kb2 is not provi ded with a subsystem clock. table 6-3. setting of operati on mode for subsystem clock pin (78k0/kc2, 78k0/kd2, 78k0/ke2, 78k0/kf2) pcc oscctl bit 6 bit 5 bit 4 xtstart exclks oscsels subsystem clock pin operation mode p123/xt1 pin p124/xt2/exclks pin 0 0 0 i/o port mode i/o port 0 0 1 xt1 oscillation mode crystal resonator connection 0 1 0 i/o port mode i/o port 0 1 1 external clock input mode i/o port external clock input 1 xt1 oscillation mode crystal resonator connection caution confirm that bit 5 (cls) of the processor clock contro l register (pcc) is 0 (cpu is operating with main system clock) when cha nging the current values of xt start, exclks, and oscsels. remark : don?t care 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 235 jul 15, 2010 (4) internal oscillati on mode register (rcm) this register sets the operation mode of internal oscillator. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h note 1 . figure 6-7. format of internal oscillation mode register (rcm) address: ffa0h after reset: 80h note 1 r/w note 2 symbol <7> 6 5 4 3 2 <1> <0> rcm rsts 0 0 0 0 0 lsrstop rstop rsts status of internal high-speed oscillator 0 waiting for accuracy stabilizati on of internal high-speed oscillator 1 stability operating of internal high-speed oscillator lsrstop internal low-speed oscillator oscillating/stopped 0 internal low-speed oscillator oscillating 1 internal low-s peed oscillator stopped rstop internal high-speed oscillator oscillating/stopped 0 internal high-spe ed oscillator oscillating 1 internal high-speed oscillator stopped notes 1. the value of this register is 00h immediately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. 2. bit 7 is read-only. caution when setting rstop to 1, be sure to confirm that th e cpu operates with a clock other than the internal high-speed oscillation clo ck. specifically, set under either of the following conditions. <1> 78k0/kb2 ? when mcs = 1 (when cpu operates with the high-speed system clock) <2> 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 ? when mcs = 1 (when cpu operates with the high-speed system clock) ? when cls = 1 (when cpu opera tes with the subsystem clock) in addition, stop peripheral hardware that is operating on the intern al high-speed oscillation clock before setting rstop to 1. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 236 jul 15, 2010 (5) main osc control register (moc) this register selects the operati on mode of the high-speed system clock. this register is used to stop the x1 oscillator or to disable an external clock input from the exclk pin when the cpu operates with a clock other than the high-speed system clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h. figure 6-8. format of main osc control register (moc) address: ffa2h after reset: 80h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 control of high-speed system clock operation mstop x1 oscillation mode external clock input mode 0 x1 oscillator operating external clock from exclk pin is enabled 1 x1 oscillator stopped external clock from exclk pin is disabled cautions 1. when setting mstop to 1, be su re to confirm that the cpu operates with a clock other than the high-speed syst em clock. specifically, set under either of the following conditions. <1> 78k0/kb2 ? when mcs = 0 (when cpu operates wit h the internal high-speed oscillation clock) <2> 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 ? when mcs = 0 (when cpu operates wit h the internal high-speed oscillation clock) ? when cls = 1 (when cpu operat es with the subsystem clock) in addition, stop peripheral hardware that is operati ng on the high-speed system clock before setting mstop to 1. 2. do not clear mstop to 0 while bit 6 (oscsel) of the clock operation mode select register (oscctl) is 0 (i/o port mode). 3. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of th e peripheral hardware after the peripheral hardware clock has been stopped, in itialize the peri pheral hardware. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 237 jul 15, 2010 (6) main clock mode register (mcm) this register selects the main system clock supplied to cpu clock and clock supplied to peripheral hardware clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 6-9. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 <2> <1> <0> mcm 0 0 0 0 0 xsel mcs mcm0 selection of clock supplied to main system clock and peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) mcs main system clock status 0 operates with internal high-speed oscillation clock 1 operates with hi gh-speed system clock note bit 1 is read-only. cautions 1. xsel can be change d only once after a reset release. 2. do not rewrite mcm0 when the cp u clock operates with th e subsystem clock. 3. a clock other than f prs is supplied to the following peri pheral functions regardless of the setting of xsel and mcm0. ? watchdog timer (operates with intern al low-speed oscillation clock) ? when ?f rl ?, ?f rl /2 7 ?, or ?f rl /2 9 ? is selected as the count clock for 8-bit timer h1 (operates with internal low-speed oscillation clock) ? peripheral hardware selects the ext ernal clock as the clock source (except when the external count clock of tm 0n (n = 0, 1) is selected (ti00n pin valid edge)) 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 238 jul 15, 2010 (7) oscillation stabilization time c ounter status register (ostc) this is the register that indi cates the count status of the x1 clock oscill ation stabilization time counter. when x1 clock oscillation starts with the internal high -speed oscillatio n clock or subsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 6-10. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 239 jul 15, 2010 (8) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the oper ation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confi rm with ostc that the desired oscillation stabilization time has elapsed after the stop m ode is released. the oscillati on stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 6-11. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 204.8 s 102.4 s 0 1 0 2 13 /f x 819.2 s 409.6 s 0 1 1 2 14 /f x 1.64 ms 819.2 s 1 0 0 2 15 /f x 3.27 ms 1.64 ms 1 0 1 2 16 /f x 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 cl ock is used as the cpu cl ock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 240 jul 15, 2010 6.4 system clock oscillator 6.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (1 to 20 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. figure 6-12 shows an example of the exte rnal circuit of the x1 oscillator. figure 6-12. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock x1 x2 v ss exclk external clock cautions are listed on the next page. 6.4.2 xt1 oscillator the xt1 oscillator note oscillates with a crystal resonator (standard: 32. 768 khz) connected to the xt1 and xt2 pins. an external clock can also be input. in this case, input the clock signal to the exclks pin. figure 6-13 shows an example of the exte rnal circuit of the xt1 oscillator. note the 78k0/kb2 is not prov ided with an xt1 oscillator. figure 6-13. example of extern al circuit of xt1 oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz exclks external clock cautions are listed on the next page. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 241 jul 15, 2010 caution 1. when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 6-12 and 6-13 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplit ude circuit for reducing power consumption. figure 6-14 shows examples of incorrect resonator connection. figure 6-14. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 wi th xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 242 jul 15, 2010 figure 6-14. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 wi th xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 243 jul 15, 2010 6.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock note for low power consumption operatio ns, or if not using the subsystem clock as an i/o port, set the xt1 and xt2 pins to i/o mode (oscsels = 0) and connect them as follows. note the 78k0/kb2 is not provi ded with a subsystem clock. input (pm123/pm124 = 1): i ndependently connect to v dd or v ss via a resistor. output (pm123/pm124 = 0): leave open. remark oscsels: bit 4 of clock operati on mode select register (oscctl) pm123, pm124: bits 3 and 4 of port mode register 12 (pm12) 6.4.4 internal hi gh-speed oscillator the internal high-speed oscillator is in corporated in the 78k0/kx2 microcontrolle rs. oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal high-speed oscilla tor automatically starts oscillation (8 mhz (typ.)). 6.4.5 internal low-speed oscillator the internal low-speed oscillator is incor porated in the 78k0/kx2 microcontrollers. the internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer h1. the internal low-speed oscillation clock cannot be used as the cpu clock. ?can be stopped by software? or ?cannot be stopped? can be selected by the option byte. when ?can be stopped by software? is set, oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal low-speed oscillator autom atically starts oscillation, an d the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operat ion is enabled using the option byte. 6.4.6 prescaler the prescaler generates the cpu clock by dividing the main system clock when the main system clock is selected as the clock to be supplied to the cpu. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 244 jul 15, 2010 6.5 clock generator operation the clock generator generates the follo wing clocks and controls the operation modes of the cpu, such as standby mode (see figure 6-1 and 6-2 ). ? main system clock f xp ? high-speed system clock f xh x1 clock f x external main system clock f exclk ? internal high-speed oscillation clock f rh ? subsystem clock f sub note ? xt1 clock f xt ? external subsystem clock f exclks ? internal low-speed oscillation clock f rl ? cpu clock f cpu ? peripheral hardware clock f prs note the 78k0/kb2 is not provi ded with a subsystem clock. the cpu starts operation when t he internal high-speed oscillator starts outputting after a reset release in the 78k0/kx2 microcontrollers, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and t herefore does not operate after reset is rel eased. however, the start clock of the cpu is the internal high-speed oscillat ion clock, so the device c an be started by the inter nal high-speed oscillation clock after a reset release. consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or per forming safety processing when there is a malfunction. (2) improvement of performance because the cpu can be start ed without waiting for the x1 clock oscillat ion stabilization time, the total performance can be improved. when the power supply voltage is turned on, the cl ock generator operation is shown in figure 6-15. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 245 jul 15, 2010 figure 6-15. clock generator operation wh en power supply voltage is turned on (when 1.59 v poc mode is set (option byte: pocmode = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) note 5 subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note 4 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. reset processing (11 to 45 s) <3> waiting for voltage stabilization internal reset signal 0 v 1.59 v (typ.) 1.8 v notes 1,2 0.5 v/ms (min.) notes 1,2 power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> note 3 (1.93 to 5.39 ms) <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exc eeds 1.59 v (typ.), the reset is rel eased and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0. 5 v/ms (min.), the cpu star ts operation on the internal high-speed oscillation clock after the reset is released a nd after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 6.6.1 example of controlling high- speed system clock and (1) in 6.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillatio n to stabilize, and then set switching via software (see (3) in 6.6.1 example of controlli ng high-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). notes 1. with standard and (a) grade products, if the voltage ri ses with a slope of less than 0.5 v/ms (min.) from power application until the voltage reaches 1.8 v, input a low leve l to the reset pin from power application until the voltage reaches 1.8 v, or set the 2.7 v/1.59 v poc mode by using the option byte (pocmode = 1) (see figure 6-16 ). when a low level has been input to the reset pin until the voltage reaches 1.8 v, the cpu operates with the same timing as <2> and thereafter in figure 6-15, after the reset has been released by the reset pin. 2. with (a2) grade products, if the voltage rises wit h a slope of less than 0.75 v/ms (min.) from power application until the voltage reaches 2.7 v, input a low level to the r eset pin from power application until the voltage reaches 2.7 v. when a low level has been input to the reset pin until the voltage reaches 2.7 v, the cpu operates with the same timing as <2> and thereafter in figure 6-15, after the reset has been released by the reset pin. 3. the internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 246 jul 15, 2010 notes 4. when releasing a reset (above figure) or releasing st op mode while the cpu is operating on the internal high-speed oscillation clock, confirm the oscillation stab ilization time for the x1 clock using the oscillation stabilization time counter status r egister (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation stabilization time when releasing stop mode using the oscillation stabilization time select register (osts). 5. the 78k0/kb2 is not provi ded with a subsystem clock. caution it is not necessary to wait for the oscillation stabilization time wh en an external clock input from the exclk and exclks pins is used. remark while the microcontroller is operati ng, a clock that is not used as the cpu clock can be stopped via software settings. the internal high-speed oscillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 6.6.1 example of control ling high-speed system clock , (3) in 6.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 6.6.3 example of controlling subsystem clock ). 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 247 jul 15, 2010 figure 6-16. clock generator operation wh en power supply voltage is turned on (when 2.7 v/1.59 v poc mode is set (option byte: pocmode = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) note 2 subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note 1 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. waiting for oscillation accuracy stabilization (86 to 361 s) internal reset signal 0 v 2.7 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (11 to 45 s) <4> <5> <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.7 v (typ.), the reset is released an d the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is perfo rmed, the cpu starts operation on the internal high-speed oscillation clock. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 6.6.1 example of controlling high- speed system clock and (1) in 6.6.3 example of controlling subsystem clock ). <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillatio n to stabilize, and then set switching via software (see (3) in 6.6.1 example of contro lling high-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). notes 1. when releasing a reset (above figure) or releasing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the oscillation stabi lization time for the x1 clock using the oscillation stabilization time counter status r egister (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation stabilization time when releasing stop mode using the oscillation stabilization time select register (osts). 2. the 78k0/kb2 is not provi ded with a subsystem clock. cautions 1. a voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 v (typ.). if the supply voltage ri ses from 1.59 v (typ.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automati cally generated before reset processing. 2. it is not necessary to wait fo r the oscillation stabilization time when an external clock input from the exclk and exclks pins is used. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 248 jul 15, 2010 remark while the microcontroller is operati ng, a clock that is not used as the cpu clock can be stopped via software settings. the internal high-speed oscillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 6.6.1 example of contro lling high-speed system clock , (3) in 6.6.2 example of controlling internal high-speed oscillation clock , and (4) in 6.6.3 example of controlling subsystem clock ). 6.6 controlling clock 6.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected across the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p121 and x2/exclk/p 122 pins can be used as i/o port pins. caution the x1/p121 and x2/exclk/p122 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clock as cpu clock and peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting frequency (oscctl register) using amph, set the gain of the on-chip osci llator according to the frequency to be used. amph note operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. when amph is set to 1, the clock supply to the cpu is stopped for 4.06 to 16.12 s. remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecti ng x1 clock or external clock (oscctl register) when exclk is cleared to 0 and oscsel is set to 1, the mode is switched from port mode to x1 oscillation mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 0 1 x1 oscillation mode crystal/ceramic resonator connection <3> controlling oscillation of x1 clock (moc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 249 jul 15, 2010 <4> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing can be executed with the internal high-speed oscillation clock. cautions 1. do not change the value of exclk and oscsel while the x1 clock is operating. 2. set the x1 clock after the supply voltage has reached the opera ble voltage of the clock to be used (see chapter 30 electrical specifications (standard products) to chapter 33 electrical specificat ions ((a2) grade products: t a = ? 40 to +125 c)). (2) example of setting procedure when using the external main system clock <1> setting frequency (oscctl register) using amph, set the frequency to be used. amph note operating frequency control 0 1 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. the clock su pply to the cpu is stopped for the duration of 160 external clocks after amph is set to 1. remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecting operation mode (oscctl register) when exclk and oscsel are set to 1, the mode is swit ched from port mode to external clock input mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 1 1 external clock input mode i/o port external clock input <3> controlling external main system clock input (moc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. do not change the value of exclk a nd oscsel while the external main system clock is operating. 2. set the x1 clock after the supply voltage has reached the opera ble voltage of the clock to be used (see chapter 30 electrical specifications (standard products) to chapter 33 electrical specificat ions ((a2) grade products: t a = ? 40 to +125 c)). (3) example of setting procedure when using high-speed system clock as cpu clo ck and peripheral hardware clock <1> setting high-speed system clock oscillation note (see 6.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using the ext ernal main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 250 jul 15, 2010 <2> setting the high-speed system clock as the main system clock (mcm register) when xsel and mcm0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) caution if the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> setting the main system clock as the cpu clo ck and selecting the division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be st opped in the foll owing two ways. ? executing the stop instructi on and stopping the x1 oscillation (disabling clock input if the external clock is used) ? setting mstop to 1 and stopping the x1 oscillation (dis abling clock input if the external clock is used) (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for peripheral hardware that cannot be used in stop mode, see chapter 22 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in t he stop mode and x1 oscillation is stopped (the input of the exte rnal clock is disabled). 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 251 jul 15, 2010 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system clo ck is supplied to the cpu, so change the cpu clock to a clock other than the high-speed system clock. ? 78k0/kb2 mcs cpu clock status 0 internal high-speed oscillation clock 1 high-speed system clock ? 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the high-speed system clock (moc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high- speed system clock as per ipheral hardware clock (3) when stopping the internal high-speed oscillation clock 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 252 jul 15, 2010 (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note 1 <1> setting restart of oscillation of the intern al high-speed oscillation clock (rcm register) when rstop is cleared to 0, the internal high-speed oscillation clock starts operating. <2> waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (rcm register) wait until rsts is set to 1 note 2 . notes 1. after a reset release, the internal high-speed oscill ator automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu clock. 2. this wait time is not necessary if high accu racy is not necessary for the cpu clock and peripheral hardware clock. (2) example of setting procedure when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clock as periphe ral hardware clock <1> ? restarting oscillation of the internal high-speed oscillation clock note (see 6.6.2 (1) example of setting procedure when restarting oscillation of the internal high-speed oscillation clock ). ? oscillating the high-speed system clock note (this setting is required when using the high-speed system clock as the peripheral hardware clock. see 6.6.1 (1) example of setting proce dure when oscillat ing the x1 clock and (2) example of setting procedure when using the ext ernal main system clock. ) note the setting of <1> is not necessary when the inte rnal high-speed oscillation clock or high-speed system clock is already operating. <2> selecting the clock s upplied as the main system clock and peri pheral hardware clock (mcm register) set the main system clock and peripheral hardware clock using xsel and mcm0. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) <3> selecting the cpu clock division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 253 jul 15, 2010 (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction to set the stop mode ? setting rstop to 1 and stopping the internal high-speed oscillation clock (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for peripheral hardware that cannot be used in stop mode, see chapter 22 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. to operate the cpu imme diately after the stop mode has been released, set mcm0 to 0, switch the cpu clock to the internal hi gh-speed oscillation clock, and check that rsts is 1. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in the stop mode and internal high-speed oscillation clock is stopped. (b) to stop internal high-speed o scillation clock by setting rstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operatin g on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed osci llation clock is supplied to the cpu, so change the cpu clock to a clock other than the internal high-speed oscillation clock. ? 78k0/kb2 mcs cpu clock status 0 internal high-speed oscillation clock 1 high-speed system clock ? 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the internal high-speed oscillation clock (rcm register) when rstop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operating on the in ternal high-speed oscillation clock. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 254 jul 15, 2010 6.6.3 example of cont rolling subsystem clock the following two types of subsystem clocks note are available. ? xt1 clock: crystal/ceramic resonator is connected across the xt1 and xt2 pins. ? external subsystem clock: external clock is input to the exclks pin. when the subsystem clock is not us ed, the xt1/p123 and xt2/ exclks/p124 pins can be used as i/o port pins. note the 78k0/kb2 is not provi ded with a subsystem clock. cautions 1. the xt1/p123 and xt2/exclks/p124 pins are in the i/o port mode after a reset release. 2. do not start the peripheral hardware operation with the external clock from peripheral hardware pins when the internal high-s peed oscillation clo ck and high-speed syst em clock are stopped while the cpu operates with the subsystem clock, or when in the stop mode. the following describes examples of setti ng procedures for the following cases. (1) when oscillating xt1 clock (2) when using external subsystem clock (3) when using subsystem clock as cpu clock (4) when stopping subsystem clock (1) example of setting procedur e when oscillating the xt1 clock <1> setting xt1 and xt2 pins and selectin g operation mode (pcc and oscctl registers) when xtstart, exclks, and oscsels are set as any of the following, the mode is switched from port mode to xt1 oscillation mode. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 0 1 1 xt1 oscillation mode crystal/ceramic resonator connection remark : don?t care <2> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution do not change the value of xtstart, exclks, and oscsels while the subsystem clock is operating. (2) example of setting procedure when using the external subsystem clock <1> setting xt1 and xt2 pins, selecting xt1 clock/exte rnal clock and controlling oscillation (pcc and oscctl registers) when xtstart is cleared to 0 and exclks and oscsels are set to 1, the mode is switched from port mode to external clock input mode. in this case, input the external clock to the exclks/xt2/p124 pins. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 1 1 external clock input mode i/o port external clock input caution do not change the value of xtstart, exclks, and oscsels while the subsystem clock is operating. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 255 jul 15, 2010 (3) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 6.6.3 (1) example of setting proce dure when oscillating the xt1 clock and (2) example of setting procedure when using the external subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> switching the cpu clock (pcc register) when css is set to 1, the subsystem clock is supplied to the cpu. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 f sub /2 1 other than above setting prohibited (4) example of setting procedure wh en stopping the subsystem clock <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to the cpu, so change the cpu clock to a clock other than the subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (oscctl register) when oscsels is cleared to 0, xt1 oscillation is stop ped (the input of the external clock is disabled). cautions 1. be sure to confirm th at cls = 0 when clearing oscsels to 0. in addition, stop the watch timer if it is operating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 256 jul 15, 2010 6.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. only the following peripheral hardware can operate with this clock. ? watchdog timer ? 8-bit timer h1 (if f rl is selected as the count clock) in addition, the following operation modes can be selected by the option byte. ? internal low-speed oscillator cannot be stopped ? internal low-speed oscillator can be stopped by software the internal low-speed oscillat or automatically starts oscillation after a re set release, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operat ion has been enabled by the option byte. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock <1> setting lsrstop to 1 (rcm register) when lsrstop is set to 1, the internal low-speed oscillation clock is stopped. (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock <1> clearing lsrstop to 0 (rcm register) when lsrstop is cleared to 0, the internal low-speed oscillation clock is restarted. caution if ?internal low-speed oscilla tor cannot be stopped? is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 257 jul 15, 2010 6.6.5 clocks supplied to cp u and peripheral hardware the following table shows the relation among the clocks s upplied to the cpu and peripheral hardware, and setting of registers. table 6-4. clocks supplied to cpu and periphe ral hardware, and regist er setting (78k0/kb2) supplied clock clock supplied to cpu clock su pplied to peripheral hardware xsel mcm0 exclk internal high-speed oscillation clock 0 x1 clock 1 0 0 internal high-speed oscillation clock external main system clock 1 0 1 x1 clock 1 1 0 external main system clock 1 1 1 remarks 1. the 78k0/kb2 is not prov ided with a subsystem clock. 2. xsel: bit 2 of the main clock mode register (mcm) mcm0: bit 0 of mcm exclk: bit 7 of the clock operat ion mode select register (oscctl) : don?t care table 6-5. clocks supplied to cpu and peripheral hardware, and register setting (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) supplied clock clock supplied to cpu clock su pplied to peripheral hardware xsel css mcm0 exclk internal high-speed oscillation clock 0 0 x1 clock 1 0 0 0 internal high-speed oscillation clock external main system clock 1 0 0 1 x1 clock 1 0 1 0 external main system clock 1 0 1 1 internal high-speed oscillation clock 0 1 1 1 0 0 x1 clock 1 1 1 0 1 1 0 1 subsystem clock external main system clock 1 1 1 1 remark xsel: bit 2 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) mcm0: bit 0 of mcm exclk: bit 7 of the clock operati on mode select register (oscctl) : don?t care 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 258 jul 15, 2010 6.6.6 cpu clock stat us transition diagram figure 6-17 and 6-18 shows the cpu clock stat us transition diagram of this product. figure 6-17. cpu clock stat us transition diagram (when 1.59 v poc mode is set (opt ion byte: pocmode = 0), 78k0/kb2) power on reset release v dd 1.8 v (min.) note cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt (b) (a) (c) (e) (d) (f) (g) internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) v dd < 1.59 v (typ.) v dd 1.59 v (typ.) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating cpu: internal high- speed oscillation stop cpu: internal high- speed oscillation halt note standard and (a) grade products: 1.8 v, (a2) grade products: 2.7 v remark in the 2.7 v/1.59 v poc mode (opt ion byte: pocmode = 1), the cpu cl ock status changes to (a) in the above figure when the supply voltage exceeds 2.7 v (t yp.), and to (b) after reset processing (11 to 45 s). 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 259 jul 15, 2010 figure 6-18. cpu clock stat us transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0), 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) power on reset release internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: selectable by cpu cpu: internal high- speed oscillation stop internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation/exclks input: operable cpu: internal high- speed oscillation halt internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation/exclks input: selectable by cpu internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation/exclks input: operable internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating xt1 oscillation/exclks input: operable cpu: operating with xt1 oscillation or exclks input cpu: xt1 oscillation/exclks input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: operating internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operating (b) (a) (c) (d) (e) (f) (g) (h) (i) v dd 1.59 v (typ.) v dd 1.8 v (min.) note v dd < 1.59 v (typ.) note standard and (a) grade products: 1.8 v, (a2) grade products: 2.7 v remark in the 2.7 v/1.59 v poc mode (opt ion byte: pocmode = 1), the cpu cl ock status changes to (a) in the above figure when the supply voltage exceeds 2.7 v (t yp.), and to (b) after reset processing (11 to 45 s). 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 260 jul 15, 2010 table 6-6 shows transition of the cpu clock and examples of setting the sfr registers. table 6-6. cpu clock transition a nd sfr register setting examples (1/5) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition amph exclk oscsel mstop ostc register xsel mcm0 (a) (b) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 1 mhz f xh 10 mhz) 0 1 1 0 must not be checked 1 1 (a) (b) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 caution set the x1 clock after the supply vo ltage has reached the operable voltag e of the clock to be used (see chapter 30 electrical specifications (st andard products) to chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c)). (3) cpu operating with subsystem cl ock (d) after reset release (a) note (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) note the 78k0/kb2 is not prov ided with a subsystem clock. (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (a) (b) (d) (xt1 clock) 1 necessary 1 (a) (b) (d) (external subsystem clock) 0 1 1 unnecessary 1 remarks 1. (a) to (i) in table 6-6 correspond to (a) to (i) in figure 6-17 and 6-18. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 261 jul 15, 2010 table 6-6. cpu clock transition a nd sfr register setting examples (2/5) (4) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition amph note exclk oscsel mstop ostc register xsel note mcm0 (b) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 (b) (c) (external main clock: 1 mhz f xh 10 mhz) 0 1 1 0 must not be checked 1 1 (b) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 (b) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock note the value of this flag can be changed only once after a reset release. this setting is not necessary if it has already been set. caution set the x1 clock after the supply vo ltage has reached the operable voltag e of the clock to be used (see chapter 30 electrical specifications (st andard products) to chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c)). (5) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) note note the 78k0/kb2 is not prov ided with a subsystem clock. (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (b) (d) (xt1 clock) 1 necessary 1 (b) (d) (external subsystem cl ock) 0 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock remarks 1. (a) to (i) in table 6-6 correspond to (a) to (i) in figure 6-17 and 6-18. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 262 jul 15, 2010 table 6-6. cpu clock transition a nd sfr register setting examples (3/5) (6) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 (c) (b) 0 confirm this flag is 1. 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) note note the 78k0/kb2 is not prov ided with a subsystem clock. (setting sequence of sfr registers) setting flag of sfr register status transition xtstart exclks oscsels waiting for oscillation stabilization css 0 0 1 (c) (d) (xt1 clock) 1 necessary 1 (c) (d) (external subsystem clock) 0 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock (8) cpu clock changing from subsystem clock (d ) to internal high-speed oscillation clock (b) note the 78k0/kb2 is not prov ided with a subsystem clock. (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 css (d) (b) 0 confirm this flag is 1. 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if xsel is 0 remarks 1. (a) to (i) in table 6-6 correspond to (a) to (i) in figure 6-17 and 6-18. 2. mcm0: bit 0 of the main clock mode register (mcm) exclks, oscsels: bits 5 and 4 of the clo ck operation mode select register (oscctl) rsts, rstop: bits 7 and 0 of the internal oscillation mode register (rcm) xtstart, css: bits 6 and 4 of the processor clock control register (pcc) : don?t care 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 263 jul 15, 2010 table 6-6. cpu clock transition a nd sfr register setting examples (4/5) (9) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) note note the 78k0/kb2 is not prov ided with a subsystem clock. (setting sequence of sfr registers) setting flag of sfr register status transition amph note exclk oscsel mstop ostc register xsel note mcm0 css (d) (c) (x1 clock: 1 mhz f xh 10 mhz) 0 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: 1 mhz f xh 10 mhz 0 1 1 0 must not be checked 1 1 0 (d) (c) (x1 clock: 10 mhz < f xh 20 mhz) 1 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: 10 mhz < f xh 20 mhz) 1 1 1 0 must not be checked 1 1 0 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock unnecessary if this register is already set note the value of this flag can be changed only once after a reset release. this setting is not necessary if it has already been set. caution set the x1 clock after the supply vo ltage has reached the operable voltag e of the clock to be used (see chapter 30 electrical specifications (st andard products) to chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c)). (10) ? halt mode (e) set while cpu is operating wit h internal high-speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) note status transition setting (b) (e) (c) (f) (d) (g) note executing halt instruction note the 78k0/kb2 is not prov ided with a subsystem clock. remarks 1. (a) to (i) in table 6-6 correspond to (a) to (i) in figure 6-17 and 6-18. 2. exclk, oscsel, amph: bits 7, 6, and 0 of the clock operation mode sele ct register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 264 jul 15, 2010 table 6-6. cpu clock transition a nd sfr register setting examples (5/5) (11) ? stop mode (h) set while cp u is operating with internal hi gh-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (h) (c) (i) stopping peripheral functions that cannot operate in stop mode executing stop instruction remarks 1. (a) to (i) in table 6-6 correspond to (a) to (i) in figure 6-17 and 6-18. 2. exclk, oscsel, amph: bits 7, 6 and 0 of the clock operation mode sele ct register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 265 jul 15, 2010 6.6.7 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 6-7. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? internal high-speed oscillator can be stopped (rstop = 1). ? clock supply to cpu is stopped for 4.06 to 16.12 s after amph has been set to 1. internal high- speed oscillation clock external main system clock enabling input of ex ternal clock from exclk pin ? mstop = 0, oscsel = 1, exclk = 1 ? internal high-speed oscillator can be stopped (rstop = 1). ? clock supply to cpu is stopped for the duration of 160 external clocks from the exclk pin after amph has been set to 1. x1 clock x1 oscillation can be stopped (mstop = 1). kb2, kc2, kd2, ke2, kf2 external main system clock internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock xt1 clock stabilization of xt1 oscillation ? xtstart = 0, exclks = 0, oscsels = 1, or xtstart = 1 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock external subsystem clock enabling input of ex ternal clock from exclks pin ? xtstart = 0, exclks = 1, oscsels = 1 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? rstop = 0, mcs = 0 xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). x1 clock stabilization of x1 oscillation and selection of high-speed system clock as main system clock ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? mcs = 1 ? xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). ? clock supply to cpu is stopped for 4.06 to 16.12 s after amph has been set to 1. kc2, kd2, ke2, kf2 (other than kb2) xt1 clock, external subsystem clock external main system clock enabling input of ex ternal clock from exclk pin and selection of high-speed system clock as main system clock ? mstop = 0, oscsel = 1, exclk = 1 ? mcs = 1 ? xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). ? clock supply to cpu is stopped for the duration of 160 external clocks from the exclk pin after amph has been set to 1. remark the 78k0/kb2 is not provi ded with a subsystem clock. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 266 jul 15, 2010 6.6.8 time required for switchover of cpu clock and main system clock by setting bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of t he processor clock control register (pcc), the cpu clock can be switched (between the main system cloc k and the subsystem clock) and the divisi on ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewrit ing to pcc; operatio n continues on the pre- switchover clock for several clocks (see table 6-8 and 6-9 ). whether the cpu is operat ing on the main system clo ck or the subsystem clock note can be ascertained using bit 5 (cls) of the pcc register. note the 78k0/kb2 is not prov ided with a subsystem clock. table 6-8. time required for switchover of cpu clock and main system clock cycle division factor (78k0/kb2) set value before switchover set value after switchover pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 cloc k 1 clock 1 clock remark the number of clocks listed in table 6-8 is the number of cpu clocks before switchover. table 6-9. time required for switchover of cpu clock and main system clock cycle division factor (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css p cc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 2f xp /f sub clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /f sub clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /2f sub clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /4f sub clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock f xp /8f sub clocks 1 2 clocks 2 clocks 2 clo cks 2 clocks 2 clocks caution selection of the main system clock cycle division factor (pcc0 to pcc2) and switchover from the main system clock to the sub system clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the main syst em clock cycle division factor (pcc0 to pcc2) and switchover from the subsystem clock to the ma in system clock (changing css from 1 to 0). remark 1. the number of clocks listed in table 6-9 is the number of cpu clocks before switchover. 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 267 jul 15, 2010 remark 2. when switching the cpu clock from the main system clock to the sub system clock, calculate the number of clocks by rounding up to the next clock and di scarding the decimal portion, as shown below. example when switching cpu clock from f xp /2 to f sub /2 (@ oscillation with f xp = 10 mhz, f sub = 32.768 khz) f xp /f sub = 10000/32.768 ? 305.1 306 clocks by setting bit 0 (mcm0) of the main clock mode register (mcm), the main system clock can be switched (between the internal high-speed osci llation clock and the hi gh-speed system clock). the actual switchover operation is no t performed immediately after rewriting to mcm0; operation continues on the pre- switchover clock for several clocks (see table 6-10 ). whether the cpu is operating on the internal high-speed oscillation clo ck or the high-speed system clock can be ascertained using bit 1 (mcs) of mcm. table 6-10. maximum time required for main system clock switchover set value before switchover set value after switchover mcm0 mcm0 0 1 0 1 + 2f rh /f xh clock 1 1 + 2f xh /f rh clock cautions 1. when switching the in ternal high-speed oscillation clock to the high-speed sys tem clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be ch anged only once after a reset release. 2. do not rewrite mcm0 when the cp u clock operates with th e subsystem clock. remarks 1. the number of clocks listed in table 6-10 is t he number of main system clocks before switchover. 2. calculate the number of clocks in tabl e 6-10 by removing the decimal portion. example when switching the main system clock from t he internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f rh = 8 mhz, f xh = 10 mhz) 1 + 2f rh /f xh = 1 + 2 8/10 = 1 + 2 0.8 = 1 + 1.6 = 2.6 2 clocks 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 268 jul 15, 2010 6.6.9 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 6-11. conditions before the clock osc illation is stopped and flag settings (78k0/kb2) clock note conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 (the cpu is operating on the high-speed system clock) rstop = 1 x1 clock external main system clock mcs = 0 (the cpu is operating on the internal high-speed oscillation clock) mstop = 1 note the 78k0/kb2 is not prov ided with a subsystem clock. table 6-12. conditions before the clock oscillation is stopped and flag settings (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 or cls = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) rstop = 1 x1 clock external main system clock mcs = 0 or cls = 1 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 xt1 clock external subsystem clock cls = 0 (the cpu is operating on a clock other than the subsystem clock) oscsels = 0 78k0/kx2 chapter 6 clock generator r01uh0008ej0401 rev.4.01 269 jul 15, 2010 6.6.10 peripheral hardware and source clocks the following lists peripheral hardware and source clocks incorporated in t he 78k0/kx2 microcontrollers. remark the peripheral hardware depends on the product. see 1.7 block diagram and 1.8 outline of functions . table 6-13. peripheral ha rdware and source clocks source clock peripheral hardware peripheral hardware clock (f prs ) subsystem clock (f sub ) note 1 internal low- speed oscillation clock (f rl ) tm50 output external clock from peripheral hardware pins 00 y n n n y (ti000 pin) note 2 16-bit timer/ event counter 01 y n n n y (ti001 pin) note 2 50 y n n n y (ti50 pin) note 2 8-bit timer/ event counter 51 y n n n y (ti51 pin) note 2 h0 y n n y n 8-bit timer h1 y n y n n watch timer y y n n n watchdog timer n n y n n buzzer output y n n n n clock output y y n n n a/d converter y n n n n uart0 y n n y n uart6 y n n y n csi10 y n n n y (sck10 pin) note 2 csi11 y n n n y (sck11 pin) note 2 csia0 y n n n y (scka0 pin) note 2 serial interface iic0 y n n n y (exscl0, scl0 pin) note 2 notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. do not start the peripheral hardware operation with the external clock from peripheral hardware pins when the internal high-speed oscillation clock and high-speed system clock are stopped while the cpu operates with the subsystem clock, or when in the stop mode. remark y: can be selected, n: cannot be selected 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 270 jul 15, 2010 chapter 7 16-bit timer/even t counters 00 and 01 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 16-bit timer/event counters 00 16-bit timer/event counters 00 ? remark : mounted, ? : not mounted 7.1 functions of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 have the following functions. (1) interval timer 16-bit timer/event counters 00 and 01 generate an in terrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer event counters 00 and 01 can output a one-sh ot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counters 00 and 01 c an output a rectangular wave whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counters 00 and 01 can measure th e pulse width of an externally input signal. 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 271 jul 15, 2010 7.2 configuration of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. table 7-1. configuration of 16- bit timer/event counters 00 and 01 item configuration time/counter 16-bit timer counter 0n (tm0n) register 16-bit timer capture/compare registers 00n, 01n (cr00n, cr01n) timer input ti00n, ti01n pins timer output to0n pin, output controller control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0 (pm0) port register 0 (p0) remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products figures 7-1 and 7-2 show the block diagrams. figure 7-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 to cr010 to00/ti010/ p01 to00 output output latch (p01) pm01 f prs f prs /2 2 f prs /2 8 f prs (cautions 1 to 3 are listed on the next page.) 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 272 jul 15, 2010 figure 7-2. block diagram of 16-bit timer/event counter 01 internal bus capture/compare control register 01 (crc01) ti011/to01/p06 ti001/p05/ ssi11 prescaler mode register 01 (prm01) 2 prm011 prm010 crc012 16-bit timer capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) clear noise elimi- nator crc012 crc011 crc010 inttm001 to01/ti011/ p06 inttm011 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 toc014 lvs01 lvr01 toc011 toe01 selector 16-bit timer capture/compare register 001 (cr001) selector selector selector noise elimi- nator noise elimi- nator output controller ospe01 ospt01 output latch (p06) pm06 to cr011 to01 output f prs f prs /2 4 f prs /2 6 f prs cautions 1. the valid edge of ti010 and timer output (to00) cannot be used for th e p01 pin at the same time, and the valid edge of ti011 and timer output (to01) cannot be u sed for the p06 pin at the same time. select either of the functions. 2. if clearing of bits 3 and 2 (tmc0n3 and tm c0n2) of 16-bit timer mode control register 0n (tmc0n) to 00 and input of the capture trigger c onflict, then the capture d data is undefined. 3. to change the mode from the capture mode to the comparis on mode, first clear the tmc0n3 and tmc0n2 bits to 00, and then change the setting. a value that has been once cap tured remains stored in cr00n unl ess the device is reset. if the mode has been changed to the comparison mode, be sure to set a comparison value. (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 273 jul 15, 2010 figure 7-3. format of 16-bit timer counter 0n (tm0n) tm0n (n = 0, 1) ff11h (tm00), ffb1h (tm01) ff10h (tm00), ffb0h (tm01) address: ff10h, ff11h (tm00), ffb0h, ffb1h (tm01) after reset: 0000h r 1514131211109876543210 the count value of tm0n can be read by reading tm0n when the value of bits 3 and 2 (tmc0n3 and tmc0n2) of 16- bit timer mode control register 0n (tmc0n) is other than 00. the value of tm 0n is 0000h if it is read when tmc0n3 and tmc0n2 = 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if tmc0n3 and tmc0n2 are cleared to 00 ? if the valid edge of the ti00n pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti00n pin ? if tm0n and cr00n match in the mode in which the clear & start occurs when tm0n and cr00n match ? ospt0n is set to 1 in one-shot pulse output m ode or the valid edge is input to the ti00n pin caution even if tm0n is read, th e value is not captured by cr01n. (2) 16-bit timer capture/compare regi ster 00n (cr00n), 16-bit timer captu re/compare register 01n (cr01n) cr00n and cr01n are 16-bit registers that are used with a capture function or comparison function selected by using crc0n. change the value of cr00n while the timer is stopped (tmc0n3 and tmc0n2 = 00). the value of cr01n can be changed during oper ation if the value has been set in a specific way. for details, see 7.5.1 rewriting cr01n during tm0n operation . these registers can be read or written in 16-bit units. reset signal generation clears these registers to 0000h. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 274 jul 15, 2010 figure 7-4. format of 16-bit timer ca pture/compare register 00n (cr00n) cr00n (n = 0, 1) ff13h (cr000), ffb3h (cr001) ff12h (cr000), ffb2h (cr001) address: ff12h, ff13h (cr000), ffb2h, ffb3h (cr001) after reset: 0000h r/w 1514131211109876543210 (i) when cr00n is used as a compare register the value set in cr00n is constant ly compared with the tm0n count val ue, and an interrupt request signal (inttm00n) is generated if they match. t he value is held until cr00n is rewritten. caution cr00n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr00n is used as a capture register the count value of tm0n is captured to cr00n when a capture trigger is input. as the capture trigger, an edge of a phas e reverse to that of the ti00n pin or the valid edge of the ti01n pin can be selected by using crc0n or prm0n. figure 7-5. format of 16-bit timer ca pture/compare register 01n (cr01n) cr01n (n = 0, 1) ff15h (cr010), ffb5h (cr011) ff14h (cr010), ffb4h (cr011) address: ff14h, ff15h (cr010), ffb4h, ffb5h (cr011) after reset: 0000h r/w 1514131211109876543210 (i) when cr01n is used as a compare register the value set in cr01n is constant ly compared with the tm0n count val ue, and an interrupt request signal (inttm01n) is generated if they match. caution cr01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr01n is used as a capture register the count value of tm0n is captured to cr01n when a capture trigger is input. it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti 00n pin valid edge is set by prm0n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 275 jul 15, 2010 (iii) setting range when cr00n or cr 01n is used as a compare register when cr00n or cr01n is used as a compare register, set it as shown below. operation cr00n register setting range cr01n register setting range operation as interval timer operation as square-wave output operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm01n). operation in the clear & start mode entered by ti00n pin valid edge input operation as free-running timer 0000h note n ffffh 0000h note m ffffh operation as ppg output m < n ffffh 0000h note m < n operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows. a match interrupt occurs at the timing when the timer counter (tm0n register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti00n pin va lid edge (when clear & start mode is entered by ti00n pin valid edge input) ? when the timer counter is cleared due to compare match (when clear & start mode is entered by match between tm0n and cr00n (cr00n = other than 0000h, cr01n = 0000h)) operation enabled (other than 00) tm0n register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit (tmc0n3, tmc0n2) interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr00n register set value, m: cr01n register set value 2. for details of tmc0n3 and tmc0n2, see 7.3 (1) 16-bit timer mode c ontrol register 0n (tmc0n) . 3. n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 276 jul 15, 2010 table 7-2. capture oper ation of cr00n and cr01n external input signal capture operation ti00n pin input ti01n pin input set values of es0n1 and es0n0 position of edge to be captured set values of es1n1 and es1n0 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc0n1 = 1 ti00n pin input (reverse phase) 11: both edges (cannot be captured) crc0n1 bit = 0 ti01n pin input 11: both edges capture operation of cr00n interrupt signal inttm00n signal is not generated even if value is captured. interrupt signal inttm00n signal is generated each time value is captured. set values of es0n1 and es0n0 position of edge to be captured 01: rising 00: falling ti00n pin input note 11: both edges capture operation of cr01n interrupt signal inttm01n signal is generated each time value is captured. note the capture operation of cr01n is not affected by the setting of the crc0n1 bit. caution to capture the count value of the tm0n register to the cr00n register by using the phase reverse to that input to the ti00n pin, the interrupt request signal (inttm00n) is not generated after the value has been captured. if the valid edge is detected on the ti01n pin during this operation, the capture operation is not performed but the inttm00n signal is gene rated as an external interrupt signal. to not use the external interrupt, mask the inttm00n signal. remarks 1. crc0n1: see 7.3 (2) capture/compare control register 0n (crc0n) . es1n1, es1n0, es0n1, es0n0: see 7.3 (4) prescaler mode register 0n (prm0n) . 2. n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 277 jul 15, 2010 7.3 registers controlling 16-bi t timer/event counters 00 and 01 registers used to control 16-bit timer/ event counters 00 and 01 are shown below. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? port mode register 0 (pm0) ? port register 0 (p0) (1) 16-bit timer mode cont rol register 0n (tmc0n) tmc0n is an 8-bit register that sets the 16-bit timer/ event counter 0n operation mode, tm0n clear mode, and output timing, and detects an overflow. rewriting tmc0n is prohibited during operation (when tm c0n3 and tmc0n2 = other than 00). however, it can be changed when tmc0n3 and tmc0n2 are cleared to 00 (sto pping operation) and when ovf0n is cleared to 0. tmc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears tmc0n to 00h. caution 16-bit timer/event counter 0n starts operation at the moment tm c0n2 and tmc0n3 are set to values other than 00 (operation stop mo de), respectively. set tmc0n2 and tmc0n3 to 00 to stop the operation. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 278 jul 15, 2010 figure 7-6. format of 16-bit timer mode control register 00 (tmc00) address: ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 operation enable of 16-bit timer/event counter 00 0 0 disables 16-bit timer/event counter 00 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 00 (tm00). 0 1 free-running timer mode 1 0 clear & start mode entered by ti000 pin valid edge input note 1 1 clear & start mode entered upon a match between tm00 and cr000 tmc001 condition to reverse timer output (to00) 0 ? match between tm00 and cr000 or match between tm00 and cr010 1 ? match between tm00 and cr000 or match between tm00 and cr010 ? trigger input of ti000 pin valid edge ovf00 tm00 overflow flag clear (0) clears ovf00 to 0 or tmc003 and tmc002 = 00 set (1) overflow occurs. ovf00 is set to 1 when the value of tm00 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti000 pin valid edge input, and clear & start mode entered upon a match between tm00 and cr000). it can also be set to 1 by writing 1 to ovf00. note the ti000 pin valid edge is set by bits 5 and 4 ( es001, es000) of prescaler mode register 00 (prm00). 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 279 jul 15, 2010 figure 7-7. format of 16-bit timer mode control register 01 (tmc01) address: ffb6h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc01 0 0 0 0 tmc013 tmc012 tmc011 ovf01 tmc013 tmc012 operation enable of 16-bit timer/event counter 01 0 0 disables 16-bit timer/event counter 01 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 01 (tm01). 0 1 free-running timer mode 1 0 clear & start mode entered by ti001 pin valid edge input note 1 1 clear & start mode entered upon a match between tm01 and cr001 tmc011 condition to reverse timer output (to01) 0 ? match between tm01 and cr001 or match between tm01 and cr011 1 ? match between tm01 and cr001 or match between tm01 and cr011 ? trigger input of ti001 pin valid edge ovf01 tm01 overflow flag clear (0) clears ovf01 to 0 or tmc013 and tmc012 = 00 set (1) overflow occurs. ovf01 is set to 1 when the value of tm01 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti001 pin valid edge input, and clear & start mode entered upon a match between tm01 and cr001). it can also be set to 1 by writing 1 to ovf01. note the ti001 pin valid edge is set by bits 5 and 4 ( es011, es010) of prescaler mode register 01 (prm01). 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 280 jul 15, 2010 (2) capture/compare control register 0n (crc0n) crc0n is the register that controls the operation of cr00n and cr01n. changing the value of crc0n is prohibited during oper ation (when tmc0n3 and tmc0n2 = other than 00). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears crc0n to 00h. figure 7-8. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 pin 1 captures on valid edge of ti000 pin by reverse phase note the valid edge of the ti010 and ti000 pin is set by prm00. if es001 and es000 are set to 11 (both edges) when crc001 is 1, the valid edge of the ti000 pin cannot be detected. crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register if tmc003 and tmc002 are set to 11 (clear & start mode entered upon a match between tm00 and cr000), be sure to set crc000 to 0. note when the valid edge is detected from the ti010 pin, the captur e operation is not performed but the inttm000 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perfo rmed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 281 jul 15, 2010 figure 7-9. example of cr01n capture op eration (when rising edge is specified) count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n valid edge figure 7-10. format of capture/comp are control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 pin 1 captures on valid edge of ti001 pin by reverse phase note the valid edge of the ti011 and ti001 pin is set by prm01. if es011 and es010 are set to 11 (both edges) when crc011 is 1, the valid edge of the ti001 pin cannot be detected. crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register if tmc013 and tmc012 are set to 11 (clear & start mode entered upon a match between tm01 and cr001), be sure to set crc010 to 0. note when the valid edge is detected from the ti011 pin, the captur e operation is not performed but the inttm001 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perfo rmed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode regist er 01 (prm01) (see figure 7-9 example of cr01n capture operation (when rising edge is specified)). remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 282 jul 15, 2010 (3) 16-bit timer output control register 0n (toc0n) toc0n is an 8-bit register t hat controls the to0n output. toc0n can be rewritten while only o spt0n is operating (when tmc0n3 and tmc0n2 = other than 00). rewriting the other bits is prohibited during operation. however, toc0n4 can be rewritten during timer operation as a means to rewrite cr01n (see 7.5.1 rewriting cr01n during tm0n operation ). toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears toc0n to 00h. caution be sure to set toc0n using the following procedure. <1> set toc0n4 and toc0n1 to 1. <2> set only toe0n to 1. <3> set either of lvs0n or lvr0n to 1. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 283 jul 15, 2010 figure 7-11. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. do not set this bit to 1 in a mode other than the one- shot pulse output mode. if it is set to 1, tm00 is cleared and started. ospe00 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti000 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm00 and cr000. toc004 to00 output control on match between cr010 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when toc004 = 0. lvs00 lvr00 setting of to00 output status 0 0 no change 0 1 initial value of to00 output is low level (to00 output is cleared to 0). 1 0 initial value of to00 output is high level (to00 output is set to 1). 1 1 setting prohibited ? lvs00 and lvr00 can be used to set the initial value of the to00 output level. if the initial value does not have to be set, leave lvs00 and lvr00 as 00. ? be sure to set lvs00 and lvr00 when toe00 = 1. lvs00, lvr00, and toe00 being simultaneously set to 1 is prohibited. ? lvs00 and lvr00 are trigger bits. by setting these bits to 1, the initial value of the to00 output level can be set. even if these bits are cleared to 0, to00 output is not affected. ? the values of lvs00 and lvr00 are always 0 when they are read. ? for how to set lvs00 and lvr00, see 7.5.2 setting lvs0n and lvr0n . ? the actual to00/ti010/p01 pin output is determined depending on pm01 and p01, besides to00 output. toc001 to00 output control on match between cr000 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm000) is generated even when toc001 = 0. toe00 to00 output control 0 disables output (to00 output fixed to low level) 1 enables output 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 284 jul 15, 2010 figure 7-12. format of 16-bit timer ou tput control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always 0 w hen it is read. do not set this bit to 1 in a mode other than the one-shot pulse output mode. if it is set to 1, tm01 is cleared and started. ospe01 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti001 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm01 and cr001. toc014 to01 output control on match between cr011 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm011) is generated even when toc014 = 0. lvs01 lvr01 setting of to01 output status 0 0 no change 0 1 initial value of to01 output is low level (to01 output is cleared to 0). 1 0 initial value of to01 output is high level (to01 output is set to 1). 1 1 setting prohibited ? lvs01 and lvr01 can be used to set the initial value of the to01 output level. if the initial value does not have to be set, leave lvs01 and lvr01 as 00. ? be sure to set lvs01 and lvr01 when toe01 = 1. lvs01, lvr01, and toe01 being simultaneously set to 1 is prohibited. ? lvs01 and lvr01 are trigger bits. by setting these bits to 1, the initial value of the to01 output level can be set. even if these bits are cleared to 0, to01 output is not affected. ? the values of lvs01 and lvr01 are always 0 when they are read. ? for how to set lvs01 and lvr01, see 7.5.2 setting lvs0n and lvr0n . ? the actual to01/ti011/p06 pin output is determined depending on pm06 and p06, besides to01 output. toc011 to01 output control on match between cr001 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm001) is generated even when toc011 = 0. toe01 to01 output control 0 disables output (to01 output is fixed to low level) 1 enables output 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 285 jul 15, 2010 (4) prescaler mode register 0n (prm0n) prm0n is the register that se ts the tm0n count clock and ti00n and ti01n pin input valid edges. rewriting prm0n is prohibited during operati on (when tmc0n3 and tmc0n2 = other than 00). prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears prm0n to 00h. cautions 1. do not apply the following setting when se tting the prm0n1 and prm0n0 bits to 11 (to specify the valid edge of the ti00n pin as a count clock). ? clear & start mode entered by the ti00n pin valid edge ? setting the ti00n pin as a capture trigger 2. if the operation of the 16-bit timer/event counter 0n is enabled wh en the ti00n or ti01n pin is at high level and when the valid edge of the ti00n or ti01n pin is speci fied to be the rising edge or both edges, the high level of the ti00n or ti01n pin is det ected as a rising edge. note this when the ti00n or ti01n pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. the valid edge of ti010 and timer output (to00) cannot be used for the p01 pin at the same time, and the valid edge of ti011 and timer output (to01) cannot be u sed for the p06 pin at the same time. select either of the functions. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 286 jul 15, 2010 figure 7-13. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection note 1 prm001 prm000 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs note 2 2 mhz 5 mhz 10 mhz 20 mhz note 3 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.12 khz 1 1 ti000 valid edge notes 4, 5 notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of prm001 = prm000 = 0 (count clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. 4. the external clock from the ti000 pin requires a pulse longer than twice the cycle of the peripheral hardware clock (f prs ). 5. do not start timer operation with the external cl ock from the ti000 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 287 jul 15, 2010 figure 7-14. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection note 1 prm011 prm010 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs note 2 2 mhz 5 mhz 10 mhz 20 mhz note 3 0 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 f prs /2 6 31.25 khz 78.125 khz 156.25 khz 312.5 khz 1 1 ti001 valid edge notes 4, 5 notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of prm011 = prm010 = 0 (count clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. 4. the external clock from the ti001 pin requires a pulse longer than twice the cycle of the peripheral hardware clock (f prs ). 5. do not start timer operation with the external cl ock from the ti001 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 288 jul 15, 2010 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 and p 06/to01/ti011 pins for timer outpu t, set pm01 and pm06 and the output latches of p01 and p06 to 0. when using the p00/ti000, p 01/to00/ti010, p05/ti 001/ssi11, and p06/to01/ ti011 pins for timer input, set pm00, pm01, pm05, and pm06 to 1. at this time, the outpu t latches of p00, p01, p05, and p06 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm0 to ffh. figure 7-15. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) remark the figure shown above presents the format of port mode register 0 of 78k0/kf2 products. for the format of port mode register 0 of other products, see (1) port mode registers (pmxx) in 5.3 registers controlling port function . 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 289 jul 15, 2010 7.4 operation of 16-bit ti mer/event counters 00 and 01 7.4.1 interval timer operation if bits 3 and 2 (tmc0n3 and tmc0n2) of the 16-bit timer mode c ontrol register (tmc0n) are set to 11 (clear & start mode entered upon a match between tm0n and cr00n), the count operation is start ed in synchronization with the count clock. when the value of tm0n later matches the value of cr00n , tm0n is cleared to 0000h and a match interrupt signal (inttm00n) is generated. this inttm00n signal ena bles tm0n to operate as an interval timer. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 20 interrupt functions . figure 7-16. block diagram of interval timer operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm00n signal figure 7-17. basic timing exampl e of interval timer operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 290 jul 15, 2010 figure 7-18. example of register se ttings for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used for the interval timer functi on. however, a compare ma tch interrupt (inttm01n) is generated when the set value of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 291 jul 15, 2010 figure 7-19. example of software pr ocessing for interval timer function tm0n register 0000h operable bits (tmc0n3, tmc0n2) cr00n register inttm00n signal n 11 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, cr00n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 292 jul 15, 2010 7.4.2 square-wave output operation when 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1 ), a square wave can be output from the to0n pin by setting the 16-bit timer output control register 0n (toc0n) to 03h. when tmc0n3 and tmc0n2 are set to 11 (count clear & st art mode entered upon a match between tm0n and cr00n), the counting operation is started in synchronization with the count clock. when the value of tm0n later matches the value of cr00n, tm 0n is cleared to 0000h, an interrupt signal (inttm00n) is generated, and to0n output is inverted. this to0n output t hat is inverted at fixed inte rvals enables to0n to output a square wave. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . figure 7-20. block diagram of square-wave output operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm00n signal output controller to0n output to0n pin figure 7-21. basic timing example of square-wave output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) to0n output compare match interrupt (inttm00n) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 293 jul 15, 2010 figure 7-22. example of register se ttings for square-wave output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output. inverts to0n output on match between tm0n and cr00n. 0/1 1 1 specifies initial value of to0n output f/f (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interval time is as follows. ? square wave frequency = 1 / [2 (m + 1) count clock cycle] setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used for the square-wave output function. however, a compare match interrupt (inttm01n) is generated when the set valu e of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 294 jul 15, 2010 figure 7-23. example of software proce ssing for square-wave output function tm0n register 0000h operable bits (tmc0n3, tmc0n2) cr00n register to0n output inttm00n signal to0n output control bit (toc0n1, toe0n) tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, toc0n register note , cr00n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow n 11 00 n n n <1> <2> 00 note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 295 jul 15, 2010 7.4.3 external event counter operation when bits 1 and 0 (prm0n1 and prm0n0) of the prescaler m ode register 0n (prm0n) are set to 11 (for counting up with the valid edge of the ti00n pin) a nd bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between tm0n and cr00n (inttm00n) is generated. to input the external event, the ti00n pi n is used. therefore, t he timer/event counter cann ot be used as an external event counter in the clear & start mode entered by the ti00n pin valid edge input (when tmc0n3 and tmc0n2 = 10). the inttm00n signal is generated with the following timing. ? timing of generation of inttm00n signal (second time or later) = number of times of detection of valid edge of external event (set value of cr00n + 1) however, the first match interrupt immediately after the time r/event counter has started ope rating is generated with the following timing. ? timing of generation of inttm00n signal (first time only) = number of times of detection of valid edge of external event input (set value of cr00n + 2) to detect the valid edge, the signa l input to the ti00n pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two time s in a row. therefore, a noise with a short pulse width can be eliminated. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . figure 7-24. block diagram of ex ternal event counter operation 16-bit counter (tm0n) cr00n register operable bits tmc0n3, tmc0n2 clear match signal inttm00n signal edge detection ti00n pin output controller to0n output to0n pin f prs remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 296 jul 15, 2010 figure 7-25. example of register settings in external event counter mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0/1 0/1 0/1 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr00n/cr01n. 01: inverts to0n output on match between tm0n and cr00n. 10: inverts to0n output on match between tm0n and cr01n. 11: inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output f/f (d) prescaler mode register 0n (prm0n) 0 0 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock (specifies valid edge of ti00n). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 011 remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 297 jul 15, 2010 figure 7-25. example of register settings in external event counter mode (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) if m is set to cr00n, the interrupt signal (inttm00n) is generated when the number of external events reaches (m + 1). setting cr00n to 0000h is prohibited. (g) 16-bit capture/compare register 01n (cr01n) usually, cr01n is not used in the external event c ounter mode. however, a compare match interrupt (inttm01n) is generated when the set valu e of cr01n matches the value of tm0n. therefore, mask the interrupt request by using the interrupt mask flag (tmmk01n). remark n = 0: 78k0/ke2 products whose flash me mory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 298 jul 15, 2010 figure 7-26. example of software proce ssing in external event counter mode tm0n register 0000h operable bits (tmc0n3, tmc0n2) 11 00 n n n tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, toc0n register note , cr00n register, port setting start stop <1> <2> compare match interrupt (inttm00n) compare register (cr00n) to0n output control bits (toc0n4, toc0n1, toe0n) to0n output n 00 initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. <1> count operation start flow <2> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 299 jul 15, 2010 7.4.4 operation in clear & start mode entered by ti00n pin valid edge input when bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode c ontrol register 0n (tmc0n) are set to 10 (clear & start mode entered by the ti00n pin valid edge input ) and the count clock (set by prm0n) is supplied to the timer/event counter, tm0n starts counting up. when the valid edge of the ti00n pin is detected during the counting operation, tm0n is cleared to 0000h and starts counting up again. if the valid edge of the ti00n pin is not detected, tm0n overflows and continues counting. the valid edge of the ti00n pin is a cause to clear tm0n. starting the counter is not c ontrolled immediately after the start of the operation. cr00n and cr01n are used as compare registers and capture registers. (a) when cr00n and cr01n ar e used as compare registers signals inttm00n and inttm01n are generated when the value of tm0n matches the value of cr00n and cr01n. (b) when cr00n and cr01n ar e used as capture registers the count value of tm0n is captur ed to cr00n and the inttm00n signal is generated when the valid edge is input to the ti01n pin (or when the phase reverse to that of the valid edge is input to the ti00n pin). when the valid edge is input to the ti 00n pin, the count value of tm0n is captured to cr01n and the inttm01n signal is generated. as soon as the count value ha s been captured, the counter is cleared to 0000h. caution do not set the count clock as the valid edge of the ti00n pin (prm0n1 and prm0n0 = 11). when prm0n1 and prm0n0 = 11, tm0n may be cleared. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . (1) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) figure 7-27. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) timer counter (tm0n) clear output controller edge detection compare register (cr01n) match signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock to0n output to0n pin remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 300 jul 15, 2010 figure 7-28. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register , cr01n: compare register) (a) toc0n = 13h, prm0n = 10h, crc0n, = 00h, tmc0n = 08h tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output m 10 m nn nn mmm 00 n (b) toc0n = 13h, prm0n = 10h, crc0n, = 00h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of bi t 1 (tmc0n1) of the 16-bit ti mer mode control register 0n (tmc0n). (a) the to0n output level is inverted wh en tm0n matches a compare register. (b) the to0n output level is inverted when tm0n matches a compare register or when the valid edge of the ti00n pin is detected. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 301 jul 15, 2010 (2) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: compare register , cr01n: capture register) figure 7-29. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) timer counter (tm0n) clear output controller edge detector capture register (cr01n) capture signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock to0n pin to0n output figure 7-30. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n, = 04h, tmc0n = 08h, cr00n = 0001h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n output 0001h 10 q p n m s 00 0000h m n s p q this is an application example where the to0n output leve l is inverted when the count value has been captured & cleared. the count value is captured to cr01n and tm0n is clea red (to 0000h) when the valid edge of the ti00n pin is detected. when the count value of tm0n is 0001h, a com pare match interrupt signal (i nttm00n) is generated, and the to0n output level is inverted. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 302 jul 15, 2010 figure 7-30. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: compare register, cr01n: capture register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n, = 04h, tmc0n = 0ah, cr00n = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application example where the width set to cr00n (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the count value is captured to cr01n, a capture interrupt signal (inttm01n) is generated, tm0n is cleared (to 0000h), and the to0n output level is inverted when the valid edge of the ti00n pin is detected. when the count value of tm0n is 0003h (four clocks have been counted), a compare match interrupt signal (inttm00n) is generated and the to0n output level is inverted. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 303 jul 15, 2010 (3) operation in clear & start mode by entered ti00n pin valid edge input (cr00n: capture register , cr01n: compare register) figure 7-31. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) timer counter (tm0n) clear output controller edge detection capture register (cr00n) capture signal match signal interrupt signal (inttm01n) interrupt signal (inttm00n) ti00n pin compare register (cr01n) operable bits tmc0n3, tmc0n2 count clock to0n pin to0n output remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 304 jul 15, 2010 figure 7-32. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n, = 03h, tmc0n = 08h, cr01n = 0001h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output 10 p n m s 00 l 0001h 0000h mns p this is an application example where the to0n output level is to be inverted when the count value has been captured & cleared. tm0n is cleared at the rising edge detect ion of the ti00n pin and it is captur ed to cr00n at the falling edge detection of the ti00n pin. when bit 1 (crc0n1) of capture/compare c ontrol register 0n (crc0n) is set to 1, the count value of tm0n is captured to cr00n in the phase reverse to that of the signal input to the ti00n pin, but the captur e interrupt signal (inttm00n) is not generated. however, the inttm00n signal is gener ated when the valid edge of the ti01n pin is detected. mask the inttm00n signal when it is not used. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 305 jul 15, 2010 figure 7-32. timing example of clear & star t mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: compare register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n, = 03h, tmc0n = 0ah, cr01n = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application example where the width set to cr01n (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. tm0n is cleared (to 0000h) at the risi ng edge detection of the ti00n pin and c aptured to cr00n at the falling edge detection of the ti00n pin. the to0n output level is inverted when tm0n is cleared (to 0000h) because the rising edge of the ti00n pin has been detected or when the value of tm0n matches t hat of a compare register (cr01n). when bit 1 (crc0n1) of capture/compare control register 0n (crc0n) is 1, the count value of tm0n is captured to cr00n in the phase reverse to that of the input signal of the ti00n pin, but t he capture interrupt signal (inttm00n) is not generated. however, the inttm00n interrupt is genera ted when the valid edge of t he ti01n pin is detected. mask the inttm00n signal when it is not used. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 306 jul 15, 2010 (4) operation in clear & start mode en tered by ti00n pin valid edge input (cr00n: capture register , cr01n: capture register) figure 7-33. block diagram of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) timer counter (tm0n) clear output controller capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin note selector to0n output to0n pin note note the timer output (to0n) cannot be used when det ecting the valid edge of the ti01n pin is used. figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (1/3) (a) toc0n = 13h, prm0n = 30h , crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where the count value is captured to cr01n, tm0n is cleared, and the to0n output is inverted when the rising or falli ng edge of the ti00n pin is detected. when the edge of the ti01n pin is detected, an interrupt signal (inttm00n ) is generated. mask the inttm00n signal when it is not used. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 307 jul 15, 2010 figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (2/3) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti01n pin input) capture register (cr00n) capture interrupt (inttm00n) capture & count clear input (ti00n) capture register (cr01n) capture interrupt (inttm01n) 10 r s t o l m n p q 00 ffffh l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to the ti00n pin, in an applicatio n where the count value is captured to cr00n when the rising or fa lling edge of the ti01n pin is detected. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 308 jul 15, 2010 figure 7-34. timing example of clear & start mode entered by ti00n pin valid edge input (cr00n: capture register, cr01n: capture register) (3/3) (c) toc0n = 13h, prm0n = 00h , crc0n = 07h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n pin input) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) capture input (ti01n) capture interrupt (inttm00n) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti00n pin is measured. by setting crc0n, the count value can be captured to cr00n in the phase reverse to the falling edge of the ti00n pin (i.e., rising edge) and to cr01n at the falling edge of the ti00n pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr01n value] ? [cr00n value] [count clock cycle] ? low-level width = [cr00n value] [count clock cycle] if the reverse phase of the ti00n pin is selected as a trigger to capture t he count value to cr00n, the inttm00n signal is not generated. read the values of cr00n and cr01n to measure the pulse width immediately after the inttm01n signal is generated. however, if the valid edge specified by bits 6 and 5 ( es1n1 and es1n0) of prescaler mode register 0n (prm0n) is input to the ti01n pin, the count valu e is not captured but the inttm00n signal is generated. to measure the pulse width of the ti00n pin, mask the in ttm00n signal when it is not used. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 309 jul 15, 2010 figure 7-35. example of register settings in clear & st art mode entered by ti00n pin valid edge input (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000100/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge input of ti00n pin. 0: inverts to0n output on match between tm0n and cr00n/cr01n. 1: inverts to0n output on match between tm0n and cr00n/cr01n and valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr00n used as compare register 1: cr00n used as capture register 0: cr01n used as compare register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output note 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr00n/cr01n. 01: inverts to0n output on match between tm0n and cr00n. 10: inverts to0n output on match between tm0n and cr01n. 11: inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output f/f 0/1 0/1 0/1 note the timer output (to0n) cannot be used when det ecting the valid edge of the ti01n pin is used. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 310 jul 15, 2010 figure 7-35. example of register settings in clear & st art mode entered by ti00n pin valid edge input (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti00n valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) when this register is used as a compare register a nd when its value matches t he count value of tm0n, an interrupt signal (inttm00n) is generated. the count value of tm0n is not cleared. to use this register as a capture regist er, select either the ti00n or ti01n pin note input as a capture trigger. when the valid edge of the capture trigger is detect ed, the count value of tm0n is stored in cr00n. note the timer output (to0n) cannot be used when detection of the vali d edge of the ti01n pin is used. (g) 16-bit capture/compare register 01n (cr01n) when this register is used as a compare register a nd when its value matches t he count value of tm0n, an interrupt signal (inttm01n) is generated. the count value of tm0n is not cleared. when this register is used as a captur e register, the ti00n pin input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm0n is stored in cr01n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 311 jul 15, 2010 figure 7-36. example of software processing in clear & start mode entered by ti 00n pin valid edge input tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti00n pin input) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc0n3, tmc0n2 bits = 10 edge input to ti00n pin register initial setting prm0n register, crc0n register, toc0n register note , cr00n, cr01n registers, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 10. starts count operation when the valid edge is input to the ti00n pin, the value of the tm0n register is cleared. start <1> count operation start flow <2> tm0n register clear & start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 312 jul 15, 2010 7.4.5 free-running timer operation when bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) are set to 01 (free-running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. when it has counted up to ffffh, the overflow flag (ovf0n) is set to 1 at the next clock, and tm0n is cleared (to 0000h) and continues counting. clear ovf0n to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both cr00n and cr01n are used as compare registers. ? one of cr00n or cr01n is used as a compare regi ster and the other is us ed as a capture register. ? both cr00n and cr01n are used as capture registers. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . (1) free-running timer mode operation (cr00n: compare register , cr01n: compare register) figure 7-37. block diagram of free-running timer mode (cr00n: compare register, cr01n: compare register) timer counter (tm0n) output controller compare register (cr01n) match signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock to0n pin to0n output remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 313 jul 15, 2010 figure 7-38. timing example of free-running timer mode (cr00n: compare register, cr01n: compare register) ? toc0n = 13h, prm0n = 00h, crc0n = 00h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output ovf0n bit 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the to0n output level is reversed each time the count va lue of tm0n matches the set value of cr00n or cr01n. when the count value matches the register val ue, the inttm00n or inttm01n signal is generated. (2) free-running timer mode operation (cr00n: compare register , cr01n: capture register) figure 7-39. block diagram of free-running timer mode (cr00n: compare register, cr01n: capture register) timer counter (tm0n) output controller edge detection capture register (cr01n) capture signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) ti00n pin compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock to0n pin to0n output remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 314 jul 15, 2010 figure 7-40. timing example of free-running timer mode (cr00n: compare register, cr01n: capture register) ? toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) compare register (cr00n) compare match interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) to0n output overflow flag (ovf0n) 0 write clear 0 write clear 0 write clear 0 write clear 01 m n s p q 00 0000h 0000h mn s p q this is an application example where a compare register and a capture register are used at the same time in the free- running timer mode. in this example, the inttm00n signal is generated and the to0n output level is reversed each time the count value of tm0n matches the set value of cr00n (compare register). in addition, the inttm01n signal is generated and the count value of tm0n is captured to cr01n each ti me the valid edge of t he ti00n pin is detected. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 315 jul 15, 2010 (3) free-running timer mode operation (cr00n: capture register , cr01n: capture register) figure 7-41. block diagram of free-running timer mode (cr00n: capture register, cr01n: capture register) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin selector remarks 1. if both cr00n and cr01n are used as capture register s in the free-running timer mode, the to0n output level is not inverted. however, it can be inverted each time the valid edg e of the ti00n pin is detect ed if bit 1 (tmc0n1) of 16- bit timer mode control register 0n (tmc0n) is set to 1. 2. n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 316 jul 15, 2010 figure 7-42. timing example of free-running timer mode (cr00n: capture register, cr01n: capture register) (1/2) (a) toc0n = 13h, prm0n = 50h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q this is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate captur e registers in the free-running timer mode. the count value is captured to cr01n when the valid edge of the ti00n pin input is det ected and to cr00n when the valid edge of the ti01n pin input is detected. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 317 jul 15, 2010 figure 7-42. timing example of free-running timer mode (cr00n: capture register, cr01n: capture register) (2/2) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example where bot h the edges of the ti01n pin are detect ed and the count value is captured to cr00n in the free-running timer mode. when both cr00n and cr01n are used as c apture registers and when the valid e dge of only the ti01n pin is to be detected, the count value c annot be captured to cr01n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 318 jul 15, 2010 figure 7-43. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode 0: inverts to0n output on match between tm0n and cr00n/cr01n. 1: inverts to0n output on match between tm0n and cr00n/cr01n valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr00n used as compare register 1: cr00n used as capture register 0: cr01n used as compare register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr00n/cr01n. 01: inverts to0n output on match between tm0n and cr00n. 10: inverts to0n output on match between tm0n and cr01n. 11: inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 319 jul 15, 2010 figure 7-43. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti00n valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) when this register is used as a compare register a nd when its value matches t he count value of tm0n, an interrupt signal (inttm00n) is generated. the count value of tm0n is not cleared. to use this register as a capture register, select either the ti00n or ti01n pin input as a capture trigger. when the valid edge of the capture trigger is detect ed, the count value of tm0n is stored in cr00n. (g) 16-bit capture/compare register 01n (cr01n) when this register is used as a compare register a nd when its value matches t he count value of tm0n, an interrupt signal (inttm01n) is generated. the count value of tm0n is not cleared. when this register is used as a captur e register, the ti00n pin input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm0n is stored in cr01n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 320 jul 15, 2010 figure 7-44. example of software pr ocessing in free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) timer output control bits (toe0n, toc0n4, toc0n1) to0n output m 01 n n n n m m m 00 <1> <2> 00 n tmc0n3, tmc0n2 bits = 0, 1 register initial setting prm0n register, crc0n register, toc0n register note , cr00n/cr01n register, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 01. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 321 jul 15, 2010 7.4.6 ppg output operation a square wave having a pulse width set in advance by cr01n is output from the to0n pin as a ppg (programmable pulse generator) signal during a cycle set by cr00n when bits 3 and 2 (tmc0n3 and tmc0n2) of 16-bit timer mode control register 0n (tmc0n) are set to 11 (cle ar & start upon a match between tm0n and cr00n). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of cr00n + 1) count clock cycle ? duty = (set value of cr01n + 1) / (set value of cr00n + 1) caution to change the duty factor (value of cr01n) dur ing operation, see 7.5.1 re writing cr01n during tm0n operation. remarks 1. for the setting of i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . figure 7-45. block diagram of ppg output operation timer counter (tm0n) clear output controller compare register (cr01n) match signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock to0n pin to0n output remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 322 jul 15, 2010 figure 7-46. example of register se ttings for ppg output operation (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output 11: inverts to0n output on match between tm0n and cr00n/cr01n. 00: disables one-shot pulse output specifies initial value of to0n output f/f 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 323 jul 15, 2010 figure 7-46. example of register se ttings for ppg output operation (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) an interrupt signal (inttm00n) is gener ated when the value of this register matches the count value of tm0n. the count value of tm0n is cleared. (g) 16-bit capture/compare register 01n (cr01n) an interrupt signal (inttm01n) is gener ated when the value of this register matches the count value of tm0n. the count value of tm0n is not cleared. caution set values to cr00n and cr 01n such that th e condition 0000h cr01n < cr00n ffffh is satisfied. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 324 jul 15, 2010 figure 7-47. example of software pr ocessing for ppg output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) timer output control bits (toe0n, toc0n4, toc0n1) to0n output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc0n3, tmc0n2 bits = 11 register initial setting prm0n register, crc0n register, toc0n register note , cr00n, cr01n registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remarks 1. ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1) 2. n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 325 jul 15, 2010 7.4.7 one-shot pulse output operation a one-shot pulse can be output by setting bits 3 and 2 (tmc 0n3 and tmc0n2) of the 16-bit timer mode control register 0n (tmc0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti 00n pin valid edge) and setting bit 5 (ospe0n) of 16-bit timer output c ontrol register 0n (toc0n) to 1. when bit 6 (ospt0n) of toc0n is set to 1 or when the va lid edge is input to the ti00n pin during timer operation, clearing & starting of tm0n is triggered, a nd a pulse of the difference between the values of cr00n and cr01n is output only once from the to0n pin. cautions 1. do not input the trigger again (setting ospt 0n to 1 or detecting the valid edge of the ti00n pin) while the one-shot pulse is output. to output th e one-shot pulse again, gene rate the trigger after the current one-shot pulse output has completed. 2. to use only the setting of o spt0n to 1 as the trigger of one-s hot pulse output, do not change the level of the ti00n pin or its alte rnate function port pin. other wise, the pulse will be unexpectedly output. remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . figure 7-48. block diagram of on e-shot pulse output operation timer counter (tm0n) output controller compare register (cr01n) match signal match signal interrupt signal (inttm00n) interrupt signal (inttm01n) compare register (cr00n) operable bits tmc0n3, tmc0n2 count clock ti00n edge detection ospt0n bit ospe0n bit clear to0n pin to0n output remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 326 jul 15, 2010 figure 7-49. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode by valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0/1 1 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output inverts to0n output on match between tm0n and cr00n/cr01n. specifies initial value of to0n output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 327 jul 15, 2010 figure 7-49. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) this register is used as a compare register when a one- shot pulse is output. when the value of tm0n matches that of cr00n, an interrupt signal (inttm00n) is generated and the to0n output level is inverted. (g) 16-bit capture/compare register 01n (cr01n) this register is used as a compare register when a one- shot pulse is output. when the value of tm0n matches that of cr01n, an interrupt signal (inttm01n) is generated and the to0n output level is inverted. caution do not set the same value to cr00n and cr01n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 328 jul 15, 2010 figure 7-50. example of software processing for one-shot pulse output operation (1/2) ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) one-shot pulse enable bit (ospe0n) one-shot pulse trigger bit (ospt0n) one-shot pulse trigger input (ti00n pin) overflow plug (ovf0n) compare register (cr00n) compare match interrupt (inttm00n) compare register (cr01n) compare match interrupt (inttm01n) to0n output to0n output control bits (toe0n, toc0n4, toc0n1) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to0n output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2,] 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 329 jul 15, 2010 figure 7-50. example of software processing for one-shot pulse output operation (2/2) tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, toc0n register note , cr00n, cr01n registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow toc0n.ospt0n bit = 1 or edge input to ti00n pin write the same value to the bits other than the ostp0n bit. note care must be exercised when setting toc0n. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 330 jul 15, 2010 7.4.8 pulse width measurement operation tm0n can be used to measure the pulse width of the signal input to the ti00n and ti01n pins. measurement can be accomplished by operat ing the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the ti00n pin. when an interrupt is generated, read the va lue of the valid capture register and measure the pulse width. check bit 0 (ovf0n) of 16-bit timer mode control re gister 0n (tmc0n). if it is set (to 1), clear it to 0 by software. figure 7-51. block di agram of pulse width measureme nt (free-running timer mode) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin selector figure 7-52. block diagram of pulse width measurement (clear & start mode entered by ti00n pin valid edge input) timer counter (tm0n) capture register (cr00n) capture signal capture signal interrupt signal (inttm01n) interrupt signal (inttm00n) capture register (cr01n) operable bits tmc0n3, tmc0n2 count clock edge detection ti00n pin edge detection ti01n pin clear selector remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 331 jul 15, 2010 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti00n and ti01n pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti00n pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti00n pin (clear & start mode entered by the ti00n pin valid edge input) remarks 1. for the setting of the i/o pins, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n signal interrupt, see chapter 20 interrupt functions . (1) measuring the pulse width by using two input signals of the ti00n and ti01n pi ns (free-running timer mode) set the free-running timer mode (tmc0n3 and tmc0n2 = 01). when the valid edge of the ti00n pin is detected, the count value of tm0n is captured to cr01n. when the valid edge of the ti01n pin is det ected, the count value of tm0n is captured to cr00n. specify detection of both the edges of the ti00n and ti01n pins. by this measurement method, the previ ous count value is subtracted from t he count value captured by the edge of each input signal. therefore, save the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the previous ly captured value is simply subtracted from the current captured value and, t herefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc0n) to 0. figure 7-53. timing example of pulse width measurement (1) ? tmc0n = 04h, prm0n = f0h, crc0n = 05h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 332 jul 15, 2010 (2) measuring the pulse width by using one input si gnal of the ti00n pin (free-running timer mode) set the free-running timer mode (tmc0n3 and tmc0n2 = 01). t he count value of tm0n is captured to cr00n in the phase reverse to the valid edge detected on the ti00n pin. when the valid edge of the ti00n pin is detected, the count value of tm0n is captured to cr01n. by this measurement method, values are stored in separat e capture registers when a width from one edge to another is measured. therefore, the capture values do not have to be saved. by subtracting the value of one capture register from that of another, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one captured value is simply s ubtracted from another and, therefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear bit 0 (ovf0n) of 16-bit timer mode control register 0n (tmc0n) to 0. figure 7-54. timing example of pulse width measurement (2) ? tmc0n = 04h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) overflow flag (ovf0n) capture trigger input (ti01n) capture interrupt (inttm00n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 333 jul 15, 2010 (3) measuring the pulse width by using one input signal of the ti00n pin (clear & start mode entered by the ti00n pin valid edge input) set the clear & start mode entered by the ti00n pin vali d edge (tmc0n3 and tmc0n2 = 10). the count value of tm0n is captured to cr00n in the phase reverse to the valid edge of the ti00n pin, and the count value of tm0n is captured to cr01n and tm0n is cleared (0000h) when the valid edge of the ti00n pin is det ected. therefore, a cycle is stored in cr01n if tm0n does not overflow. if an overflow occurs, take the value that results from addi ng 10000h to the value stored in cr01n as a cycle. clear bit 0 (ovf0n) of 16-bit timer mode co ntrol register 0n (tmc0n) to 0. figure 7-55. timing example of pulse width measurement (3) ? tmc0n = 08h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n) capture register (cr00n) capture register (cr01n) capture interrupt (inttm01n) overflow flag (ovf0n) capture trigger input (ti01n) capture interrupt (inttm00n) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf0n bit is set to 1 + captured value of cr01n) count clock cycle <2> high-level pulse width = (10000h number of times ovf0n bit is set to 1 + captured value of cr00n) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 334 jul 15, 2010 figure 7-56. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode entered by valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 0000010/11 crc0n2 crc0n1 crc0n0 1: cr00n used as capture register 1: cr01n used as capture register 0: ti01n pin is used as capture trigger of cr00n. 1: reverse phase of ti00n pin is used as capture trigger of cr00n. (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 3 2 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock (setting valid edge of ti00n is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc0n1 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 335 jul 15, 2010 figure 7-56. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 0n (tm0n) by reading tm0n, the count value can be read. (f) 16-bit capture/compare register 00n (cr00n) this register is used as a capture regi ster. either the ti00n or ti01n pin is se lected as a capture trigger. when a specified edge of the c apture trigger is detected, the coun t value of tm0n is stored in cr00n. (g) 16-bit capture/compare register 01n (cr01n) this register is used as a capture regi ster. the signal input to the ti00n pi n is used as a capture trigger. when the capture trigger is det ected, the count value of tm0n is stored in cr01n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 336 jul 15, 2010 figure 7-57. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti00n) capture register (cr01n) capture interrupt (inttm01n) capture trigger input (ti01n) capture register (cr00n) capture interrupt (inttm00n) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti00n pin valid edge ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti00n) capture register (cr00n) capture interrupt (inttm00n) capture register (cr01n) capture interrupt (inttm01n) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 337 jul 15, 2010 figure 7-57. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti00n, ti01n pins calculated pulse width from capture value stores count value to cr00n, cr01n registers generates capture interrupt note tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (inttm00n) is not gener ated when the reverse-phase edge of the ti00n pin input is selected to the valid edge of cr00n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 338 jul 15, 2010 7.5 special use of tm0n 7.5.1 rewriting cr01n during tm0n operation in principle, rewriting cr00n and cr01n of the 78k0/kx2 microcontrollers when they are used as compare registers is prohibited while tm0n is operating (t mc0n3 and tmc0n2 = other than 00). however, the value of cr01n can be changed, even while tm0n is operating, using the following procedure if cr01n is used for ppg output and the duty factor is changed. (when changing the value of cr01n to a smaller value than the current one, rewrite it immediately after its value matches the value of tm0n. when changing the value of cr01n to a larger value than the current one, rewrite it immediately after the values of cr00n and tm0n match. if the value of cr01n is rewritten immediately before a match between cr01n and tm0n, or between cr00n and tm0n, an unexpected operation may be performed.). procedure for changing value of cr01n <1> disable interrupt inttm01n (tmmk01n = 1). <2> disable reversal of the timer output when th e value of tm0n matches that of cr01n (toc0n4 = 0). <3> change the value of cr01n. <4> wait for one cycle of the count clock of tm0n. <5> enable reversal of the timer output when the value of tm0n matches that of cr01n (toc0n4 = 1). <6> clear the interrupt flag of inttm01n (tmif01n = 0) to 0. <7> enable interrupt inttm01n (tmmk01n = 0). remark for tmif01n and tmmk01n, see chapter 20 interrupt functions . 7.5.2 setting lvs0n and lvr0n (1) usage of lvs0n and lvr0n lvs0n and lvr0n are used to set the defau lt value of the to0n output and to in vert the timer output without enabling the timer operation (tmc0n3 and tmc0n2 = 00). clear lvs 0n and lvr0n to 00 (default value: low-level output) when software control is unnecessary. lvs0n lvr0n timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 339 jul 15, 2010 (2) setting lvs0n and lvr0n set lvs0n and lvr0n using the following procedure. figure 7-58. example of flow for setting lvs0n and lvr0n bits setting toc0n.ospe0n, toc0n4, toc0n1 bits setting toc0n.toe0n bit setting toc0n.lvs0n, lvr0n bits setting tmc0n.tmc0n3, tmc0n2 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set lvs0n and lvr0n fo llowing steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 7-59. timing example of lvr0n and lvs0n toc0n.lvs0n bit toc0n.lvr0n bit operable bits (tmc0n3, tmc0n2) to0n output inttm00n signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to0n output goes high when lvs0n and lvr0n = 10. <2> the to0n output goes low when l vs0n and lvr0n = 01 (the pin output re mains unchanged from the high level even if lvs0n and lvr0n are cleared to 00). <3> the timer starts operating when tmc0n3 and tmc0n2 are set to 01, 10, or 11. because lvs0n and lvr0n were set to 10 before the operation wa s started, the to0n output starts from the high level. after the timer starts operating, setting lvs0n and lvr0n is prohibit ed until tmc0n3 and tmc0n2 = 00 (disabling the timer operation). <4> the to0n output level is inverted each time an interrupt signal (inttm00n) is generated. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 340 jul 15, 2010 7.6 cautions for 16-bit timer/event counters 00 and 01 (1) restrictions for each channel of 16-bit timer/event counter 0n table 7-3 shows the restrictions for each channel. table 7-3. restrictions for each ch annel of 16-bit timer/event counter 0n operation restriction as interval timer as square-wave output as external event counter ? as clear & start mode entered by ti00n pin valid edge input using timer output (to0n) is prohibited when det ection of the valid edge of the ti01n pin is used. (toc0n = 00h) as free-running timer ? as ppg output 0000h cp01n < cr00n ffffh as one-shot pulse output setting the same value to cr00n and cp01n is prohibited. as pulse width measurement using timer output (to0n) is prohibited (toc0n = 00h) (2) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because counting tm0n is started asynchronously to the count pulse. figure 7-60. start timing of tm0n count 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value (3) setting of cr00n and cr01n (c lear & start mode entered upon a match between tm0n and cr00n) set a value other than 0000h to cr00n and cr01n (tm0n ca nnot count one pulse when it is used as an external event counter). remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 341 jul 15, 2010 (4) timing of holding data by capture register (a) when the valid edge is input to the ti00n/ti01n pin and the reverse phase of the ti00n pin is detected while cr00n/cr01n is read, cr01n performs a capture operation but the r ead value of cr00n/cr01n is not guaranteed. at this time, an interrupt signal (i nttm00n/inttm01n) is generated when the valid edge of the ti00n/ti01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the ti00n pin is detected). when the count value is captured because the valid edge of the ti00n/ti01n pin was detec ted, read the value of cr00n/cr01n after inttm00n/inttm01n is generated. figure 7-61. timing of holding data by capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm01n value captured to cr01n capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of cr00n and cr01n are not guarant eed after 16-bit timer/event counter 0n stops. (5) setting valid edge set the valid edge of the ti00n pin while the timer oper ation is stopped (tmc0n3 and tmc0n2 = 00). set the valid edge by using es0n0 and es0n1. (6) re-triggering one-shot pulse make sure that the trigger is not gen erated while an active level is being output in the one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 342 jul 15, 2010 (7) operation of ovf0n flag (a) setting ovf0n flag (1) the ovf0n flag is set to 1 in the following case, as well as when tm0n overflows. select the clear & start mode entered upon a match between tm0n and cr00n. set cr00n to ffffh. when tm0n matches cr00n and tm0n is cleared from ffffh to 0000h figure 7-62. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm00n ovf0n cr00n (b) clearing ovf0n flag even if the ovf0n flag is cleared to 0 after tm0n overfl ows and before the next count clock is counted (before the value of tm0n becomes 0001h), it is set to 1 again and clearing is invalid. (8) one-shot pulse output one-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the ti00n pin valid edge. the one-shot pu lse cannot be output in the clear & start mode entered upon a match between tm0n and cr00n. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 343 jul 15, 2010 (9) capture operation (a) when valid edge of ti00n is specified as count clock when the valid edge of ti00n is specified as the count clock, the capture register for whic h ti00n is specified as a trigger does not operate correctly. (b) pulse width to accurately capture value by signals input to ti01n and ti00n pins to accurately capture the count value, the pulse input to the ti00n and ti01n pins as a capture trigger must be wider than two count clocks selected by prm0n (see figure 7-9 ). (c) generation of interrupt signal the capture operation is per formed at the falling edge of the count cl ock but the interrupt signals (inttm00n and inttm01n) are generated at the rising edge of the next count clock (see figure 7-9 ). (d) note when crc0n1 (bit 1 of capture/compare control register 0n (crc0n)) is set to 1 when the count value of the tm0n register is captured to the cr00n register in the phase reverse to the signal input to the ti00n pin, the interrupt si gnal (inttm00n) is not generated after t he count value is captured. if the valid edge is detected on the ti01n pin during this operat ion, the capture operation is not performed but the inttm00n signal is generated as an external interrupt signal. mask the inttm00n signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/event counter 0n is enabled after reset and while the ti00n or ti01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti00n or ti01n pin, then the high level of the ti00n or ti0 1n pin is detected as the rising edge. note this when the ti00n or ti01n pin is pulled up. however, the rising edge is not det ected when the operation is once stopped and then enabled again. (b) sampling clock for eliminating noise the sampling clock for eliminating noise differs dependi ng on whether the valid edge of ti00n is used as the count clock or capture trigger. in the fo rmer case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm0n is used for sampling. when the signal input to the ti00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 7-9 ). (11) timer operation the signal input to the ti00n/ti01n pin is not acknowledg ed while the timer is stopped, regardless of the operation mode of the cpu. remarks 1. f prs : peripheral hardware clock frequency 2. n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 7 16-bit ti mer/event counters 00 and 01 r01uh0008ej0401 rev.4.01 344 jul 15, 2010 (12) reading of 16-bit timer counter 0n (tm0n) tm0n can be read without stopping the actual counter, bec ause the count values captured to the buffer are fixed when it is read. the buffer, however, may not be updated w hen it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. figure 7-63. 16-bit timer count er 0n (tm0n) read timing count clock tm0n count value 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 0034h 0035h 0037h 0038h 003bh read buffer read signal remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 345 jul 15, 2010 chapter 8 8-bit timer/even t counters 50 and 51 8.1 functions of 8-bit ti mer/event counters 50 and 51 8-bit timer/event counters 50 and 51 are mounted onto all 78k0/kx2 microcontroller products. 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output 8.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) or port mode register 3 (pm3) port register 1 (p1) or port register 3 (p3) figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 346 jul 15, 2010 figure 8-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p17 match mask circuit ovf 3 clear tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector to tmh0 to uart0 to uart6 inttm50 note 1 note 2 selector 8-bit timer counter 50 (tm50) selector to50 output to50/ti50/ p17 output latch (p17) pm17 f prs /2 13 f prs f prs /2 f prs /2 2 f prs /2 8 f prs /2 6 figure 8-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/ p33/intp4 match mask circuit ovf 3 clear tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p33/intp4 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector to51 output output latch (p33) pm33 f prs /2 12 f prs f prs /2 f prs /2 6 f prs /2 4 f prs /2 8 notes 1. timer output f/f 2. pwm output f/f 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 347 jul 15, 2010 (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 8-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset signal generation <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which cl ear & start occurs upon a match of the tm5n and cr5n. (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in the pwm mode, to5n output becomes inactive when the va lues of tm5n and cr5n match, but no interrupt is generated. the value of cr5n can be set within 00h to ffh. reset signal generation clears cr5n to 00h. figure 8-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in which clear & start o ccurs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 348 jul 15, 2010 8.3 registers controlling 8-bit ti mer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 1 (pm1) or port mode register 3 (pm3) ? port register 1 (p1) or port register 3 (p3) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit timer/ev ent counter 5n and the valid edge of the ti5n pin input. tcl5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears tcl5n to 00h. remark n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 349 jul 15, 2010 figure 8-5. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 count clock selection note 1 tcl502 tcl501 tcl500 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti50 pin falling edge note 2 0 0 1 ti50 pin rising edge note 2 0 1 0 f prs note 3 2 mhz 5 mhz 10 mhz 20 mhz note 4 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 13 0.24 khz 0.61 khz 1.22 khz 2.44 khz notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. do not start timer operation with the external cl ock from the ti50 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. 3. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tcl502, tcl501, tcl500 = 0, 1, 0 (count clock: f prs ) is prohibited. 4. this is settable only if 4.0 v v dd 5.5 v. cautions 1. when rewriting tcl50 to othe r data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to ?0?. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 350 jul 15, 2010 figure 8-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 count clock selection note 1 tcl512 tcl511 tcl510 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti51 pin falling edge note 2 0 0 1 ti51 pin rising edge note 2 0 1 0 f prs note 3 2 mhz 5 mhz 10 mhz 20 mhz note 4 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 12 0.49 khz 1.22 khz 2.44 khz 4.88 khz notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. do not start timer operation with the external cl ock from the ti51 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. 3. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tcl512, tcl511, tcl510 = 0, 1, 0 (count clock: f prs ) is prohibited. 4. this is settable only if 4.0 v v dd 5.5 v. cautions 1. when rewriting tcl51 to othe r data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to ?0?. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 351 jul 15, 2010 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 figure 8-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to50 output: low level) 1 0 timer output f/f set (1) (defaul t value of to50 output: high level) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (to50 output is low level) 1 output enabled note bits 2 and 3 are write-only. ( cautions and remarks are listed on the next page.) 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 352 jul 15, 2010 figure 8-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to51 output: low) 1 0 timer output f/f set (1) (default value of to51 output: high) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (to51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6 : operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n 3. when tce5n = 1, setting the ot her bits of tmc5n is prohibited. 4. the actual to50/ti50/p17 a nd to51/ti51/p33/intp4 pin output s are determined depending on pm17 and p17, and pm33 and p33, besides to5n output. remarks 1. in pwm mode, pwm output is made inactive by clearing tce5n to 0. 2. if lvs5n and lvr5n are read, the value is 0. 3. the values of the tmc5n6, lvs 5n, lvr5n, tmc5n1, and toe5n bits are reflected at the to5n output regardless of the value of tce5n. 4. n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 353 jul 15, 2010 (3) port mode registers 1 and 3 (pm1, pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p3 3/to51/ti51/intp4 pins for timer output, clear pm17 and pm33 and the output latches of p17 and p33 to 0. when using the p17/to50/ti50 and p33/to 51/ti51/intp4 pins for timer input, set pm17 and pm33 to 1. the output latches of p17 and p33 at this time may be 0 or 1. pm1 and pm3 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 8-9. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 8-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 354 jul 15, 2010 8.4 operations of 8-bit timer/event counters 50 and 51 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer th at generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (t cl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don?t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, intt m5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 20 interrupt functions . 2. n = 0, 1 figure 8-11. interval ti mer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 01h to ffh n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 355 jul 15, 2010 figure 8-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 356 jul 15, 2010 8.4.2 operation as external event counter the external event counter counts the num ber of external clock pulses to be input to the ti5n pin by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the va lue of 8-bit timer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? set the port mode register (pm17 or pm33) note to 1. ? tcl5n: select ti5n pin input edge. ti5n pin falling edge tcl5n = 00h ti5n pin rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 00000000b) <2> when tce5n = 1 is set, the number of pu lses input from the ti5n pin is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. note 8-bit timer/event counter 50: pm17 8-bit timer/event counter 51: pm33 remark for how to enable the inttm5n signal interrupt, see chapter 20 interrupt functions . figure 8-12. external event counter oper ation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n count start remark n = 00h to ffh n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 357 jul 15, 2010 8.4.3 square-wave output operation a square wave with any selected frequency is output at interval s determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control regi ster 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count oper ation, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 0 1 timer output f/f clear (0) (default value of to5n output: low level) 1 0 timer output f/f set (1) (defaul t value of to5n output: high level) timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at t he same interval and a square wave is output from to5n. the frequency is as follows. ? frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 20 interrupt functions . 2. n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 358 jul 15, 2010 figure 8-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output can be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 8.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8- bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the ac tive level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 359 jul 15, 2010 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 pwm output operation <1> pwm output (to5n output) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 8-14 and 8-15 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 360 jul 15, 2010 figure 8-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> inactive level <3> inactive level <5> inactive level t <2> active level (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n 01h 00h ffh 00h 01h 02h 00h ffh 00h 01h 02h m 00h to5n l (inactive level) t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h ffh <1> inactive level <2> active level ffh 00h 01h 02h m 00h <3> inactive level <2> active level <5> inactive level t remarks 1. <1> to <3> and <5> in figure 8-14 (a) and (c) correspond to <1> to <3> and <5> in pwm output operation in 8.4.4 (1) pwm output basic operation . 2. n = 0, 1 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 361 jul 15, 2010 (2) operation with cr5n changed figure 8-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n between <1> and <2> in figure 8-15, the value read differs from the actual value (read value: m, actual value of cr5n: n). 78k0/kx2 chapter 8 8-bit ti mer/event counters 50 and 51 r01uh0008ej0401 rev.4.01 362 jul 15, 2010 8.5 cautions for 8-bit ti mer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm51) are started asynchronously to the count clock. figure 8-16. 8-bit timer counter 5n (tm5n) start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start (2) reading of 8-bit timer counter 5n (tm5n) tm5n can be read without stopping the actual counter, bec ause the count values captured to the buffer are fixed when it is read. the buffer, however, may not be updated w hen it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. figure 8-17. 8-bit timer counter 5n (tm5n) read timing 34h 35h 36h 37h 38h 39h 3ah 3bh 34h 35h 37h 38h 3bh count clock tm5n count value read buffer read signal remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 363 jul 15, 2010 chapter 9 8-bit timers h0 and h1 9.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 are mounted onto all 78k0/kx2 microcontroller products. 8-bit timers h0 and h1 have the following functions. ? interval timer ? square-wave output ? pwm output ? carrier generator (8-bit timer h1 only) 9.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 include the following hardware. table 9-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output tohn, output controller control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note port mode register 1 (pm1) port register 1 (p1) note 8-bit timer h1 only remark n = 0, 1 figures 9-1 and 9-2 show the block diagrams. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 364 jul 15, 2010 figure 9-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 inttmh0 1 0 f/f r 3 2 match internal bus 8-bit timer h mode register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0 toh0/p15 toh0 output pm15 output latch (p15) f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 365 jul 15, 2010 figure 9-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector interrupt generator output controller level inversion pm16 output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode register 1 (tmhmd1) selector toh1 output f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl f rl /2 7 f rl /2 9 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 366 jul 15, 2010 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory mani pulation instruction. this r egister is used in all of the timer operation modes. this register constantly compares t he value set to cmp0n with the count value of the 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn) and inverts the output level of tohn. rewrite the value of cmp0n while the timer is stopped (tmhen = 0). a reset signal generation clears this register to 00h. figure 9-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritten during timer count operation. cmp0 n can be refreshed (the same value is written) during ti mer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory mani pulation instruction. this register is used in the pwm output mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to cmp1n with the count value of the 8-bit timer counter hn and, when the two values match, inverts t he output level of tohn. no interrupt request signal is generated. in the carrier generator mode, the cmp 1n register always compares the value set to cmp1n with the count value of the 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn). at the same time, the count value is cleared. cmp1n can be refreshed (the same value is writt en) and rewritten during timer count operation. if the value of cmp1n is rewritten while the timer is oper ating, the new value is latched and transferred to cmp1n when the count value of the timer matches the old value of cmp1n, and then the value of cmp1n is changed to the new value. if matching of the count value and the cmp1n va lue and writing a value to cmp1n conflict, the value of cmp1n is not changed. a reset signal generation clears this register to 00h. figure 9-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 caution in the pwm output mode and carrier generator mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to cmp1n). remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 367 jul 15, 2010 9.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 1 (pm1) ? port register 1 (p1) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 368 jul 15, 2010 figure 9-5. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 count clock selection note 1 other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> f prs note 2 f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 tm50 output note 4 setting prohibited f prs = 2 mhz 2 mhz 1 mhz 500 khz 31.25 khz 1.95 khz f prs = 5 mhz 5 mhz 2.5 mhz 1.25 mhz 78.13 khz 4.88 khz f prs = 10 mhz 10 mhz 5 mhz 2.5 mhz 156.25 khz 9.77 khz f prs = 20 mhz 20 mhz note 3 10 mhz 5 mhz 312.5 khz 19.54 khz notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 369 jul 15, 2010 notes 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks02 = c ks01 = cks00 = 0 (count clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. 4. note the following points when select ing the tm50 output as the count clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 fi rst and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. cautions 1. when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. however, tmhmd0 can be refreshed (the same va lue is written). 2. in the pwm output mode, be sure to set th e 8-bit timer h compare re gister 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). 3. the actual toh0/p15 pin output is determi ned depending on pm15 and p15, besides toh0 output. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 370 jul 15, 2010 figure 9-6. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control <7> 6 5 4 3 2 <1> <0> cks12 0 0 0 0 1 1 1 1 cks11 0 0 1 1 0 0 1 1 cks10 0 1 0 1 0 1 0 1 count clock selection note 1 f prs note 2 f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl /2 7 f rl /2 9 f rl f prs = 2 mhz 2 mhz 500 khz 125 khz 31.25 khz 0.49 khz 1.88 khz (typ.) 0.47 khz (typ.) 240 khz (typ.) f prs = 5 mhz 5 mhz 1.25 mhz 312.5 khz 78.13 khz 1.22 khz f prs = 10 mhz 10 mhz 2.5 mhz 625 khz 156.25 khz 2.44 khz f prs = 20 mhz 20 mhz note 3 5 mhz 1.25 mhz 312.5 khz 4.88 khz notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 371 jul 15, 2010 notes 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks12 = c ks11 = cks10 = 0 (count clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. cautions 1. when tmhe1 = 1, setti ng the other bits of tmhmd1 is prohibited. however, tmhmd1 can be refreshed (the same va lue is written). 2. in the pwm output mode and carrier generato r mode, be sure to set the 8-bit timer h compare register 11 (cmp11) when starti ng the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). 3. when the carrier generator mode is used, set so that the count cl ock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. 4. the actual toh1/intp5/p16 pin output is de termined depending on pm16 and p16, besides toh1 output. remarks 1. f prs : peripheral hardware clock frequency 2. f rl : internal low-speed oscillation clock frequency (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 9-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note low-level output high-level output at rising edge of inttm51 signal input low-level output carrier pulse output at rising edge of inttm51 signal input rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. caution do not rewrite rmc1 when tmhe = 1. ho wever, tmcyc1 can be refreshed (the same value is written). 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 372 jul 15, 2010 (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p15/toh0 and p16/toh1/intp5 pins for ti mer output, clear pm15 and pm16 and the output latches of p15 and p16 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 373 jul 15, 2010 9.4 operation of 8-bit timers h0 and h1 9.4.1 operation as inter val timer/square-wave output when the 8-bit timer counter hn and com pare register 0n (cmp0n) match, an in terrupt request signal (inttmhn) is generated and the 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of the 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmhmd n) to 1, a square wave of any frequency (duty = 50%) is output from tohn. setting <1> set each register. figure 9-9. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting default setting of timer output level interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting the interval time is as follows if n is set as a comparison value. ? interval time = (n +1)/f cnt <2> count operation starts when tmhen = 1. <3> when the values of the 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and the 8-bit timer counter hn is cleared to 00h. <4> subsequently, the inttmhn signal is generated at the sa me interval. to stop the count operation, clear tmhen to 0. remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for how to enable the inttmhn signal interrupt, see chapter 20 interrupt functions . 3. n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 374 jul 15, 2010 figure 9-10. timing of interval time r/square-wave output operation (1/2) (a) basic operation (operation when 01h cmp0n feh) 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bit to 1. the coun t clock starts counting no more than 1 clock after the operation is enabled. <2> when the value of the 8-bit timer counter hn matches the value of the cmp0n regist er, the value of the timer counter is cleared, and the level of the tohn output is inverted. in addition, the inttmhn si gnal is output at the rising edge of the count clock. <3> if the tmhen bit is cleared to 0 while timer h is oper ating, the inttmhn signal and tohn output are set to the default level. if they are already at the default level before the tmhen bit is cleared to 0, then that level is maintained. remark n = 0, 1 01h n feh 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 375 jul 15, 2010 figure 9-10. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h 00h 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn interval time remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 376 jul 15, 2010 9.4.2 operation as pwm output in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. the 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). rewriting the cmp0n register during timer operation is prohibited. the 8-bit timer compare register 1n (cmp 1n) controls the duty of timer output (t ohn). rewriting the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. pwm output (tohn output) out puts an active level and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. pwm output (tohn out put) outputs an inactive level when 8-bit timer counter hn and the cmp1n register match. setting <1> set each register. figure 9-11. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled default setting of timer output level pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare re gister that is to be compared first afte r counter operation is enabled. when the values of the 8-bit timer counter hn and the cmp0n register match, the 8- bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and an ac tive level is output. at the same time, the compare register to be compared with the 8- bit timer counter hn is changed from the cmp0n register to the cmp1n register. <4> when the 8-bit timer counter hn and the cmp1n regist er match, an inactive level is output and the compare register to be compared with the 8- bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, the 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 377 jul 15, 2010 <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp 1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. ? pwm pulse output cycle = (n + 1)/f cnt ? duty = (m + 1)/(n + 1) cautions 1. the set value of the cmp1n register can be changed while the time r counter is operating. however, this takes a duration of three operating clocks (signal selected by the cksn2 to cksn0 bits of the tmhmdn register) fr om when the value of the cmp1 n register is changed until the value is transferred to the register. 2. be sure to set the cmp1n re gister when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (b e sure to set again even if setting the same value to the cmp1n register). 3. make sure that the cmp1n register setting val ue (m) and cmp0n regist er setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for details on how to enable the inttmhn signal interrupt, see chapter 20 interrupt functions . 3. n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 378 jul 15, 2010 figure 9-12. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start the 8-bit time r counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> when the values of the 8-bit timer c ounter hn and the cmp0n register match, an active level is output. at this time, the value of the 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of the 8-bit timer counter hn and the cm p1n register match, an inactive level is output. at this time, the 8-bit timer counter value is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operation se ts the inttmhn signal to the default and pwm output to an inactive level. remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 379 jul 15, 2010 figure 9-12. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 380 jul 15, 2010 figure 9-12. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 381 jul 15, 2010 figure 9-12. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 02h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmp11 <6> <5> 02h a5h 03h 02h (03h) <2> 80h <1> the count operation is enabled by setting tmhen = 1. start the 8-bit timer counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> the cmp1n register value can be changed during timer count er operation. this operatio n is asynchronous to the count clock. <3> when the values of the 8-bit timer counter hn and the cmp0n register match, the value of the 8-bit timer counter hn is cleared, an active level is output, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is la tched and not transferred to the register. when the values of the 8-bit timer counter hn and t he cmp1n register before the change matc h, the value is transferred to the cmp1n register and the cmp1n register value is changed (<2>?. however, three count clocks or more are required from when the cmp1n register va lue is changed to when the value is transferred to the register. if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> when the values of the 8-bit timer counter hn and the cm p1n register after the change match, an inactive level is output. the 8-bit timer counter hn is not cl eared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operation se ts the inttmhn signal to the default and pwm output to an inactive level. remark n = 0, 1 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 382 jul 15, 2010 9.4.3 carrier generator opera tion (8-bit timer h1 only) in the carrier generator mode, the 8-bit timer h1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generat e an infrared remote control signal (time count). the carrier clock generated by the 8-bit timer h1 is output in the cycle set by the 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is out put from the toh1 output. (1) carrier generation in carrier generator mode, the 8-bit timer h compare regi ster 01 (cmp01) generates a low-level width carrier pulse waveform and the 8-bit timer h compare register 11 (cmp11 ) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during the 8-bit timer h1 o peration is possible but rewriting the cmp01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request signal (inttm51) of the 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier control r egister (tmcyc1). the relati onship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output at rising edge of inttm51 signal input 1 0 low-level output 1 1 carrier pulse output at rising edge of inttm51 signal input 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 383 jul 15, 2010 to control the carrier pulse output dur ing a count operation, the nrz1 and nrzb1 bits of t he tmcyc1 register have a master and slave bit configuration. the nrz1 bit is read-only but the nrz b1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 c ount clock and is output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrzb1 bit to the nrz1 bit is as shown below. figure 9-13. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <3> <1> the inttm51 signal is synchronized with the count clock of the 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is transferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. <3> write the next value to the nrzb1 bit in the interrupt servicing program that has been started by the inttm5h1 interrupt or after timing has been checked by polling the inte rrupt request flag. write data to count the next time to the cr51 register. cautions 1. do not rewrite the nrzb1 bit again until at least the second clo ck after it has been rewritten, or else the transfer from the nrzb1 bit to the nrz1 bit is not guaranteed. 2. when the 8-bit time r/event counter 51 is used in the carri er generator mode, an interrupt is generated at the timing of <1>. when the 8-bi t timer/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs. remark inttm5h1 is an internal signal and not an interrupt source. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 384 jul 15, 2010 setting <1> set each register. figure 9-14. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled default setting of timer output level carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? see 8.3 registers controlling 8-bit timer/event counters 50 and 51 . <2> when tmhe1 = 1, the 8-bit timer h1 starts counting. <3> when tce51 of the 8-bit timer mode control register 51 (tmc51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first compare register to be co mpared is the cmp01 register. when the count value of the 8-bit timer counter h1 and t he cmp01 register value match, the inttmh1 signal is generated, the 8-bit timer counter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. <5> when the count value of the 8-bit timer counter h1 and the cmp11 register value match, the inttmh1 signal is generated, the 8-bit timer counter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> r epeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with count clock of the 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> write the next value to the nrzb1 bit in the interrupt servicing program that has been started by the inttm5h1 interrupt or after timing has been checked by polling the in terrupt request flag. write dat a to count the next time to the cr51 register. <9> when the nrz1 bit is high level, a carrier clock is output by toh1 output. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 385 jul 15, 2010 <10> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, clear tmhe1 to 0. if the setting value of the cmp01 register is n, the setti ng value of the cmp11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. ? carrier clock output cycle = (n + m + 2)/f cnt ? duty = high-level width/carrier cl ock output width = (m + 1)/(n + m + 2) cautions 1. be sure to set the cmp11 register wh en starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. 3. set the values of the cmp01 and cmp 11 registers in a range of 01h to ffh. 4. the set value of the cmp11 register can be changed while the timer counter is operating. however, it takes the duration of three opera ting clocks (signal selected by the cks12 to cks10 bits of the tmhmd1 register) since the value of the cmp11 register has been changed until the value is tr ansferred to the register. 5. be sure to set the rmc1 bit be fore the count operation is started. remarks 1. for the setting of the output pin, see 9.3 (3) port mode register 1 (pm1) . 2. for how to enable the inttmh1 signal interrupt, see chapter 20 interrupt functions . 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 386 jul 15, 2010 figure 9-15. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n cmp01 cmp11 tmhe11 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm51 count value cr5 1 tce5 1 toh 1 0 0 1 1 0 0 1 1 0 0 inttm5 1 nrzb 1 nrz 1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h 1 <1><2> <3> <4> <5> <6> <7> 8-bit timer h1 count clock 8-bit timer counter h1 count value k l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at t hat time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 ma tches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level. remark inttm5h1 is an internal signal and not an interrupt source. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 387 jul 15, 2010 figure 9-15. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n cmp01 cmp11 tmhe1 inttmh1 carrier clock tm51 count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce51 toh1 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h1 <1><2> <3> <4> <5> <6> <7> 8-bit timer 51 count clock 8-bit timer h1 count clock 8-bit timer counter h1 count value k cr51 l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at t hat time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 ma tches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 out put is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). remark inttm5h1 is an internal signal and not an interrupt source. 78k0/kx2 chapter 9 8-bit timers h0 and h1 r01uh0008ej0401 rev.4.01 388 jul 15, 2010 figure 9-15. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3> <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, the 8-bit timer h1 starts a c ount operation. at that time , the carrier clock remains default. <2> when the count value of the 8-bit timer counter h1 matches the value of the cm p01 register, the inttmh1 signal is output, the carrier signal is inverted, and the time r counter is cleared to 00h. at the same time, the compare register whose value is to be compared with t hat of the 8-bit timer count er h1 is changed from the cmp01 register to the cmp11 register. <3> the cmp11 register is asynchronous to the count clock, and its value c an be changed while the 8-bit timer h1 is operating. the new value (l) to which the value of the r egister is to be changed is latched. when the count value of the 8-bit timer counter h1 matches the value (m) of the cmp11 register before the change, the cmp11 register is changed (<3>?. however, it takes three count clocks or more since t he value of the cmp11 regist er has been changed until the value is transferred to the register. even if a match si gnal is generated before the dur ation of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter h1 matches the value (m) of the cmp1 register before the change, the inttmh1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter h1 is changed from the cmp11 register to the cmp01 register. <5> the timing at which the count value of the 8-bit timer counter h1 and the cmp11 register value match again is indicated by the value after the change (l). 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 389 jul 15, 2010 chapter 10 watch timer 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 watch timer ? remark : mounted, ? : not mounted 10.1 functions of watch timer the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. block diagram of watch timer f prs /2 7 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f sub intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 f w clear 11-bit prescaler clear 5-bit counter watch timer operation mode register (wtm) internal bus selector selector selector selector f wx /2 4 f wx /2 5 f wx remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) f wx : f w or f w /2 9 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 390 jul 15, 2010 (1) watch timer when the peripheral hardware clock or subsystem clock is used, interrupt request si gnals (intwt) are generated at preset intervals. table 10-1. watch timer interrupt time interrupt time when operated at f sub = 32.768 khz when operated at f prs = 2 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 2 5 /f w 977 s 2.05 ms 819 s 410 s 205 s 2 13 /f w 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 2 14 /f w 0.5 s 1.05 s 0.419 s 0. 210 s 0.105 s remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) (2) interval timer interrupt request signals (intwti) are generated at preset time intervals. table 10-2. interval timer interval time interval time when operated at f sub = 32.768 khz when operated at f prs = 2 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 2 5 /f w 977 s 2.05 ms 820 s 410 s 205 s 2 6 /f w 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 2 7 /f w 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 2 8 /f w 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 2 9 /f w 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 2 10 /f w 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 2 11 /f w 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 391 jul 15, 2010 10.2 configuration of watch timer the watch timer includes the following hardware. table 10-3. watch timer configuration item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) 10.3 register controlling watch timer the watch timer is controlled by the wa tch timer operation mode register (wtm). ? watch timer operation mode register (wtm) this register sets the watch timer count clock, enables/dis ables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears wtm to 00h. 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 392 jul 15, 2010 figure 10-2. format of watch timer operation mode register (wtm) address: ff6fh after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 watch timer count clock selection (f w ) note wtm7 f sub = 32.768 khz f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 f prs /2 7 ? 15.625 khz 39.062 khz 78.125 khz 156.25 khz 1 f sub 32.768 khz ? wtm6 wtm5 wtm4 prescaler interval time selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 9 /f w 1 1 0 2 10 /f w 1 1 1 2 11 /f w wtm3 wtm2 selection of watch timer interrupt time 0 0 2 14 /f w 0 1 2 13 /f w 1 0 2 5 /f w 1 1 2 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear bot h prescaler and 5-bit counter) 1 operation enable note the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 393 jul 15, 2010 caution do not change the count clock and interval ti me (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 394 jul 15, 2010 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request signal (intwt) at a specific time interval by using the peripheral hardware clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1, the count operation starts. when these bits are cleared to 0, t he 5-bit counter is cleared an d the count operation stops. when the interval timer is simultaneously operated, zero-s econd start can be achieved only for the watch timer by clearing wtm1 to 0. in this case, however, the 11-bit prescaler is not cleared. therefore, an error up to 2 9 1/f w seconds occurs in the first overflow (intwt) after zero-second start. the interrupt request is generated at the following time intervals. table 10-4. watch timer interrupt time wtm3 wtm2 interrupt time selection when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 2 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 2 14 /f w 0.5 s 1.05 s 0.419 s 0. 210 s 0.105 s 0 1 2 13 /f w 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 1 0 2 5 /f w 977 s 2.05 ms 819 s 410 s 205 s 1 1 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt request signals (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer oper ation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count operati on starts. when this bit is set to 0, the count operation stops. table 10-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 2 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 0 2 4 /f w 488 s 1.02 ms 410 s 205 s 102 s 0 0 1 2 5 /f w 977 s 2.05 ms 820 s 410 s 205 s 0 1 0 2 6 /f w 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 0 1 1 2 7 /f w 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 1 0 0 2 8 /f w 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 1 0 1 2 9 /f w 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 1 1 0 2 10 /f w 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 1 1 1 2 11 /f w 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency 78k0/kx2 chapter 10 watch timer r01uh0008ej0401 rev.4.01 395 jul 15, 2010 figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) remark f w : watch timer clock frequency figures in parentheses are for operation with f w = 32.768 khz (wtm7 = 1, wtm3, wtm2 = 0, 0) 10.5 cautions for watch timer when operation of the watch timer and 5- bit counter is enabled by the watch ti mer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the interval until the first interrupt reques t signal (intwt) is generated after the register is set does not exac tly match the specification made with bits 2 and 3 (wtm2, wtm3) of wtm. subsequently, however, the intwt signal is generated at the specified intervals. figure 10-4. example of generation of watc h timer interrupt request signal (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 396 jul 15, 2010 chapter 11 watchdog timer 11.1 functions of watchdog timer the watchdog timer is mounted onto all 78k0/kx2 microcontroller products. the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program l oop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period ? if the instruction is fetched from an ar ea not set by the ims and ixs registers ( detection of an invalid check while the cpu hangs up) ? if the cpu accesses an area that is not set by the im s and ixs registers (excluding fb00h to ffcfh and ffe0h to ffffh) by executing a read/write inst ruction (detection of an abnormal access during a cpu program loop) when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 23 reset function . 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 397 jul 15, 2010 11.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 11-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow ti me, and window open period are set by the option byte. table 11-2. setting of op tion bytes and watchdog timer setting of watchdog timer option byte (0080h) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) remark for the option byte, see chapter 26 option byte . figure 11-1. block diag ram of watchdog timer f rl /2 clock input controller reset output controller internal reset signal internal bus selector 17-bit counter 2 10 /f rl to 2 17 /f rl watchdog timer enable register (wdte) clear, reset control wdton of option byte (0080h) window1 and window0 of option byte (0080h) count clear signal wdcs2 to wdcs0 of option byte (0080h) overflow signal cpu access signal cpu access error detector window size determination signal 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 398 jul 15, 2010 11.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 11-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (0080h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however , an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)). 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 399 jul 15, 2010 11.4 operation of watchdog timer 11.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (0080h). ? enable counting operation of the watchdog timer by setti ng bit 4 (wdton) of the opti on byte (0080h) to 1 (the counter starts operating after a re set release) (for details, see chapter 26 ). wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped after rese t), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h) (for details, see 11.4.2 and chapter 26 ). ? set a window open period by using bits 6 and 5 (wi ndow1 and window0) of the opt ion byte (0080h) (for details, see 11.4.3 and chapter 26 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer star ts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. after that, write wdte the second time or later a fter a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. a internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if the instruction is fetched from an area not set by the ims and ixs registers (det ection of an invalid check during a cpu program loop) ? if the cpu accesses an area not set by the ims and i xs registers (excluding fb00h to ffcfh and ffe0h to ffffh) by executing a read/write inst ruction (detection of an abnormal access during a cpu program loop) cautions 1. the first writing to wd te after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of th e writing, and the watc hdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. 3. the watchdog timer can be cleared immediately before the count value overflows (ffffh). 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 400 jul 15, 2010 cautions 4. the operation of th e watchdog timer in the halt and stop modes differs as follows depending on the set value of bit 0 (lsrosc) of the option byte. lsrosc = 0 (internal low-speed oscillator can be stopped by software) lsrosc = 1 (internal low-speed oscillator cannot be stopped) in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if lsrosc = 0, the watchdog timer resumes counting after the hal t or stop mode is released. at this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed oscilla tor is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. 5. the watchdog timer continues its operation during self-programming a nd eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledg e time is delayed. set the overflow time and window size taki ng this delay into consideration. 11.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h). if an overflow occurs, an internal reset signal is generated. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte during the window open period before the overflow time. the following overflow time is set. table 11-3. setting of over flow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) cautions 1. the combination of wdcs2 = w dcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its op eration during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 401 jul 15, 2010 11.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, wi ndow0) of the option byte (0080h). the outline of t he window is as follows. ? if ?ach? is written to wdte during the window open period, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window clos e period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ach is written to wdte. internal reset signal is generated if ach is written to wdte. caution the first writing to wdte afte r a reset release clears the watchdog timer, if it is made before the overflow time regardless of the ti ming of the writing, and the watchdog timer starts counting again. the window open period to be set is as follows. table 11-4. setting window open period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the combination of wdcs2 = w dcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. setting window1 = window0 = 0 is prohi bited when using the watchdog timer at 1.8 v v dd < 2.7 v. 3. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. 78k0/kx2 chapter 11 watchdog timer r01uh0008ej0401 rev.4.01 402 jul 15, 2010 remark if the overflow time is set to 2 11 /f rl , the window close time and open time are as follows. (when 2.7 v v dd 5.5 v) setting of window open period 25% 50% 75% 100% window close time 0 to 7.11 ms 0 to 4.74 ms 0 to 2.37 ms none window open time 7.11 to 7.76 ms 4.74 to 7.76 ms 2.37 to 7.76 ms 0 to 7.76 ms 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 403 jul 15, 2010 chapter 12 clock output/buzzer output controller 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 clock output ? 38/44 pins: ? 48 pins: buzzer output ? remark : mounted, ? : not mounted 12.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier outpu t during remote controlled transmission and clock output for supply to peripheral ics. the clock selected with t he clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 12-1 and 12-2 show the block diagram of clock output/buzzer output controller. figure 12-1. block diagram of clo ck output/buzzer output controller (78k0/kd2, 48-pin products of 78k0/kc2) cloe 8 pcl/intp6/p140 clock controller prescaler internal bus ccs3 clock output select register (cks) ccs2 ccs1 ccs0 output latch (p140) pm140 selector f prs f prs to f prs /2 7 f sub 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 404 jul 15, 2010 figure 12-2. block diagram of clock output/buzzer output c ontroller (78k0/ke2, 78k0/kf2) f prs f prs /2 10 to f prs /2 13 f prs to f prs /2 7 f sub bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/intp6/p140 buz/busy0/intp7/p141 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p141) pm141 output latch (p140) pm140 selector selector 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 12-1. configuration of clock output/buzzer output controller item configuration control registers clock output selection register (cks) port mode register 14 (pm14) port register 14 (p14) 12.3 registers controlling clock ou tput/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 14 (pm14) (1) clock output selection register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears cks to 00h. 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 405 jul 15, 2010 figure 12-3. format of clock output selection re gister (cks) (78k0/kd2, 48-pin products of 78k0/kc2) address: ff40h after reset: 00h r/w symbol 7 6 5 <4> 3 2 1 0 cks 0 0 0 cloe ccs3 ccs2 ccs1 ccs0 cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. pcl output clock selection note 1 ccs3 ccs2 ccs1 ccs0 f sub = 32.768 khz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note 2 10 mhz setting prohibited note 3 0 0 0 1 f prs /2 5 mhz 10 mhz 0 0 1 0 f prs /2 2 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 312.5 khz 625 khz 0 1 1 0 f prs /2 6 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 ? 78.125 khz 156.25 khz 1 0 0 0 f sub 32.768 khz ? other than above setting prohibited notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 v v dd < 2.7 v, setting ccs3 = ccs2 = ccs1 = ccs 0 = 0 (output clock of pcl: f prs ) is prohibited. 3. the pcl output clock prohibits settings if they exceed 10 mhz. caution set ccs3 to ccs0 while the clo ck output operation is stopped (cloe = 0). remarks 1. f prs : peripheral hardware clock frequency 2. f sub : subsystem clock frequency 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 406 jul 15, 2010 figure 12-4. format of clock output select ion register (cks) (78k0/ke2, 78k0/kf2) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. buz output clock selection note 1 bcs1 bcs0 f prs = 10 mhz f prs = 20 mhz 0 0 f prs /2 10 9.77 khz 19.54 khz 0 1 f prs /2 11 4.88 khz 9.77 khz 1 0 f prs /2 12 2.44 khz 4.88 khz 1 1 f prs /2 13 1.22 khz 2.44 khz cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. pcl output clock selection note 1 ccs3 ccs2 ccs1 ccs0 f sub = 32.768 khz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note 2 10 mhz setting prohibited note 3 0 0 0 1 f prs /2 5 mhz 10 mhz 0 0 1 0 f prs /2 2 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 312.5 khz 625 khz 0 1 1 0 f prs /2 6 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 ? 78.125 khz 156.25 khz 1 0 0 0 f sub 32.768 khz ? other than above setting prohibited notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 407 jul 15, 2010 notes 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (xsel = 0) when 1.8 v v dd < 2.7 v, setting ccs3 = ccs2 = ccs1 = ccs0 = 0 (output clock of pcl: f prs ) is prohibited. 3. the pcl output clock prohibits settings if they exceed 10 mhz. cautions 1. set bcs1 and bcs0 when the bu zzer output operation is stopped (bzoe = 0). 2. set ccs3 to ccs0 while the clock output operation is stopped (cloe = 0). remarks 1. f prs : peripheral hardware clock frequency 2. f sub : subsystem clock frequency (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pcl pin for clock output and the p141/intp7/busy0/buz pin for buzzer output, clear pm140 and pm141 and the output latches of p140 and p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm14 to ffh. figure 12-5. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 pm145 pm144 pm143 pm142 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) remark the figure shown above presents the format of port mode register 14 of 78k0/kf2 products. for the format of port mode register 14 of other products, see (1) port mode registers (pmxx) in 5.3 registers controlling port function . 78k0/kx2 chapter 12 clock output/buzzer output controller r01uh0008ej0401 rev.4.01 408 jul 15, 2010 12.4 operations of clock output/buzzer output controller 12.4.1 operation as clock output the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the cloc k output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is des igned not to output pulses with a small width during output enable/disable switching of the clock output. as s hown in figure 12-6, be sure to star t output from the low period of the clock (marked with * in the figure). when stopping outpu t, do so after the high-level period of the clock. figure 12-6. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the cl ock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 409 jul 15, 2010 chapter 13 a/d converter 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 10-bit a/d converter 4 ch 38 pins: 6 ch 44/48 pins: 8 ch 8 ch 13.1 function of a/d converter the a/d converter converts an analog input signal into a digi tal value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly fo r one analog input channel selected from ani0 to ani7. each time an a/d conversion operation ends, an interrupt request (intad) is generated. figure 13-1. block diag ram of a/d converter av ref av ss intad adcs bit adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator a/d converter mode register (adm) internal bus 3 ads2 ads1 ads0 analog input channel specification register (ads) ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 controller a/d conversion result register (adcr) successive approximation register (sar) lv1 lv0 5 a/d port configuration register (adpc) adpc3 adpc2 adpc1 adpc0 4 selector tap selector remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 410 jul 15, 2010 13.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani7 pins these are the analog input pins of the 8-channel a/d converter. they input analog signals to be converted into digital signals. pins other than the o ne selected as the analog input pin can be used as i/o port pins. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above (2) sample & hold circuit the sample & hold circuit samples the input voltage of the analog input pin selected by the selector when a/d conversion is started, and holds the samp led voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the sampled voltage value. figure 13-2. circuit configuration of series resistor string adcs series resistor string av ref p-ch av ss (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, star ting from the most significant bit (msb). when the voltage value is converted into a digital value down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transferred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to this register each time a/d conversion is completed, and the adcr regi ster holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 411 jul 15, 2010 (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to this register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. caution when data is read from adcr and adcrh, a wait cycle is generated. do not read data from adcr and adcrh when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. (8) controller this circuit controls the conversion time of an input analog si gnal that is to be converted into a digital signal, as well as starting and stopping of the conver sion operation. when a/d conversion has been completed, this controller generates intad. (9) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. make this pin the same potential as the v dd pin when port 2 is used as a digital port. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pi n of the a/d converter. always use this pi n at the same potential as that of the v ss pin even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conv ersion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. (13) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) port mode register 2 (pm2) this register switches the ani0/p20 to ani7/p27 pins to input or output. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 412 jul 15, 2010 13.3 registers used in a/d converter the a/d converter uses the following six registers. ? a/d converter mode register (adm) ? a/d port configuration register (adpc) ? analog input channel specification register (ads) ? port mode register 2 (pm2) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-3. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: ff28h after reset: 00h r/w symbol comparator operation control note 2 stops comparator operation enables comparator operation adce 0 1 notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 13-2 a/d conversion time selection (conventional-specification products ( pd78f05xx and 78f05xxd)) , and table 13-3 a/d conversion time selection (exp anded-specification products ( pd78f05xxa and 78f05xxda)) . 2. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. therefore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. table 13-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (comparator oper ation, only comparator consumes power) 1 0 conversion mode (comparator operation stopped note ) 1 1 conversion mode (comparator operation) note ignore the first conversion data. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 413 jul 15, 2010 figure 13-4. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the fallin g of the adcs bit must be 1 s or longer. cautions 1. a/d conversion must be stopped before rewriting bits fr0 to fr2, lv1, and lv0 to values other than the identical data. 2. if data is written to adm, a wait cycle is genera ted. do not write data to adm when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 414 jul 15, 2010 table 13-2. a/d conversion time selection (conventional-specification products ( pd78f05xx and 78f05xxd)) (1) 2.7 v av ref 5.5 v (lv0 = 0) a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 10 mhz f prs = 20 mhz note conversion clock (f ad ) 0 0 0 0 0 264/f prs 26.4 s 13.2 s note f prs /12 0 0 1 0 0 176/f prs 17.6 s 8.8 s note f prs /8 0 1 0 0 0 132/f prs 13.2 s 6.6 s note f prs /6 0 1 1 0 0 88/f prs setting prohibited 8.8 s note f prs /4 1 0 0 0 0 66/f prs 33.0 s 6.6 s note f prs /3 1 0 1 0 0 44/f prs 22.0 s setting prohibited setting prohibited f prs /2 other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. (2) 2.3 v av ref < 2.7 v (lv0 = 1) a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz conversion clock (f ad ) 0 0 0 0 1 480/f prs setting prohibited f prs /12 0 0 1 0 1 320/f prs 64.0 s f prs /8 0 1 0 0 1 240/f prs 48.0 s f prs /6 0 1 1 0 1 160/f prs setting prohibited 32.0 s f prs /4 1 0 0 0 1 120/f prs 60.0 s setting prohibited f prs /3 1 0 1 0 1 80/f prs 40.0 s setting prohibited f prs /2 other than above setting prohibited cautions 1. set the conversion ti mes with the following conditions. ? 4.0 v av ref 5.5 v: f ad = 0.6 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.6 to 1.8 mhz ? 2.3 v av ref < 2.7 v: f ad = 0.6 to 1.48 mhz (standard produc ts and (a) grade products only) 2. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time do es not include clock frequency e rrors. select conversion time, taking clock frequency erro rs into consideration. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 415 jul 15, 2010 table 13-3. a/d conversion time sel ection (expanded-specification products ( pd78f05xxa and 78f05xxda)) (1) 2.7 v av ref 5.5 v (lv0 = 0) a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz conversion clock (f ad ) 0 0 0 0 0 264/f prs 52.8 s 26.4 s 13.2 s f prs /12 0 0 1 0 0 176/f prs setting prohibited 35.2 s 17.6 s 8.8 s note f prs /8 0 1 0 0 0 132/f prs 66.0 s 26.4 s 13.2 s 6.6 s note f prs /6 0 1 1 0 0 88/f prs 44.0 s 17.6 s 8.8 s note f prs /4 1 0 0 0 0 66/f prs 33.0 s 13.2 s 6.6 s note f prs /3 1 0 1 0 0 44/f prs 22.0 s 8.8 s note setting prohibited setting prohibited f prs /2 other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. (2) 2.3 v av ref 5.5 v (lv0 = 1) a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz conversion clock (f ad ) 0 0 0 0 1 480/f prs setting prohibited 48.0 s note 2 24.0 s note 2 f prs /12 0 0 1 0 1 320/f prs 64.0 s 32.0 s note 2 16.0 s note 1 f prs /8 0 1 0 0 1 240/f prs 48.0 s 24.0 s note 2 12.0 s note 1 f prs /6 0 1 1 0 1 160/f prs setting prohibited 32.0 s 16.0 s note 1 f prs /4 1 0 0 0 1 120/f prs 60.0 s 24.0 s note 2 12.0 s note 1 f prs /3 1 0 1 0 1 80/f prs 40.0 s 16.0 s note 1 setting prohibited setting prohibited f prs /2 other than above setting prohibited notes 1. this can be set only when 4.0 v av ref 5.5 v. 2. this can be set only when 2.7 v av ref 5.5 v. cautions 1. set the conversion ti mes with the following conditions. (1) 2.7 v av ref 5.5 v (lv0 = 0) ? 4.0 v av ref 5.5 v: f ad = 0.33 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.33 to 1.8 mhz (2) 2.3 v av ref 5.5 v (lv0 = 1) ? 4.0 v av ref 5.5 v: f ad = 0.6 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.6 to 1.8 mhz ? 2.3 v av ref < 2.7 v: f ad = 0.6 to 1.48 mhz (standard produc ts and (a) grade products only) 2. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time do es not include clock frequency e rrors. select conversion time, taking clock frequency erro rs into consideration. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 416 jul 15, 2010 figure 13-5. a/d converter sa mpling and a/d conversion timing adcs wait period note conversion time conversion time sampling sampling timing intad adcs 1 or ads rewrite sampling sar clear sar clear transfer to adcr, intad generation successive conversion note for details of wait period, see chapter 36 cautions for wait . (2) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that st ores the a/d conversion result. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. the higher 8 bits of the conversion result are stored in ff09h and the lower 2 bits are stored in the higher 2 bits of ff08h. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 13-6. format of 10-bit a/d conversion result register (adcr) symbol address: ff08h, ff09h after reset: 0000h r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration re gister (adpc), the cont ents of adcr may become undefined. read the conversion result following conversion completion before writing to adm, ads, and adpc. using timing other than the abo ve may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is generated. do not read data from adcr when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 417 jul 15, 2010 (3) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that st ores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: ff09h after reset: 00h r 76543210 cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration regi ster (adpc), the contents of adcrh may become undefined. read the conversion result following conversion completion before writing to adm, ads, and adpc. using timing other than the abo ve may cause an incorrect conversion result to be read. 2. if data is read from adcrh, a wait cycle is generated. do not read data from adcrh when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 418 jul 15, 2010 (4) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above figure 13-8. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol kb2 38-pin products of kc2 products other than the right note 1 note 1 note 2 note 1 note 2 notes 1. setting permitted 2. setting prohibited cautions 1. be sure to cl ear bits 3 to 7 to ?0?. 2 set a channel to be used for a/d conversion in the input mode by using port mode register 2 (pm2). 3. if data is written to ads, a wait cycle is genera ted. do not write data to ads when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 419 jul 15, 2010 (5) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above figure 13-9. format of a/d port configuration register (adpc) adpc0 adpc1 adpc2 adpc3 0 0 0 0 digital i/o (d)/analog input (a) switching setting prohibited adpc3 0 1 2 3 4 5 6 7 adpc address: ff2fh after reset: 00h r/w symbol p27/ ani7 a a a a a a a a d p26/ ani6 a a a a a a a d d p25/ ani5 a a a a a a d d d p24/ ani4 a a a a a d d d d p23/ ani3 a a a a d d d d d p22/ ani2 a a a d d d d d d p21/ ani1 a a d d d d d d d p20/ ani0 a d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc2 0 0 0 0 1 1 1 1 0 adpc1 0 0 1 1 0 0 1 1 0 adpc0 0 1 0 1 0 1 0 1 0 other than above kb2 38-pin products of kc2 products other than the right note 1 note 1 note 2 note 1 note 2 notes 1. setting permitted 2. setting prohibited cautions 1. set a channel to be u sed for a/d conversion in the input mo de by using port mode register 2 (pm2). 2. if data is written to adpc, a wait cycle is generated. do not write data to adpc when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 420 jul 15, 2010 (6) port mode register 2 (pm2) when using the ani0/p20 to ani7/p27 pins for analog input por t, set pm20 to pm27 to 1. the output latches of p20 to p27 at this time may be 0 or 1. if pm20 to pm27 are set to 0, they cannot be used as analog input port pins. pm2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above figure 13-10. format of port mode register 2 (pm2) pm20 pm21 pm22 pm23 pm24 pm25 pm26 pm27 p2n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm2n 0 1 0 1 2 3 4 5 6 7 pm2 address: ff22h after reset: ffh r/w symbol caution for the 38-pin products of 78 k0/kc2, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. remark the format of port mode register 2 of 78k0/kb2 products is diffe rent from the above format. see 5.3 registers controlling port function (1) port mode registers (pmxx) . ani0/p20 to ani7/p27 pins are as shown below depending on the settings of adpc, ads, and pm2. table 13-4. setting functions of ani0/p20 to ani7/p27 pins adpc pm2 ads ani0/p20 to ani7/p27 pins selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited input mode ? digital input digital i/o selection output mode ? digital output 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 421 jul 15, 2010 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1 to start the operation of the comparator. <2> set channels for a/d conversion to analog input by us ing the a/d port configuration register (adpc) and set to input mode by using port mode register 2 (pm2). <3> set a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select one channel for a/d conversion using the analog input channel specification register (ads). <5> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<6> to <12> are operations performed by hardware.) <6> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <7> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <8> bit 9 of the successive approximation register (sar) is set. the series resistor stri ng voltage tap is set to (1/2) av ref by the tap selector. <9> the voltage difference between the se ries resistor string voltage tap and sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <10> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <11> comparison is continued in this way up to bit 0 of sar. <12> upon completion of the comparison of 10 bits, an effe ctive digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <13> repeat steps <6> to <12>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the status of adce = 1, start from <5>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <5>. to change a channel of a/d conversion, start from <4>. caution make sure the period of <1> to <5> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 422 jul 15, 2010 figure 13-11. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/ d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input channel specification register (ads ) during an a/d conversion operation, the conversion operation is init ialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation clears the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h. 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to t he analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the 10-bit a/d conversion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or ( ? 0.5) v ain < ( + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above v ain av ref av ref 1024 av ref 1024 adcr 64 adcr 64 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 423 jul 15, 2010 figure 13-12 shows the relationship between the analo g input voltage and the a/d conversion result. figure 13-12. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 424 jul 15, 2010 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode register (a dm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specified by the anal og input channel specification r egister (ads), is started. when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (int ad) is generated. when one a/d conversion has been completed, the next a/d conversion oper ation is immediately started. if ads is rewritten during a/d conver sion, the a/d conversion operation under execution is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conver sion is immediately stopped. at this time, the conversion result immediately before is retained. figure 13-13. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped conversion result immediately before is retained a/d conversion adcr, adcrh intad conversion is stopped conversion result immediately before is retained remarks 1. 78k0/kb2: n = 0 to 3, 38-pin products of the 78k0/ kc2: n = 0 to 5, other products: n = 0 to 7 2. 78k0/kb2: m = 0 to 3, 38-pin products of the 78k0/ kc2: m = 0 to 5, other products: m = 0 to 7 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 425 jul 15, 2010 the setting methods are described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> set the channel to be used in the analog input mode by using bits 3 to 0 (adpc3 to adpc0) of the a/d port configuration register (adpc) and bits 7 to 0 (p m27 to pm20) of port mode register 2 (pm2). <3> select conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select a channel to be used by using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads). <5> set bit 7 (adcs) of adm to 1 to start a/d conversion. <6> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <7> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 426 jul 15, 2010 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identifi ed. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (least significant bi t). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integr al linearity error, and differential linearit y errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital co de, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale erro r, integral linearity error, and differential linearity erro r in the characteristics table. figure 13-14. overall error figur e 13-15. quanti zation error ideal line 0 0 1 1 digital output overall error analog input av ref 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is gr eater than the theoretical value, it shows the difference between the actual measurement value of the analog inpu t voltage and the theoretical value (3/ 2lsb) when the digital output changes from 0001 to 0010. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 427 jul 15, 2010 (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual m easurement value and the ideal straight line when the zero- scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indicate s the difference between the ac tual measurement value and the ideal value. figure 13-16. zero-scale error figure 13-17. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 13-18. integral linearity error figure 13-19. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 1 0 0 0 av ref digital output analog input differential linearity error 1 1 0 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 428 jul 15, 2010 13.6 cautions for a/d converter (1) operating current in stop mode the a/d converter stops operati ng in the stop mode. at this time, the operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag regist er 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani7 observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an ana log input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read operati on, the new conversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh writ e and a/d converter mode register (adm) write, analog input channel specification register (ads), or a/ d port configuration register (adpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or a dcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani7. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 13-20 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 429 jul 15, 2010 figure 13-20. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 <1> the analog input pins (ani0 to ani7) ar e also used as i/o port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not access p20 to p27 while conversion is in progress; otherwise the conversion re solution may be degraded. it is recommended to select pins used as p20 to p27 starting with t he ani0/p20 that is the furthest from av ref . <2> if a digital pulse is applied to the pins adjacent to t he pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. consequently, the input impedanc e fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 10 k , and to connect a capacitor of about 100 pf to the ani0 to ani7 pins (see figure 13-20 ). (7) av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedanc e of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. remark ani0 to ani3: 78k0/kb2 ani0 to ani5: 38-pin products of the 78k0/kc2 ani0 to ani7: products other than above 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 430 jul 15, 2010 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel spec ification register (ads) is changed. therefore, if an analog in put pin is changed during a/d conversion, the a/d conversion result and adif for the pre- change analog input may be set just before the ads rewrite. caution is therefor e required since, at this time, when adif is read immediately after the ad s rewrite, adif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 13-21. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr, adcrh adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. 78k0/kb2: n = 0 to 3, 38-pin products of the 78k0/ kc2: n = 0 to 5, other products: n = 0 to 7 2. 78k0/kb2: m = 0 to 3, 38-pin products of the 78k0/ kc2: m = 0 to 5, other products: m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conversi on starts may not fall within the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if the adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d converter mode register (ad m), analog input channel specification register (ads), and a/d port conf iguration register (adpc), the c ontents of adcr and adcrh may become undefined. read the conversion result following conversi on completion before writing to adm, ads, and adpc. using a timing other than the above may cause an incorrect conversion result to be read. 78k0/kx2 chapter 13 a/d converter r01uh0008ej0401 rev.4.01 431 jul 15, 2010 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 13-22. internal equi valent circuit of anin pin anin c1 c2 r1 table 13-5. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 c1 c2 4.0 v av ref 5.5 v 8.1 k 8 pf 5 pf 2.7 v av ref < 4.0 v 31 k 8 pf 5 pf 2.3 v av ref < 2.7 v 381 k 8 pf 5 pf remarks 1. the resistance and capacitance values shown in table 13-5 are not guaranteed values. 2. 78k0/kb2: n = 0 to 3, 38-pin products of the 78k0/ kc2: n = 0 to 5, other products: n = 0 to 7 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 432 jul 15, 2010 chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 are mounted ont o all 78k0/kx2 microcontroller products. serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial communication is not execut ed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 14.4.2 asynchronous ser ial interface (uart) mode and 14.4.3 dedicated baud rate generator . ? maximum transfer rate: 625 kbps ? two-pin configuration t x d0: transmit data output pin r x d0: receive data input pin ? length of communication data can be selected from 7 or 8 bits. ? dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full-duplex operation). ? fixed to lsb-first communication cautions 1. if clock supply to serial interface ua rt0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to seria l interface uart0 is stopped (e.g., in the stop mode), each register stops opera ting, and holds the value immedi ately before clock supply was stopped. the t x d0 pin also holds the value immediat ely before clock supply was stopped and outputs it. however, the operation is not guarant eed after clock supply is resumed. therefore, reset the circuit so that power0 = 0, rxe0 = 0, and txe0 = 0. 2. set power0 = 1 and then set txe0 = 1 (tr ansmission) or rxe0 = 1 (reception) to start communication. 3. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two cl ocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 4. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 433 jul 15, 2010 14.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 14-1. configurati on of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface o peration mode register 0 (asim0) asynchronous serial interface recepti on error status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 1 (pm1) port register 1 (p1) 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 434 jul 15, 2010 figure 14-1. block diagram of serial interface uart0 intst0 intsr0 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) 8-bit timer/ event counter 50 output registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit output latch (p10) pm10 7 7 t x d0/ sck10/p10 r x d0/ si10/p11 f prs /2 5 f prs /2 3 f prs /2 f xclk0 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 435 jul 15, 2010 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data conv erted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is transferr ed to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the rece ive data is not transferred to rxb0. rxb0 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation and power0 = 0 set this register to ffh. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. txs0 can be written by an 8-bit memory manipulatio n instruction. this register cannot be read. reset signal generation, power0 = 0, and txe0 = 0 set this register to ffh. cautions 1. set transmit data to txs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 2. do not write the next transm it data to txs0 before the tran smission completion interrupt signal (intst0) is generated. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 436 jul 15, 2010 14.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following five registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 0 (asim0) this 8-bit register controls the serial comm unication operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception. notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status r egister 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 437 jul 15, 2010 figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface reception error status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power0 to 1 and then set txe0 to 1. to stop the transmission, clear txe0 to 0, and then clear power0 to 0. 2. to start the reception, set power0 to 1 and th en set rxe0 to 1. to stop the reception, clear rxe0 to 0, and then clear power0 to 0. 3. set power0 to 1 and then set rxe0 to 1 while a high level is input to th e rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 while a low level is input, reception is started. 4. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 6. clear the txe0 and rxe0 bits to 0 be fore rewriting the ps01, ps00, and cl0 bits. 7. make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. 8. be sure to set bit 0 to 1. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 438 jul 15, 2010 (2) asynchronous serial interface recepti on error status register 0 (asis0) this register indicates an error status on completion of rec eption by serial interface uart 0. it includes three error flag bits (pe0, fe0, ove0). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power0) or bit 5 (rxe0) of asim0 to 0 clears this register to 00h. 00h is read when this register is read. if a reception error o ccurs, read asis0 and then read receive buffer register 0 (rxb0) to clear the error flag. figure 14-3. format of asynchronous serial inte rface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 status flag indicating parity error 0 if power0 = 0 or rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 or rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb0 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operati on mode register 0 (asim0). 2. only the first bit of the rece ive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, th e next receive data is not written to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 439 jul 15, 2010 (3) baud rate generator c ontrol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. figure 14-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 base clock (f xclk0 ) selection note 1 tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 tm50 output note 2 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 setting prohibited 0 1 0 0 0 8 f xclk0 /8 0 1 0 0 1 9 f xclk0 /9 0 1 0 1 0 10 f xclk0 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 1 0 26 f xclk0 /26 1 1 0 1 1 27 f xclk0 /27 1 1 1 0 0 28 f xclk0 /28 1 1 1 0 1 29 f xclk0 /29 1 1 1 1 0 30 f xclk0 /30 1 1 1 1 1 31 f xclk0 /31 note 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 440 jul 15, 2010 note 2. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 fi rst and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 fi rst and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. cautions 1. make sure that bit 6 (t xe0) and bit 5 (rxe0) of the asim0 re gister = 0 when rewriting the mdl04 to mdl00 bits. 2. make sure that bit 7 (power0) of the asim0 register = 0 when rewrit ing the tps01 and tps00 bits. 3. the baud rate value is the output clock of the 5-bit c ounter divided by 2. remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f prs : peripheral hardware clock frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4. : don?t care 5. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 (4) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p10/txd0/sck10 pin for serial interface dat a output, clear pm10 to 0 and set the output latch of p10 to 1. when using the p11/rxd0/si10 pin for serial interface data input, set pm11 to 1. the output latch of p11 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 14-5. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 441 jul 15, 2010 14.4 operation of serial interface uart0 serial interface uart0 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 14.4.1 operation stop mode in this mode, serial communication cannot be executed, thus reducing the power consumptio n. in addition, the pins can be used as ordinary port pins in this mode. to set t he operation stop mode, clear bits 7, 6, and 5 (power0, txe0, and rxe0) of asim0 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status r egister 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. caution clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the communication, set power0 to 1, and then set txe0 or rxe0 to 1. remark to use the rxd0/si10/p11 and txd0/sck10/p 10 pins as general-purpose port pins, see chapter 5 port functions . 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 442 jul 15, 2010 14.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is in corporated, so that communication c an be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the brgc0 register (see figure 14-4 ). <2> set bits 1 to 4 (sl0, cl0, ps00, and ps01) of the asim0 register (see figure 14-2 ). <3> set bit 7 (power0) of the asim0 register to 1. <4> set bit 6 (txe0) of the asim0 register to 1. transmission is enabled. set bit 5 (rxe0) of the asim0 register to 1. reception is enabled. <5> write data to the txs0 register. data transmission is started. caution take relationship with the ot her party of communication when se tting the port mode register and port register. the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins pin function power0 txe0 rxe0 pm10 p10 pm11 p11 uart0 operation txd0/sck10/p10 rxd0/si10/p11 0 0 0 note note note note stop sck10/p10 si10/p11 0 1 note note 1 reception sck10/p10 rxd0 1 0 0 1 note note transmission txd0 si10/p11 1 1 1 0 1 1 transmission/ reception txd0 rxd0 note can be set as port function or serial interface csi10. remark : don?t care power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 pm1 : port mode register p1 : port output latch 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 443 jul 15, 2010 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. figure 14-6. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and st op bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (asim0). figure 14-7. example of normal uart transmit/receive data waveform 1. data length: 8 bits, parity: even pari ty, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity , stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, pa rity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 444 jul 15, 2010 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same ty pe of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no par ity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bi t, is controlled so that t he number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when t he data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 445 jul 15, 2010 (c) transmission if bit 7 (power0) of asynchronous serial interface operat ion mode register 0 (asim0) is set to 1 and bit 6 (txe0) of asim0 is then set to 1, transmission is enabled. tr ansmission can be started by writing transmit data to transmit shift register 0 (txs0). the start bit, parit y bit, and stop bit are automatically appended to the data. when transmission is started, the start bit is output from the t x d0 pin, and the transmit data is output followed by the rest of the data in order starti ng from the lsb. when transmission is completed, the parity and stop bits set by asim0 are appended and a transmission completi on interrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 14-8 shows the timing of the transmission completion in terrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 14-8. transmission comple tion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 446 jul 15, 2010 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator starts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 14-9). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, reception is started, and seri al data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the stop bit has been re ceived, the reception completion interrupt (intsr0) is generated and the data of rxs0 is writt en to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an reception error interrupt (intsr0) is generated after completion of reception. intsr0 occurs upon completion of reception and in case of a reception error. figure 14-9. reception completi on interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. if a reception error occurs, read asynchronous serial interface reception error status register 0 (asis0) and then read receive buffe r register 0 (rxb0) to clear the error flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1?. the second stop bit is ignored. 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 447 jul 15, 2010 (e) reception error three types of errors may occur during reception: a parity erro r, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status regist er 0 (asis0) is set as a result of data reception, a reception error interrupt (intsr0) is generated. which error has occurred during reception can be identified by reading the contents of asis0 in the reception error interrupt (intsr0) servicing (see figure 14-3 ). the contents of asis0 are cleared to 0 when asis0 is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of the ma tch detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-10. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 448 jul 15, 2010 14.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator contro l register 0 (brgc0) is supplied to each module when bit 7 (power0) of asynch ronous serial interface o peration mode register 0 (asim0) is 1. this clock is called the base clock and its frequency is called f xclk0 . the base clock is fixed to low level when power0 = 0. ? transmission counter this counter stops operation, cleared to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, cleared to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 14-11. configuration of baud rate generator f xclk0 selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 8-bit timer/ event counter 50 output f prs /2 5 f prs /2 f prs /2 3 baud rate generator remark power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 449 jul 15, 2010 (2) generation of serial clock a serial clock to be generated can be specified by usi ng baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value (f xclk0 /8 to f xclk0 /31) of the 5-bit counter. 14.4.4 calculation of baud rate (1) baud rate calculation expression the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk0 : frequency of base clock selected by the tps 01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of t he brgc0 register (k = 8, 9, 10, ..., 31) table 14-4. set value of tps01 and tps00 base clock (f xclk0 ) selection note 1 tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 tm50 output note 2 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. note the following points when sele cting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/ event counter 50 first and then set t he count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. f xclk0 2 k 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 450 jul 15, 2010 (2) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transm ission to within the permi ssible error range at the reception destination. 2. make sure that the baud rate error during r eception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] (3) example of setting baud rate table 14-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz f prs = 20.0 mhz baud rate [bps] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] tps01, tps00 k calculated value err [%] 4800 2h 26 4808 0.16 3h 16 4883 1.73 ? ? ? ? ? ? ? ? 9600 2h 13 9615 0.16 3h 8 9766 1.73 3h 16 9766 1.73 ? ? ? ? 10400 2h 12 10417 0.16 2h 30 10417 0.16 3h 15 10417 0.16 3h 30 10417 0.16 19200 1h 26 19231 0.16 2h 16 19531 1.73 3h 8 19531 1.73 3h 16 19531 1.73 24000 1h 21 23810 ? 0.79 2h 13 24038 0.16 2h 26 24038 0.16 3h 13 24038 0.16 31250 1h 16 31250 0 2h 10 31250 0 2h 20 31250 0 3h 10 31250 0 33600 1h 15 33333 ? 0.79 2h 9 34722 3.34 2h 19 32895 ? 2.1 3h 9 34722 3.34 38400 1h 13 38462 0.16 2h 8 39063 1.73 2h 16 39063 1.73 3h 8 39063 1.73 56000 1h 9 55556 ? 0.79 1h 22 56818 1.46 2h 11 56818 1.46 2h 22 56818 1.46 62500 1h 8 62500 0 1h 20 62500 0 2h 10 62500 0 2h 20 62500 0 76800 ? ? ? ? 1h 16 78125 1.73 2h 8 78125 1.73 2h 16 78125 1.73 115200 ? ? ? ? 1h 11 113636 ? 1.36 1h 22 113636 ? 1.36 2h 11 113636 ? 1.36 153600 ? ? ? ? 1h 8 156250 1.73 1h 16 156250 1.73 2h 8 156250 1.73 312500 ? ? ? ? ? ? ? ? 1h 8 312500 0 1h 16 312500 0 625000 ? ? ? ? ? ? ? ? ? ? ? ? 1h 8 625000 0 remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk0 )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f prs : peripheral hardware clock frequency err: baud rate error actual baud rate (baud rate with error) desired baud rate (correct baud rate) 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 451 jul 15, 2010 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within th e permissible error range, by using the calculation expression shown below. figure 14-12. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-12, the latch timing of the receive dat a is determined by the counter set by baud rate generator control register 0 (brgc0) after the start bit has been detect ed. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks 78k0/kx2 chapter 14 serial interface uart0 r01uh0008ej0401 rev.4.01 452 jul 15, 2010 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the trans mission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the permissible error of reception depends on the num ber of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 453 jul 15, 2010 chapter 15 serial interface uart6 15.1 functions of serial interface uart6 serial interface uart6 are mounted ont o all 78k0/kx2 microcontroller products. serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not execut ed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 15.4.2 asynchronous ser ial interface (uart) mode and 15.4.3 dedicated baud rate generator . ? maximum transfer rate: 625 kbps ? two-pin configuration t x d6: transmit data output pin r x d6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full duplex operation). ? msb- or lsb-first communication selectable ? inverted transmission operation ? sync break field transmission from 13 to 20 bits ? more than 11 bits can be identified for sync break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only the transmissi on side and not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to seria l interface uart6 is stopped (e.g., in the stop mode), each register stops opera ting, and holds the value immedi ately before clock supply was stopped. the t x d6 pin also holds the value immediat ely before clock supply was stopped and outputs it. however, the operation is not guarant eed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. 3. set power6 = 1 and then set txe6 = 1 (tr ansmission) or rxe6 = 1 (reception) to start communication. 4. txe6 and rxe6 are synch ronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission ci rcuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. if data is continuously tran smitted, the communication timing from the stop bit to the next start bit is extended two operati ng clocks of the macro. however, th is does not affect the result of communication because the recep tion side initializes the timing when it has detected a start bit. do not use the continuous tran smission function if the interf ace is used in lin communication operation. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 454 jul 15, 2010 remark lin stands for local interconnect network and is a lo w-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, actuators, and sensors, and these ar e connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method an d is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master tr ansmits a frame with baud rate informa tion and the slave receives it and corrects the baud rate error. theref ore, communication is possible when the baud rate error in the slave is 15% or less. figures 15-1 and 15-2 outline the transmissi on and reception operations of lin. figure 15-1. lin transmission operation lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission sync break field sync field identifier field data field data field checksum field tx6 (output) intst6 note 3 notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the sync break field is output by har dware. the output width is the bit length set by bits 4 to 2 (sbl62 to sbl60) of asynchronous serial interfac e control register 6 (asicl6) (see 15.4.2 (2) (h) sbf transmission ). 3. intst6 is output on completion of each transmissi on. it is also output when sbf is transmitted. remark the interval between each field is controlled by software. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 455 jul 15, 2010 figure 15-2. lin reception operation lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identifier field data field data field checksum field r x d6 (input) reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> reception processing is as follows. <1> the wakeup signal is detected at the edge of the pi n, and enables uart6 and sets the sbf reception mode. <2> reception continues until the stop bit is detected. when an sbf with low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if an sbf with low-level data of less than 11 bits has been det ected, it is assumed t hat an sbf reception error has occurred. the interrupt signal is not out put and the sbf reception mode is restored. <3> if sbf reception has been completed correctly, an interrupt signal is output. start 16-bit timer/event counter 00 by the sbf reception end interrupt se rvicing and measure the bit interval (pulse width) of the sync field (see 7.4.8 pulse width measurement operation ). detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of uart communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. <4> calculate the baud rate error from the bit interval of the sync field, disable uart6 after sf reception, and then re-set baud rate generator co ntrol register 6 (brgc6). <5> distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again. figure 15-3 shows the port configurat ion for lin reception operation. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0). the length of the sync field transmitted fr om the lin master can be measured usin g the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. the input source of the reception port input (r x d6) can be input to the external in terrupt (intp0) and 16-bit timer/event counter 00 by port input switch c ontrol (isc0/isc1), without connecting r x d6 and intp0/ti000 externally. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 456 jul 15, 2010 figure 15-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p14/rxd6 p120/intp0/exlvi p00/ti000 port input switch control (isc0) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 457 jul 15, 2010 15.2 configuration of serial interface uart6 serial interface uart6 includes the following hardware. table 15-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 458 jul 15, 2010 figure 15-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p13) pm13 8 selector t x d6/ p13 r x d6/ p14 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 note selectable with input switch control register (isc). 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 459 jul 15, 2010 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this regist er from rxs6. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. cautions 1. do not write data to txb6 when bit 1 (txbf6) of asynchronous seria l interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bits 7 and 6 (power6, txe6) of asynchr onous serial interface operation mode register 6 (asim6) are 1 or when bits 7 and 5 (power6, rxe6) of asim6 are 1). 3. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is writt en for the first transmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 460 jul 15, 2010 15.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. remark asim6 can be refreshed (the same value is writ ten) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of t he internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. if power6 = 0 is set while transmitting data, the out put of the txd6 pin will be fixed to high level (if txdlv6 = 0). furthermore, the input from the rxd6 pin will be fixed to high level. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 (sbrf6 ) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receiv e buffer register 6 (rxb6) are reset. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 461 jul 15, 2010 figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power6 to 1 and then set txe6 to 1. to stop the transmission, clear txe6 to 0, and then clear power6 to 0. 2. to start the reception, set power6 to 1 and th en set rxe6 to 1. to stop the reception, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 while a high level is input to the r x d6 pin. if power6 is set to 1 and rxe6 is set to 1 while a low level is input, reception is started. 4. txe6 and rxe6 are synchronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or rxe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or recepti on circuit may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 7. fix the ps61 and ps60 bits to 0 when used in lin communication operation. 8. clear txe6 to 0 before rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not aff ected by the set value of the sl6 bit. 9. make sure that rxe6 = 0 when rewriting the isrm6 bit. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 462 jul 15, 2010 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of rec eption by serial interface uart 6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bit 5 (rxe6) of asim6 to 0 clears this register to 00h. 00h is read when this register is read. if a reception error o ccurs, read asis6 and then read receive buffer register 6 (rxb6) to clear the error flag. figure 15-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb6 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. for the stop bit of the receive data, only the fi rst stop bit is checked regardless of the number of stop bits. 3. if an overrun error occurs, th e next receive data is not written to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 463 jul 15, 2010 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by serial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without di sruption even during an interrupt peri od, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bit 6 (txe6) of asim6 to 0 clears this register to 00h. figure 15-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data continu ously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next tr ansmit data (sec ond byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon completion of continuous transmission, be sure to check that the txsf6 flag is ?0? afte r generation of the transmission completion interrupt, and then execute initialization. if initia lization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 464 jul 15, 2010 figure 15-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection note 1 tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note 2 2 mhz 5 mhz 10 mhz 20 mhz note 3 0 0 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output note 4 other than above setting prohibited notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tps63 = tps 62 = tps61 = tps60 = 0 (base clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. 4. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit ti mer/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 465 jul 15, 2010 caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark brgc6 can be refreshed (the same value is writ ten) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 15-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk6 /4 0 0 0 0 0 1 0 1 5 f xclk6 /5 0 0 0 0 0 1 1 0 6 f xclk6 /6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (t xe6) and bit 5 (rxe6) of the asim6 re gister = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 4, 5, 6, ..., 255) 3. : don?t care 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 466 jul 15, 2010 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 16h. caution asicl6 can be refreshed (t he same value is written) by so ftware during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). however, do not set both sbrt6 and sbtt6 to 1 by a refresh operation during sbf reception (sbrt6 = 1) or sbf transmission (until intst6 o ccurs since sbtt6 has been set (1)), because it may re-trigger sbf recepti on or sbf transmission. figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 467 jul 15, 2010 figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 first-bit specification 0 msb 1 lsb txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 cautions 1. in the case of an sbf rece ption error, the mode returns to the sbf reception mode. the status of the sbrf6 flag is held (1). 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. after setting the sbrt6 bit to 1, do no t clear it to 0 before sbf r eception is completed (before an interrupt request si gnal is generated). 3. the read value of the sbrt6 bit is always 0. sbrt 6 is automatically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt6 bit to 1, make sure th at bit 7 (power6) and bit 6 (txe6) of asim6 = 1. after setting the sbtt6 bit to 1, do not clear it to 0 before sbf transmi ssion is completed (before an interrupt request signal is generated). 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission. 6. do not set the sbrt6 bit to 1 during reception, and do not set the sbtt6 bit to 1 during transmission. 7. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. 8. when the txdlv6 bit is set to 1 (inverted txd6 output), the txd6/scla0/p60 pin cannot be used as a general-purpose port, regard less of the settings of power6 and txe6. when using the txd6/scla0/p60 pin as a general-purpose port, clear the txdlv6 bit to 0 (normal txd6 output). 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 468 jul 15, 2010 (7) input switch control register (isc) the input switch control register (isc) is used to receive a status signal trans mitted from the master during lin (local interconnect network) reception. the signal input from the p14/r x d6 pin is selected as the input source of intp0 and ti000 when isc0 and isc1 are set to 1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 15-11. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p00) 1 r x d6 (p14) isc0 intp0 input source selection 0 intp0 (p120) 1 r x d6 (p14) (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/t x d6 pin for serial interface data output, clear pm 13 to 0 and set the output latch of p13 to 1. when using the p14/r x d6 pin for serial interface data input, set pm14 to 1. the output latch of p14 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 15-12. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 469 jul 15, 2010 15.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 15.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption c an be reduced. in addition, the pins can be used as ordinary port pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6 enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. if power6 = 0 is set while transmitting data, the out put of the txd6 pin will be fixed to high level (if txdlv6 = 0). furthermore, the input from the rxd6 pin will be fixed to high level. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 (sbrf6 ) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receiv e buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing t xe6 and rxe6 to 0 to stop the operation. to start the communication, set power6 to 1, and then set txe6 or rxe6 to 1. remark to use the r x d6/p14 and t x d6/p13 pins as general-purpose port pins, see chapter 5 port functions . 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 470 jul 15, 2010 15.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received followi ng a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is in corporated, so that communication c an be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 15-8 ). <2> set the brgc6 register (see figure 15-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 15-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 15-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take relationship with the ot her party of communication when se tting the port mode register and port register. the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm13 p13 pm14 p14 uart6 operation t x d6/p13 r x d6/p14 0 0 0 note note note note stop p13 p14 0 1 note note 1 reception p13 r x d6 1 0 0 1 note note transmission t x d6 p14 1 1 1 0 1 1 transmission/ reception t x d6 r x d6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm1 : port mode register p1 : port output latch 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 471 jul 15, 2010 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. figure 15-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and st op bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 472 jul 15, 2010 figure 15-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 473 jul 15, 2010 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same ty pe of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no par ity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 when the device is used in lin communication operation. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bi t, is controlled so that t he number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when t he data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 474 jul 15, 2010 (c) normal transmission when bit 7 (power6) of asynchronous serial interface o peration mode register 6 (asim6) is set to 1 and bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to transmit buffer register 6 (txb6). the start bit, par ity bit, and stop bit are automat ically appended to the data. when transmission is started, the data in txb6 is transferr ed to transmit shift register 6 (txs6). after that, the transmit data is sequentially output from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 15-15 shows the timing of the transmission completion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 15-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 475 jul 15, 2010 (d) continuous transmission the next transmit data can be written to transmit buffer register 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data c an be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be efficientl y written twice (2 bytes) wit hout having to wait for the transmission time of one data frame, by reading bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the trans mission completion interrupt has occurred. to transmit data continuously, be sure to reference t he asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asif6 register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the st atus, therefore, do not use a combination of the txbf6 and txsf6 flags for judgment . read only the txbf 6 flag when executing continuous transmission. 2. when the device is use in lin communi cation operation, the continuous transmission function cannot be used. make sure that asynchronous serial in terface transmission status register 6 (asif6) is 00h before writing transm it data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (firs t byte) to the txb6 register. be sure to check that the txbf 6 flag is ?0?. if so, write the n ext transmit data (second byte) to the txb6 register. if data is written to the txb6 re gister while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initialization is executed whil e the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmission, the next transmission may complete before execution of intst6 interrupt servicing afte r transmission of one data fr ame. as a countermeasure, detection can be performed by developing a pr ogram that can count the number of transmit data and by referenc ing the txsf6 flag. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 476 jul 15, 2010 figure 15-16 shows an example of the continuous transmission processing flow. figure 15-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 477 jul 15, 2010 figure 15-17 shows the timing of starting continuous tr ansmission, and figure 15-18 shows the timing of ending continuous transmission. figure 15-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a per iod in which txbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 478 jul 15, 2010 figure 15-18. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 479 jul 15, 2010 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator starts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 15-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, recepti on is started, and serial data is s equentially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the dat a of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receive data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a reception error interrupt (intsr6/in tsre6) is generated on completion of reception. figure 15-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. if a reception error occurs, read asis6 a nd then rxb6 to clear the er ror flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchronous serial interface recepti on error status register 6 (asis6) before reading rxb6. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 480 jul 15, 2010 (f) reception error three types of errors may occur during reception: a parity erro r, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status regist er 6 (asis6) is set as a result of data reception, a reception error interrupt request (intsr6/intsre6) is generated. which error has occurred during reception can be identified by reading the contents of asis6 in the reception error interrupt (intsr6/intsre6) servicing (see figure 15-6 ). the contents of asis6 are cleared to 0 when asis6 is read. table 15-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the reception error interrupt can be separated into rec eption completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous seri al interface operation mode register 6 (asim6) to 0. figure 15-20. reception error interrupt 1. if isrm6 is cleared to 0 (re ception completion interrupt (intsr6) and error interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 481 jul 15, 2010 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of the ma tch detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 15-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is use in lin communication operation, t he sbf (synchronous break field) transmission control function is used for transmission. for the transmission operation of lin, see figure 15-1 lin transmission operation . when bit 7 (power6) of asynchronous serial interf ace mode register 6 (asim6) is set to 1, the t x d6 pin outputs high level. next, when bit 6 (txe6) of asim6 is set to 1, the transmission enabled status is entered, and sbf transmission is started by setting bit 5 (sbtt6) of asynchro nous serial interface control register 6 (asicl6) to 1. thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) is output. following the end of sbf transmission, the transmission completion in terrupt request (intst6) is generated and sbtt6 is automatically cleared. thereafter, t he normal transmission mode is restored. transmission is suspended until the data to be transmitted next is written to tr ansmit buffer register 6 (txb6), or until sbtt6 is set to 1. figure 15-22. sbf transmission t x d6 intst6 sbtt6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 482 jul 15, 2010 (i) sbf reception when the device is used in lin communication operation, the sbf (synchronous break field) reception control function is used for reception. for the reception operat ion of lin, see figure 15-2 lin reception operation . reception is enabled when bit 7 (power6) of asynchrono us serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in t he same manner as the normal reception enable status. when the start bit has been detected, rece ption is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. when the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt request (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatically cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of asynchronous serial inte rface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart comm unication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffe r register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the sbf recepti on mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 15-23. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 483 jul 15, 2010 15.4.3 dedicated baud rate generator the dedicated baud rate generator c onsists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selection register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial inte rface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, cleared to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. if there is no data to be transmitted next, the counter is not cl eared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, cleared to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 484 jul 15, 2010 figure 15-24. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 (2) generation of serial clock a serial clock to be generated can be specified by using cl ock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). the clock to be input to the 8-bit counter can be set by bi ts 3 to 0 (tps63 to tps60) of cksr6 and the division value (f xclk6 /4 to f xclk6 /255) of the 8-bit counter can be set by bits 7 to 0 (mdl67 to mdl60) of brgc6. 15.4.4 calculation of baud rate (1) baud rate calculation expression the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of brgc6 register (k = 4, 5, 6, ..., 255) f xclk6 2 k 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 485 jul 15, 2010 table 15-4. set value of tps63 to tps60 base clock (f xclk6 ) selection note 1 tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note 2 2 mhz 5 mhz 10 mhz 20 mhz note 3 0 0 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output note 4 other than above setting prohibited notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tps63 = tps 62 = tps61 = tps60 = 0 (base clock: f prs ) is prohibited. 3. this is settable only if 4.0 v v dd 5.5 v. 4. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit ti mer/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 486 jul 15, 2010 (2) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transm ission to within the permi ssible error range at the reception destination. 2. make sure that the baud rate error during r eception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m / (2 33) = 10000000 / (2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] (3) example of setting baud rate table 15-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz f prs = 20.0 mhz baud rate [bps] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] 300 8h 13 301 0.16 7h 65 301 0.16 8h 65 301 0.16 9h 65 301 0.16 600 7h 13 601 0.16 6h 65 601 0.16 7h 65 601 0.16 8h 65 601 0.16 1200 6h 13 1202 0.16 5h 65 1202 0.16 6h 65 1202 0.16 7h 65 1202 0.16 2400 5h 13 2404 0.16 4h 65 2404 0.16 5h 65 2404 0.16 6h 65 2404 0.16 4800 4h 13 4808 0.16 3h 65 4808 0.16 4h 65 4808 0.16 5h 65 4808 0.16 9600 3h 13 9615 0.16 2h 65 9615 0.16 3h 65 9615 0.16 4h 65 9615 0.16 19200 2h 13 19231 0.16 1h 65 19231 0.16 2h 65 19231 0.16 3h 65 19231 0.16 24000 1h 21 23810 ? 0.79 3h 13 24038 0.16 4h 13 24038 0.16 5h 13 24038 0.16 31250 1h 16 31250 0 4h 5 31250 0 5h 5 31250 0 6h 5 31250 0 38400 1h 13 38462 0.16 0h 65 38462 0.16 1h 65 38462 0.16 2h 65 38462 0.16 48000 0h 21 47619 ? 0.79 2h 13 48077 0.16 3h 13 48077 0.16 4h 13 48077 0.16 76800 0h 13 76923 0.16 0h 33 75758 ? 1.36 0h 65 76923 0.16 1h 65 76923 0.16 115200 0h 9 111111 ? 3.55 1h 11 113636 ? 1.36 0h 43 116279 0.94 0h 87 114943 ? 0.22 153600 ? ? ? ? 1h 8 156250 1.73 0h 33 151515 ? 1.36 1h 33 151515 ? 1.36 312500 ? ? ? ? 0h 8 312500 0 1h 8 312500 0 2h 8 312500 0 625000 ? ? ? ? 0h 4 625000 0 1h 4 625000 0 2h 4 625000 0 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 4, 5, 6, ..., 255) f prs : peripheral hardware clock frequency err: baud rate error actual baud rate (baud rate with error) desired baud rate (correct baud rate) 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 487 jul 15, 2010 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within th e permissible error range, by using the calculation expression shown below. figure 15-25. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-25, the latch timing of the receive dat a is determined by the counter set by baud rate generator control register 6 (brgc6) after the start bit has been detect ed. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 488 jul 15, 2010 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the trans mission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 15-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 4 +2.33% ? 2.44% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on the num ber of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k 78k0/kx2 chapter 15 serial interface uart6 r01uh0008ej0401 rev.4.01 489 jul 15, 2010 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal val ue. however, the result of communica tion is not affected because the timing is initialized on the reception si de when the start bit is detected. figure 15-26. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 490 jul 15, 2010 chapter 16 serial interfaces csi10 and csi11 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 serial interface csi10 serial interface csi11 ? remark : mounted, ? : not mounted 16.1 functions of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 have the following two modes. (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 16.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is used to communicate 8-bit data using three lines: a serial clock line (sck1n) and two serial data lines (si1n and so1n). the processing time of data communication can be shor tened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is used for connecting peripheral ics and display controllers with a clocked serial interface. for details, see 16.4.2 3-wire serial i/o mode . remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 491 jul 15, 2010 16.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 include the following hardware. table 16-1. configuration of serial interfaces csi10 and csi11 item configuration controller transmit controller clock start/stop controller & clock phase controller registers transmit buffer register 1n (sotb1n) serial i/o shift re gister 1n (sio1n) control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) port mode register 0 (pm0) or port mode register 1 (pm1) port register 0 (p0) or port register 1 (p1) remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products figure 16-1. block diagram of serial interface csi10 internal bus si10/p11/r x d0 transmit buffer register 10 (sotb10) serial i/o shift register 10 (sio10) output selector so10/p12 output latch 8 transmit data controller 8 output latch (p12) pm12 so10 output intcsi10 transmit controller clock start/stop controller & clock phase controller output latch (p10) pm10 selector sck10/p10/txd0 f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 492 jul 15, 2010 figure 16-2. block diagram of serial interface csi11 8 8 internal bus output selector output latch so11/p02 transmit buffer register 11 (sotb11) transmit data controller si11/p03 serial i/o shift register 11 (sio11) ssi11 output latch (p02) pm02 so11 output transmit controller clock start/stop controller & clock phase controller intcsi11 output latch (p04) pm04 sck11/p04 ssi11 selector f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 (1) transmit buffer register 1n (sotb1n) this register sets the transmit data. transmission/reception is started by wr iting data to sotb1n when bit 7 (csie 1n) and bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. the data written to sotb1n is c onverted from parallel data into serial data by serial i/o shift register 1n, and output to the serial output pin (so1n). sotb1n can be written or read by an 8- bit memory manipulation instruction. reset signal generation clears this register to 00h. cautions 1. do not access sotb1n when csot1n = 1 (during serial communication). 2. in the slave mode, transmissi on/reception is started when data is written to sotb11 with a low level input to the ssi11 pin. for details on th e transmission/reception ope ration, see 16.4.2 (2) communication operation. (2) serial i/o shift register 1n (sio1n) this is an 8-bit register that converts data from parallel data into serial data and vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data from sio1n if bit 6 (trmd1n) of serial operati on mode register 1n (csim1n) is 0. during reception, the data is read from the serial input pin (si1n) to sio1n. reset signal generation clears this register to 00h. cautions 1. do not access sio1n when cs ot1n = 1 (during serial communication). 2. in the slave mode, reception is started when data is read from sio11 with a low level input to the ssi11 pin. for details on the reception oper ation, see 16.4.2 (2) communication operation. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 493 jul 15, 2010 16.3 registers controlling seri al interfaces csi10 and csi11 serial interfaces csi10 and csi11 are cont rolled by the following four registers. ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 0 (pm0) or port mode register 1 (pm1) ? port register 0 (p0) or port register 1 (p1) (1) serial operation mode register 1n (csim1n) csim1n is used to select the operation m ode and enable or disable operation. csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products figure 16-3. format of serial oper ation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd10 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 6 first bit specification 0 msb 1 lsb csot10 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p10/sck10/t x d0 and p12/so10 as general-purpose ports, se t csim10 in the default status (00h). 3. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 4. do not rewrite trmd10 when csot10 = 1 (during serial communication). 5. the so10 output (see figure 16-1 ) is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 6. do not rewrite dir10 when csot10 = 1 (during serial communication). caution be sure to clear bit 5 to 0. 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 494 jul 15, 2010 figure 16-4. format of serial oper ation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd11 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 6, 7 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 8 first bit specification 0 msb 1 lsb csot11 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p02/so11, p04/sck11, and p05/ssi11/ti001 as general-purpose ports, set csim11 in the default status (00h). 3. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 4. do not rewrite trmd11 when csot11 = 1 (during serial communication). 5. the so11 output (see figure 16-2 ) is fixed to the low level when trmd11 is 0. reception is started when data is read from sio11. 6. do not rewrite sse11 when csot11 = 1 (during serial communication). 7. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 8. do not rewrite dir11 when csot11 = 1 (during serial communication). 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 495 jul 15, 2010 (2) serial clock selecti on register 1n (csic1n) this register specifies the timing of the data transmission/reception and sets the serial clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products figure 16-5. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 csi10 serial clock selection notes 1, 2 cks102 cks101 cks100 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 1 mhz 2.5 mhz 5 mhz setting prohibited 0 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 15.63 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input from sck10 note 3 slave mode 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 496 jul 15, 2010 notes 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. set the serial clock to satisfy the following conditions. conventional-specification products ( pd78f05xx and 78f05xxd) and expanded-specification products ( pd78f05xxa and 78f05xxda) supply voltage standard products (a) grade products (a2) grade products 4.0 v v dd 5.5 v serial clock 6.25 mhz serial clock 5 mhz serial clock 5 mhz 2.7 v v dd < 4.0 v serial clock 4 mhz serial clock 2.5 mhz serial clock 2.5 mhz 1.8 v v dd < 2.7 v serial clock 2 mhz serial clock 1.66 mhz ? 3. do not start communication with the external clock from the sck10 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. cautions 1. do not write to csic10 while csie10 = 1 (operation enabled). 2. to use p10/sck10/t x d0 and p12/so10 as general-purpose ports , set csic10 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 497 jul 15, 2010 figure 16-6. format of serial clo ck selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 csi11 serial clock selection notes 1, 2 cks112 cks111 cks110 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 1 mhz 2.5 mhz 5 mhz setting prohibited 0 0 1 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 62.5 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 15.63 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input from sck11 note 3 slave mode note 1. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 498 jul 15, 2010 notes 2. set the serial clock to satisfy the following conditions. conventional-specification products ( pd78f05xx and 78f05xxd) and expanded-specification products ( pd78f05xxa and 78f05xxda) supply voltage standard products (a) grade products (a2) grade products 4.0 v v dd 5.5 v serial clock 6.25 mhz serial clock 5 mhz serial clock 5 mhz 2.7 v v dd < 4.0 v serial clock 4 mhz serial clock 2.5 mhz serial clock 2.5 mhz 1.8 v v dd < 2.7 v serial clock 2 mhz serial clock 1.66 mhz ? 3. do not start communication with the external clock from the sck11 pin when the internal high-speed oscillation clock and high-speed system clock are st opped while the cpu oper ates with the subsystem clock, or when in the stop mode. cautions 1. do not write to csic11 while csie11 = 1 (operation enabled). 2. to use p02/so11 and p04/sck11 as general- purpose ports, set csic11 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency (3) port mode registers 0 and 1 (pm0, pm1) these registers set port 0 and 1 input/output in 1-bit units. when using p10/sck10 and p04/sck11 as the clock output pins of the serial interface, clear pm10 and pm04 to 0, and set the output latches of p10 and p04 to 1. when using p12/so10 and p02/so11 as t he data output pins of the serial in terface, clear pm12, pm02, and the output latches of p12 and p02 to 0. when using p10/sck10 and p04/sck11 as the clock i nput pins of the serial interface, p11/si10/r x d0 and p03/si11 as the data input pins, and p05/ssi11/ti 001 as the chip select input pin, set pm10, pm04, pm11, pm03, and pm05 to 1. at this time, the output latches of p10, p04, p11, p03, and p05 may be 0 or 1. pm0 and pm1 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 16-7. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) remark the figure shown above presents the format of port mode register 0 of 78k0/kf2 products. for the format of port mode register 0 of other products, see (1) port mode registers (pmxx) in 5.3 registers controlling port function . 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 499 jul 15, 2010 figure 16-8. format of port mode register 1 (pm1) 7 pm17 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 symbol pm1 address: ff21h after reset: ffh r/w pm1n 0 1 p1n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 16.4 operation of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 16.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10/t x d0, p11/si10/r x d0, p12/so10, p02/so11, p 03/si11, and p04/sck11 pins can be used as ordinary i/o port pins in this mode. (1) register used the operation stop mode is set by serial operation mode register 1n (csim1n). to set the operation stop mode, clear bit 7 (csie1n) of csim1n to 0. (a) serial operation mode register 1n (csim1n) csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears csim1n to 00h. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p10/sck10/t x d0 and p12/so10 as general-purpose po rts, set csim10 in the default status (00h). 2. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 500 jul 15, 2010 ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p02/so11, p04/sck11, and p05/ssi11/ti001 as general-pur pose ports, set csim11 in the default status (00h). 2. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controllers with a clocked serial interface. in this mode, communication is executed by using three li nes: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) registers used ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 0 (pm0) or port mode register 1 (pm1) ? port register 0 (p0) or port register 1 (p1) the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set the csic1n register (see figures 16-5 and 16-6 ). <2> set bits 4 to 6 (dir1n, sse11 (serial interface cs i11 only), and trmd1n) of the csim1n register (see figures 16-3 and 16-4 ). <3> set bit 7 (csie1n) of the csim1n register to 1. transmission/reception is enabled. <4> write data to transmit buffer register 1n (sotb1n). data transmission/reception is started. read data from serial i/o shift register 1n (sio1n). data reception is started. caution take relationship with the ot her party of communication when se tting the port mode register and port register. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 501 jul 15, 2010 the relationship between the register settings and pins is shown below. table 16-2. relationship between register settings and pins (1/2) (a) serial interface csi10 pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation si10/r x d0/ p11 so10/p12 sck10/ t x d0/p10 0 0 note 1 note 1 note 1 note 1 note 1 note 1 stop r x d0/p11 p12 note 2 t x d0/ p10 note 3 1 0 1 note 1 note 1 1 slave reception note 4 si10 p12 note 2 sck10 (input) note 4 1 1 note 1 note 1 0 0 1 slave transmission note 4 r x d0/p11 so10 sck10 (input) note 4 1 1 1 0 0 1 slave transmission/ reception note 4 si10 so10 sck10 (input) note 4 1 0 1 note 1 note 1 0 1 master reception si10 p12 note 2 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission r x d0/p11 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p12/so10 as general-purpose port, set the seri al clock selection regist er 10 (csic10) in the default status (00h). 3. to use p10/sck10/t x d0 as port pins, clear ckp10 to 0. 4. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1 : port mode register p1 : port output latch 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 502 jul 15, 2010 table 16-2. relationship between register settings and pins (2/2) (b) serial interface csi11 pin function csie11 trmd11 sse11 pm03 p03 pm02 p02 pm04 p04 pm05 p05 csi11 operation si11/ p03 so11/ p02 sck11/ p04 ssi11/ ti001/p05 0 0 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 stop p03 p02 note 2 p04 note 3 ti001/ p05 0 note 1 note 1 ti001/ p05 1 0 1 1 note 1 note 1 1 1 slave reception note 4 si11 p02 note 2 sck11 (input) note 4 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 note 1 note 1 0 0 1 1 slave transmission note 4 p03 so11 sck11 (input) note 4 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 1 0 0 1 1 slave transmission/ reception note 4 si11 so11 sck11 (input) note 4 ssi11 1 0 0 1 note 1 note 1 0 1 note 1 note 1 master reception si11 p02 note 2 sck11 (output) ti001/ p05 1 1 0 note 1 note 1 0 0 0 1 note 1 note 1 master transmission p03 so11 sck11 (output) ti001/ p05 1 1 0 1 0 0 0 1 note 1 note 1 master transmission/ reception si11 so11 sck11 (output) ti001/ p05 notes 1. can be set as port function. 2. to use p02/so11 as general-purpose port, set the seri al clock selection regist er 11 (csic11) in the default status (00h). 3 to use p04/sck11 as port pins, clear ckp11 to 0. 4 to use the slave mode, set cks112, cks111, and cks110 to 1, 1, 1. remark : don?t care csie11: bit 7 of serial operation mode register 11 (csim11) trmd11: bit 6 of csim11 ckp11: bit 4 of serial clock selection register 11 (csic11) cks112, cks111, cks110: bits 2 to 0 of csic11 pm0 : port mode register p0 : port output latch 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 503 jul 15, 2010 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the data is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is written to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 0. reception is started when dat a is read from serial i/o shift register 1n (sio1n). however, communication is performed as follows if bit 5 (sse 11) of csim11 is 1 when serial interface csi11 is in the slave mode. <1> low level input to the ssi11 pin transmission/reception is started when sotb11 is writt en, or reception is star ted when sio11 is read. <2> high level input to the ssi11 pin transmission/reception or reception is held, therefore, even if sotb 11 is written or sio11 is read, transmission/reception or rece ption will not be started. <3> data is written to sotb11 or data is read from sio 11 while a high level is input to the ssi11 pin, then a low level is input to the ssi11 pin transmission/reception or reception is started. <4> a high level is input to the ssi11 pi n during transmission/reception or reception transmission/reception or reception is suspended. after communication has been started, bi t 0 (csot1n) of csim1n is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1n) is set, and csot1n is cleared to 0. then the next communication is enabled. cautions 1. do not access the control register a nd data register when cs ot1n = 1 (during serial communication). 2. when using serial interface csi11, wait for the duration of at least one clock before the clock operation is started to change the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 504 jul 15, 2010 figure 16-9. timing in 3-wire serial i/o mode (1/2) (a) transmission/reception timing (t ype 1: trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for seri al interface csi11, and are used in the slave mode. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 505 jul 15, 2010 figure 16-9. timing in 3-wire serial i/o mode (2/2) (b) transmission/reception timing (t ype 2: trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for seri al interface csi11, and are used in the slave mode. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 506 jul 15, 2010 figure 16-10. timing of clock/data phase (a) type 1: ckp1n = 0, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2: ckp1n = 0, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3: ckp1n = 1, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4: ckp1n = 1, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remarks 1. n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash memory is at least 48 kb, and 78k0/kf2 products 2. the above figure illustrates a communication operat ion where data is transmitted with the msb first. 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 507 jul 15, 2010 (3) timing of output to so1n pin (first bit) when communication is started, the valu e of transmit buffer register 1n (sotb 1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 16-11. output operation of first bit (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch (b) type 3: ckp1n = 1, dap1n = 0 sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n first bit 2nd bit the first bit is directly latched by t he sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output sele ctor. then, the value of the sotb1n register is transferred to the sio1n register at the next rising (or falling) ed ge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio1n re gister via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 508 jul 15, 2010 figure 16-11. output operation of first bit (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch (d) type 4: ckp1n = 1, dap1n = 1 first bit 2nd bit 3rd bit sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n the first bit is directly latched by the sotb1n register at the falling edge of the write si gnal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector . then, the value of the sotb1n register is transferred to the s io1n register at the next falling (or risi ng) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio1n regi ster via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next rising (or falling) edge of sck1n, and the data is output from the so1n pin. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 509 jul 15, 2010 (4) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 16-12. output value of so1n pin (last bit) (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n ( next request is issued.) last bit output latch (b) type 3: ckp1n = 1, dap1n = 0 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 510 jul 15, 2010 figure 16-12. output value of so1n pin (last bit) (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n last bit writing to sotb1n or reading from sio1n ( next request is issued.) output latch (d) type 4: ckp1n = 1, dap1n = 1 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0: 78k0/ke2 products whose flash memo ry is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 16 serial interfaces csi10 and csi11 r01uh0008ej0401 rev.4.01 511 jul 15, 2010 (5) so1n output (see fi gures 16-1 and 16-2) the status of the so1n output is as follows depending on the setting of csie1n, trmd1n, dap1n, and dir1n. table 16-3. so1n output status csie1n trmd1n dap1n dir1n so1n output note 1 trmd1n = 0 notes 2, 3 ? ? low level output note 2 dap1n = 0 ? low level output dir1n = 0 value of bit 7 of sotb1n csie1n = 0 note 2 trmd1n = 1 dap1n = 1 dir1n = 1 value of bit 0 of sotb1n trmd1n = 0 note 3 ? ? low level output csie1n = 1 trmd1n = 1 ? ? transmission data note 4 notes 1. the actual output of the so10/p12 or so11/p02 pin is dete rmined according to pm12 and p12 or pm02 and p02, as well as the so1n output. 2. this is a status after reset. 3. to use the p12/so10 or p02/so 11 pin as general-purpose port, set the serial clock selection register 1n (csic1n) in the default status (00h). 4. after transmission has been completed, the so1n pin holds the output value of the last bit of transmission data. caution if a value is written to csie1n, trmd 1n, dap1n, and dir1n, the output value of so1n changes. remark n = 0: 78k0/ke2 products whose flash memory is less than 32 kb, and 78k0/kb2, 78k0/kc2, 78k0/kd2 products n = 0, 1: 78k0/ke2 products whose flash me mory is at least 48 kb, and 78k0/kf2 products 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 512 jul 15, 2010 chapter 17 serial interface csia0 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 serial interface csia0 ? remark : mounted, ? : not mounted 17.1 functions of serial interface csia0 serial interface csia0 has the following three modes. (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 17.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is to communicate data successively in 8-bit uni ts, by using three lines: serial clock (scka0) and serial data (sia0 and soa0) lines. the processing time of data communication can be shor tened in the 3-wire serial i/o mode because transmission and reception can be simu ltaneously executed. in addition, whether 8-bit data is communicated msb or lsb first can be specified, so this interface can be connected to any device. for details, see 17.4.2 3-wire serial i/o mode . (3) 3-wire serial i/o mode with automatic transmit/receive functi on (msb/lsb-first selectable) this mode is used to communicate data continuously in 8- bit units using three lines: a serial clock line (scka0) and two serial data lines (sia0 and soa0). the processing time of data communication can be shortened in the 3-wire seri al i/o mode with automatic transmit/receive function because transmission an d reception can be simultaneously executed. in addition, whether 8-bit data is communicated msb or lsb first can be specified, so this interface can be connected to any device. data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer ram is incorporated. also, the incorporation of hands hake pins (stb0, busy0) used in the master mode has made connection to peripheral ics easy. for details, see 17.4.3 3-wire serial i/o mode with au tomatic transmit/receive function . 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 513 jul 15, 2010 the features of serial interface csia0 are as follows. ? master mode/slave mode selectable ? communication data length: 8 bits ? msb/lsb-first selectab le for communication data ? automatic transmit/receive function: number of transfer bytes c an be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single communication/repeat communication selectable internal 32-byte buffer ram ? on-chip dedicated baud rate generator (6/8/16/32 divisions) ? 3-wire soa0: serial data output sia0: seri al data input scka0: serial clock i/o ? handshake function incorporated stb0: strobe output busy0: busy input ? detection of bit shift error due to busy0 signal ? transmission/reception completion interrupt: intacsi 17.2 configuration of serial interface csia0 serial interface csia0 consists of the following hardware. table 17-1. configuration of serial interface csia0 item configuration controller serial transfer controller registers serial i/o sh ift register 0 (sioa0) control registers serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0) automatic data transfer address count register 0 (adtc0) port mode register 14 (pm14) port register 14 (p14) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 514 jul 15, 2010 figure 17-1. block diagram of serial interface csia0 internal bus baud rate generator f w /6 to f w /32 selector master0 p145 p142 pm142 pm145 pm144 scka0/p142 busy0/p141 stb0/p145 soa0/p144 sia0/p143 dir0 ate0 6-bit counter buffer ram interrupt generator serial transfer controller atm0 serial clock counter stbe0 busye0 atstp0 atsta0 busylv0 erre0 errf0 tsf0 automatic data transfer address point specification register 0 (adtp0) automatic data transfer address count register 0 (adtc0) divisor selection register 0 (brgca0) serial i/o shift register 0 (sioa0) automatic data transfer interval specification register 0 (adti0) intacsi rxae0 txae0 p144 3 4 2 serial trigger register 0 (csit0) serial status register 0 (csis0) f prs f prs /2 f w cks000 atm0 master0 txea0 rxea0 dir0 ate0 csiae0 serial operation mode specification register 0 (csima0) internal bus selector 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 515 jul 15, 2010 (1) serial i/o shift register 0 (sioa0) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ate0) of serial operation mode specification r egister 0 (csima0) = 0). writing transmit data to sioa0 starts the communication. in addition, after a communication completion interrupt reques t (intacsi) is output (bit 0 (tsf0) of serial status register 0 (csis0) = 0), data can be received by reading data from sioa0. this register can be written or read by an 8-bit memory manipulation instructi on. however, writing to sioa0 is prohibited when bit 0 (tsf0) of seri al status register 0 (csis0) = 1. reset signal generation clears this register to 00h. cautions 1. a communication operation is starte d by writing to sioa0. consequently, when transmission is disabled (bit 3 (txea0) of cs ima0 = 0), write dummy data to the sioa0 register to start the communication operati on, and then perform a receive operation. 2. do not write data to sioa0 while the au tomatic transmit/receive function is operating. 17.3 registers controlling serial interface csia0 serial interface csia0 is controlle d by the following nine registers. ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) ? automatic data transfer address count register 0 (adtc0) ? port mode register 14 (pm14) ? port register 14 (p14) (1) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to cont rol the serial communication operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 516 jul 15, 2010 figure 17-2. format of serial operation mode specification register 0 (csima0) csiae0 csia0 operation disabled (soa0: low level, scka0: high level) and asynchronously resets the internal circuit note 1 . csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte communication mode automatic communication mode ate0 0 1 control of automatic communication operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic communication mode specification slave mode (synchronous with scka0 input clock) note 2 master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol < > < > < > notes 1. automatic data transfer address count register 0 (adtc0 ), serial trigger register 0 (csit0), serial i/o shift register 0 (sioa0), and bit 0 (tsf0) of serial status register 0 (csis0) are reset. 2. do not start communication with the external clock from the scka0 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the cpu operates with the subsystem clock, or when in the stop mode. cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, the registers and bits mentioned in note above are asynchronously initialized. to set csiae0 = 1 again, be sure to re -set the initialized registers. 3. when csiae0 is re-set to 1 after csiae0 is ch anged from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 517 jul 15, 2010 (2) serial status register 0 (csis0) this is an 8-bit register used to select the base clo ck, control the communication operation, and indicate the status of serial interface csia0. this register can be set by a 1-bit or 8-bit memory m anipulation instruction. ho wever, rewriting csis0 is prohibited when bit 0 (tsf0) is 1. reset signal generation clears this register to 00h. figure 17-3. format of serial st atus register 0 (csis0) (1/2) 0 csis0 symbol cks00 note 2 stbe0 busye0 busylv0 erre0 errf0 tsf0 strobe output disabled strobe output enabled stbe0 notes 6, 7 0 1 strobe output enable/disable cks00 0 1 base clock (f w ) selection note 3 address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 f prs note 4 f prs /2 f prs = 2 mhz 2 mhz 1 mhz f prs = 5 mhz 5 mhz 2.5 mhz f prs = 10 mhz 10 mhz 5 mhz f prs = 20 mhz 20 mhz note 5 10 mhz notes 1. bits 0 and 1 are read-only. 2. make sure that bit 7 (csiae0) of the serial operat ion mode specification regi ster 0 (csima0) = 0 when rewriting the cks00 bit. 3. the frequency that can be used for the peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 4. if the peripheral hardware clock (f prs ) operates on the internal hi gh-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks00 = 0 (base clock: f prs ) is prohibited. 5. this is settable only if 4.0 v v dd 5.5 v. 6. stbe0 is valid only in master mode. 7. when stbe0 is set to 1, two transfer clocks are consumed between byte trans fers regardless of the setting of automatic data transfer interv al specification regist er 0 (adti0). that is, 10 transfer clocks are used for 1-byte transfer if adti0 = 00h is set. caution be sure to clear bit 7 to 0. remark f prs : peripheral hardware clock frequency 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 518 jul 15, 2010 figure 17-3. format of serial st atus register 0 (csis0) (2/2) error detection disabled error detection enabled erre0 note 2 0 1 bit error detection enable/disable bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input when communication is started by setting bit 0 (atsta0) of serial trigger register 0 (csit0) to 1 or writing to sioa0. bit error detected (when erre0 = 1, the level specified by busylv0 during the data bit transfer period is detected via busy0 pin input). errf0 0 1 bit error detection flag bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 at reset input at the end of the specified transfer when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag busy signal detection disabled (input via busy0 pin is ignored) busy signal detection enabled and communication wait by busy signal is executed busye0 0 1 busy signal detection enable/disable low level high level busylv0 note 1 0 1 busy signal active level setting notes 1. in bit error detection by busy input, the active level specified by busylv0 is detected. 2. the erre0 setting is valid even when busye0 = 0. caution during transfer (tsf 0 = 1), rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0), divi sor selection register 0 (brgca0), automatic data transfer address point specification register 0 (adt p0), automatic data transfer in terval specification register 0 (adti0), and serial i/o shift regist er 0 (sioa0) are prohibited. however, these registers can be read and re-written to the same value. in addition, the buffer ram can be rewritten during transfer. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 519 jul 15, 2010 (3) serial trigger register 0 (csit0) this is an 8-bit register used to c ontrol execution/stop of au tomatic data transfer between buffer ram and serial i/o shift register 0 (sioa0). this register can be set by a 1-bit or 8-bit memory manipu lation instruction. this register can be set when bit 6 (ate0) of serial operation mode specif ication register 0 (csima0) is 1. reset signal generation clears this register to 00h. figure 17-4. format of serial trigger register 0 (csit0) 0 csit0 symbol 0 0 0 0 0 atstp0 atsta0 automatic data transfer stopped atstp0 0 1 automatic data transfer stop automatic data transfer started atsta0 0 1 automatic data transfer start address: ff92h after reset: 00h r/w 4 3 2 <1> <0> 6 75 ? ? cautions 1. even if atstp0 or atst a0 is set to 1, automa tic transfer cannot be st arted/stopped until 1-byte transfer is complete. 2. atstp0 and atsta0 change to 0 automatically after the interr upt signal intacsi is generated. 3. after automatic data transfer is stopped, th e data address when the tr ansfer stopped is stored in automatic data transfer address count regist er 0 (adtc0). however, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting atstp0 = 1, start automatic data transfer by setting at sta0 to 1 after re- setting the registers. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 520 jul 15, 2010 (4) divisor selection register 0 (brgca0) this is an 8-bit register used to select the base clock divisor of csia0. this register can be set by an 8-bit memory manipulation in struction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. reset signal generation sets this register to 03h. figure 17-5. format of divisor selection register 0 (brgca0) 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 selection of base clock (f w ) divisor of csia0 note 166.67 khz 125 khz 62.5 khz 31.25 khz 333.3 khz 250 khz 125 khz 62.5 khz 416.67 khz 312.5 khz 156.25 khz 78.125 khz 833.33 khz 625 khz 312.5 khz 156.25 khz 1.67 mhz 1.25 mhz 625 khz 312.5 khz setting prohibited setting prohibited 1.25 mhz 625 khz address: ff93h after reset: 03h r/w 43 21 0 6 75 f w /6 f w /2 3 f w /2 4 f w /2 5 f w = 1 mhz f w = 2 mhz f w = 5 mhz f w = 10 mhz f w = 20 mhz f w = 2.5 mhz note set the transfer clock so as to satisfy the following conditions. ? when 4.0 v v dd 5.5 v: transfer clock 1.67 mhz ? when 2.7 v v dd < 4.0 v: transfer clock 833.33 khz ? when 1.8 v v dd < 2.7 v: transfer clock 555.56 khz (standard products and (a) grade products only) remark f w : base clock frequency selected by cks00 bit of csis0 register (f prs or f prs /2) f prs : peripheral hardware clock frequency 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 521 jul 15, 2010 (5) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffer ra m address that ends transfer during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 = 1). this register can be set by an 8-bit memory manipulatio n instruction. however, during transfer (tsf0 = 1), rewriting adtp0 is prohibited. in the 78k0/kf2, 00h to 1fh can be specified bec ause 32 bytes of buffer ram are incorporated. example when adtp0 is set to 07h 8 bytes of fa00h to fa07h are transferred. in repeat transfer mode (bit 5 (atm0) of csima0 = 1), transfer is performed repeatedly up to the address specified with adtp0. example when adtp0 is set to 07h (repeat transfer mode) transfer is repeated as fa00h to fa07h, fa00h to fa07h, ? . figure 17-6. format of automatic data transfer address point specificat ion register 0 (adtp0) 0 adtp0 0 0 adtp04 adtp03 adtp02 adtp01 adtp00 address: ff94h after reset: 00h r/w symbol 43 21 0 6 75 caution be sure to clea r bits 7 to 5 to ?0?. the relationship between transfer end buffer ram address values and adtp0 setting values is shown below. table 17-2. relationship between transfer end buffer ram address values and adtp0 setting values transfer end buffer ram address value adtp0 setting value faxxh xxh remark xx: 00 to 1f 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 522 jul 15, 2010 (6) automatic data transfer inter val specification register 0 (adti0) this is an 8-bit register used to specify the interval time for byte data transfer during automatic data transfer (bit 6 (ate0) of serial operation mode specif ication register 0 (csima0) = 1). set this register when in master mode (bit 4 (master0) of csima0 = 1) (setting is unnecessary in slave mode). setting in 1-byte communication mode (bit 6 (ate0) of csima0 = 0) is also valid. when the interval time specified by adti0 after the end of 1-byte communication has elapsed, an interrupt request signal (intacsi) is output. the number of clocks for the interv al can be set to between 0 and 63 clocks. this register can be set by an 8-bit memory manipulation in struction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, re writing adti0 is prohibited. figure 17-7. format of automatic data transf er interval specificatio n register 0 (adti0) 0 adti0 0 adti05 adti04 adti03 adti02 adti01 adti00 address: ff95h after reset: 00h r/w symbol 43 21 0 6 75 caution because the setting of bit 5 (stbe0) and bit 4 ( busye0) of serial status register 0 (csis0) takes priority over the adti0 setting, the interval time based on th e setting of stbe0 and busye0 is generated even when adt i0 is cleared to 00h. example interval time when adti0 = 00h and busy signal is not generated <1> when stbe0 = 1, busye0 = 0: inter val time of two seria l clocks is generated <2> when stbe0 = 0, busye0 = 1: inter val time of one seria l clock is generated <3> when stbe0 = 1, busye0 = 1: inter val time of two seria l clocks is generated therefore, clearing stbe0 and busye0 to 0 is required to perform no-wait transfer. the specified interval time is the seri al clock (specified by divisor selecti on register 0 (brgca0)) multiplied by an integer value. example when adti0 = 03h scka0 interval time of 3 clocks 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 523 jul 15, 2010 (7) automatic data transfer a ddress count register 0 (adtc0) this is a register used to indicate buffer ram addresse s during automatic transfer. when automatic transfer is stopped, the data position when trans fer stopped can be ascertained by reading adtc0 register value. this register can be read by an 8-bi t memory manipulation instruction. reset signal generation clears this register to 00h. however, reading from adtc0 is prohibited when bit 0 (tsf0) of serial status register 0 (csis0) = 1. figure 17-8. format of automatic data tr ansfer address count register 0 (adtc0) 0 adtc0 0 0 adtc04 adtc03 adtc02 adtc01 adtp00 address: ff97h after reset: 00h r symbol 43 21 0 6 75 (8) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using p142/scka0 pin as the clock output of the serial interface, cl ear pm142 to 0 and set the output latch of p142 to 1. when using p144/soa0 and p145/stb0 pi ns as the data output or strobe output of the serial interface, clear pm144, pm145, and the output la tches of p144 and p145 to 0. when using p141/busy0, p142/scka0, and p143/sia0 pins as the busy input, clock input, or data input of the serial interface, set pm141, pm142, and pm143 to 1. at this time, the out put latches of p141, p142, and p143 may be 0 or 1. pm14 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 17-9. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 pm145 pm144 pm143 pm142 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 524 jul 15, 2010 17.4 operation of serial interface csia0 serial interface csia0 has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 17.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be re duced. in addition, the p142/scka0, p143/sia0, and p144/so a0 pins can be used as ordinary i/o port pins in this mode. (1) register used the operation stop mode is set by serial operation mode specificat ion register 0 (csima0). to set the operation stop mode, clear bit 7 (csiae0) of csima0 to 0. (a) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to cont rol the serial communication operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. csiae0 csia0 operation disabled (soa0: low level, scka0: high level) and asynchronously resets the internal circuit csiae0 0 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 address: ff90h after reset: 00h r/w < > < > < > 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 525 jul 15, 2010 17.4.2 3-wire serial i/o mode the one-byte data transmission/reception is executed in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is cleared to 0. the 3-wire serial i/o mode is useful for connecting peripheral ics and display controllers with a clocked serial interface. in this mode, communication is executed by using three lin es: serial clock (scka0), serial output (soa0), and serial input (sia0) lines. (1) registers used ? serial operation mode specif ication register 0 (csima0) note 1 ? serial status register 0 (csis0) note 2 ? divisor selection register 0 (brgca0) ? port mode register 14 (pm14) ? port register 14 (p14) notes 1. bits 7, 6, and 4 to 1 (csiae0, ate0, master0, txea0, rxea0, and dir0) are used. setting of bit 5 (atm0) is invalid. 2. only bit 0 (tsf0) and bit 6 (cks00) are used. the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set bit 6 (cks00) of the csis0 register (see figure 17-3 ) note 1 . <2> set the brgca0 register (see figure 17-5 ) note 1 . <3> set bits 4 to 1 (master0, txea0, rxea0 , and dir0) of the csima0 register (see figure 17-2 ). <4> set bit 7 (csiae0) of the csima0 register to 1 and clear bit 6 (ate0) to 0. <5> write data to serial i/o shift register 0 (sioa0). data transmission/reception is started note 2 . notes 1. this register does not have to be set when the slave mode is specified (master0 = 0). 2. write dummy data to sioa0 only for reception. caution take relationship with the other party of communication when setting the port mode register and port register. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 526 jul 15, 2010 the relationship between the register settings and pins is shown below. table 17-3. relationship between register settings and pins pin function csiae0 ate0 master0 pm 143 p143 pm144 p144 pm142 p142 serial i/o shift register 0 operation serial clock counter operation control sia0/ p143 soa0/ p144 scka0/ p142 0 note 1 note 1 note 1 note 1 note 1 note 1 operation stopped clear p143 p144 p142 0 1 scka0 (input) 1 0 1 1 note 2 note 2 0 note 3 0 note 3 0 1 operation enabled count operation sia0 note 2 soa0 note 3 scka0 (output) notes 1. can be set as port function. 2. can be used as p143 when only transmission is performed. clear bit 2 (rxea0) of csima0 to 0. 3. can be used as p144 when only reception is performed. clear bit 3 (txea0) of csima0 to 0. remark : don?t care csiae0: bit 7 of serial operation mo de specification register 0 (csima0) ate0: bit 6 of csima0 master0: bit 4 of csima0 pm14 : port mode register p14 : port output latch 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 527 jul 15, 2010 (2) 1-byte transmission/recep tion communication operation (a) 1-byte transmission/reception when bit 7 (csiae0) and bit 6 (ate0) of serial operat ion mode specification regist er 0 (csima0) = 1, 0, respectively, if communication data is written to serial i/o shift register 0 (sioa0), the data is output via the soa0 pin in synchronization with the scka0 falling edge, and stored in the sioa0 register in synchronization with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, communication c an only be started by writing a dummy value to the sioa0 register. when communication of 1 byte is complete, an inte rrupt request signal (intacsi) is generated. in 1-byte transmission/reception, the setting of bit 5 (atm0) of csima0 is invalid. be sure to read data after confirming that bit 0 (t sf0) of serial status register 0 (csis0) = 0. figure 17-10. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at falling edge of scka0 scka0 sia0 soa0 acsiif tsf0 sioa0 write caution the soa0 pin becomes lo w level by an sioa0 write. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 528 jul 15, 2010 (b) data format in the data format, data is changed in synchroniza tion with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data communica tion direction can be switched by the specification of bit 1 (dir0) of serial operation m ode specification register 0 (csima0). figure 17-11. format of transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 529 jul 15, 2010 (c) switching msb/lsb as start bit figure 17-12 shows the configuration of serial i/o shift register 0 (sioa0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. switching msb/lsb as the start bit can be specified using bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-12. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sia0 shift register 0 (sioa0) read/write gate soa0 scka0 dq soa0 latch start bit switching is realized by switching the bit or der for data written to sioa0. the sioa0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (d) communication start serial communication is started by setting communication data to serial i/o shift register 0 (sioa0) when the following two conditions are satisfied. ? serial interface csia0 operation control bit (csiae0) = 1 ? serial communication is not in progress caution if csiae0 is set to 1 after data is writte n to sioa0, communication does not start. upon termination of 8-bit communication, serial communi cation automatically stops and the interrupt request flag (acsiif) is set. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 530 jul 15, 2010 17.4.3 3-wire serial i/o mode with au tomatic transmit/receive function up to 32 bytes of data can be transmitted/ received without using software in the mode in which bit 6 (ate0) of serial operation mode specification regi ster 0 (csima0) is set to 1. after communi cation is started, only data of the set number of bytes stored in ram in advance can be transmitted, and only data of the set number of bytes can be received and stored in ram. in addition, to transmit/receive data continuously wh en used as the master, handshake signals (stb0 and busy0) generated by hardware are supported. t herefore, connection to peripheral ics su ch as osd (on screen display) ics and lcd controller/drivers can be easily realized. (1) registers used ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) ? port mode register 14 (pm14) ? port register 14 (p14) the relationship between the register settings and pins is shown below. caution a wait state may be generated when data is written to the buffer ram. for details, see chapter 36 cautions for wait. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 531 jul 15, 2010 table 17-4. relationship between register settings and pins csiae0 0 1 ate0 1 master0 0 1 stbe0 note 1 0 1 busye0 note 1 note 1 0 1 erre0 note 1 0/1 0/1 0/1 pm143 note 1 1 p143 note 1 pm144 note 1 0 p144 note 1 0 pm142 note 1 1 0 p142 note 1 1 pm145 note 1 note 1 note 1 0 p145 note 1 note 1 note 1 0 pm141 note 1 note 1 note 1 1 p141 note 1 note 1 note 1 serial i/o shift register 0 operation operation stopped operation enabled busy0/ p141 p141 p141 p141 busy0 stb0/ p145 p145 p145 p145 stb0 scka0/ p142 p142 scka0 (input) scka0 (output) pin function soa0/ p144 p144 soa10 sia0/ p143 p143 sia0 serial clock counter operation control clear count operation note 2 note 3 notes 1. can be set as port function. 2. can be used as p143 when only transmission is performed. clear bit 2 (rxea0) of csima0 to 0. 3. can be used as p144 when only reception is per formed. clear bit 3 (txea0) of csima0 to 0. remark : don?t care csiae0: bit 7 of serial operation mo de specification register 0 (csima0) ate0: bit 6 of csima0 master0: bit 4 of csima0 stbe0: bit 5 of serial status register 0 (csis0) busye0: bit 4 of csis0 erre0: bit 2 of csis0 pm14 : port mode register p14 : port output latch 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 532 jul 15, 2010 (2) automatic transmit/receive data setting here is an example of the procedure for successi vely transmitting/receiving data as the master. <1> enable csia0 to operate by setting bit 7 (csiae0) of serial operation mode specification register 0 (csima0) to 1 (the buffer ram can now be accessed). <2> select a serial clock by using serial status register 0 (csis0). <3> set the division ratio of the serial clock by usi ng division value selection regi ster 0 (brgca0), and specify a communication rate. <4> sequentially write data to be tr ansmitted to the buffer ram, starting from the least significant address fa00h, up to fa1fh. data is transmitted from the lo west address, continuing on to higher addresses. <5> set ?number of data items to be transmitted ? 1? to automatic data transfe r address point specification register 0 (adtp0). <6> set bits 6 (ate0) and 4 (master0) of csima0 to select a master oper ation in the automatic communication mode. <7> set bits 3 (txea0) and 2 (rxea0) of csim a0 to 1 to enable transmission/reception. <8> set the transmission interval of data to the automati c data transfer interval specif ication register (adti0). <9> automatic transmit/receive processing is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1. caution take the relationship with the other communicating party in to consideration when setting the port mode register and port register. operations <1> to <9> exec ute the following operation. ? after the buffer ram data indicated by automatic da ta transfer address count register 0 (adtc0) is transferred to sioa0, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by adtc0. ? adtc0 is incremented and the next data tr ansmission/reception is carried out. data transmission/reception continues until the adtc0 increm ental output matches the set value of automatic data transfer address point specificat ion register 0 (adtp0) (end of aut omatic transmission/reception). however, if bit 5 (atm0) of csima0 is set to 1 (repeat mode), adtc0 is cleared after a match between adtp0 and adtc0, and then repeated tr ansmission/reception is started. ? when automatic transmission/reception is terminated , an interrupt request (intacsi) is generated and bit 0 (tsf0) of csis0 is cleared. ? to continue transmitting the next data, set the new dat a to the buffer ram, and set ?number of data to be transmitted ? 1? to adtp0. after setting the number of data, set atsta0 to 1. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 533 jul 15, 2010 (3) automatic transmission/re ception communication operation (a) automatic transmi ssion/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soa0 pin via the sioa 0 register in synchronization with the scka0 falling edge by performing (2) automatic transmit/receive data setting . the receive data is stored in the buffer ram via the s ioa0 register in synchronization with the scka0 rising edge. data transfer ends if bit 0 (tsf0) of serial status register 0 (csis0) is set to 1 when any of the following conditions is met. ? communication stop: reset by clearing bi t 7 (csiae0) of the csima0 register to 0 ? communication suspension: transfer of 1 byte is comp lete by setting bit 1 (atstp0) of the csit0 register to 1 ? bit shift error: transfer of 1 byte is complete when bit 1 (errf0) of the csis0 register becomes 1 while bit 2 (erre0) = 1 ? transfer of the range specified by the adtp0 register is complete at this time, an interrupt request signal (intacsi ) is generated except when the csiae0 bit = 0. if a transfer is terminated in the middle, transfer starti ng from the remaining dat a is not possible. read automatic data transfer address count register 0 (adtc0) to confirm how much of the data has already been transferred and re-execute transfer by performing (2) automatic transmit/receive data setting . in addition, when busy control and strobe contro l are not performed, the busy0/buz/intp7/p141 and stb0/p145 pins can be used as ordinary i/o port pins. figure 17-13 shows the example of the operation timing in automatic tr ansmission/reception mode and figure 17-14 shows the operation flowchart. figures 17-15 and 17-16 show the operation of internal buffer ram when 6 bytes of data are transmitted/received. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 534 jul 15, 2010 figure 17-13. example of automatic transm ission/reception mode operation timings scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the au tomatic transmission/reception mo de, the automatic transmit/receive function writes/reads data to/from th e internal buffer ram after 1-byte transmission/reception, an inte rval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu pr ocessing, the interval is dependent upon the value of au tomatic data transfer inter val specification register 0 (adti0) and the set values of bits 5 and 4 (s tbe0, busye0) of serial status register 0 (csis0) (see (5) automatic tran smit/receive interval time). 2. if an access to the buffer ram by the cp u conflicts with an access to the buffer ram by serial interface csia0 during the interval period, the interval time sp ecified by automatic data transfer interval specification register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 535 jul 15, 2010 figure 17-14. automatic transm ission/reception mode flowchart start set csiae0 to 1 set the communication speed write transmit data in internal buffer ram note set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission/reception mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission/reception operation write receive data from sioa0 to internal buffer ram note adtp0 = adtc0 no tsf0 = 0 no end yes yes increment adtc0 software execution hardware execution software execution csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0) note a wait state may be generated when data is written to the buffer ram. for details, see chapter 36 cautions for wait . 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 536 jul 15, 2010 in 6-byte transmission/reception (atm0 = 0, rxea0 = 1, txea0 = 1, ate0 = 1) in automatic transmission/reception mode, internal buffer ram operates as follows. (i) starting automatic transmi ssion/reception (see figure 17-15) <1> when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0 and transmission/reception is started. <2> when transmission of the first byte is completed, the receive data 1 (r1) is transferred from sioa0 to the buffer ram, and automatic data transfer addr ess count register 0 (adtc0) is incremented. <3> next, transmit data 2 (t2) is transferred from the internal buffer to sioa0. figure 17-15. internal buffer ram operation in automatic transmi ssion/reception mode (starting transmission/reception) (1/2) <1> starting 1st byte transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h transmit data 1 (t1) data transmission 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 537 jul 15, 2010 figure 17-15. internal buffer ram operation in automatic transmi ssion/reception mode (starting transmission/reception) (2/2) <2> end of 1st byte transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 1 (r1) data reception +1 <3> starting of 2nd by te transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) receive data 1 (r1) 1 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 1 (r1) (ii) completion of transmissi on/reception (see figure 17-16) <1> when transmission/reception of t he sixth byte is completed, receiv e data 6 (r6) is transferred from sioa0 to the internal buffer ram and adtc0 is incremented. <2> when the value of adpt0 and that of adtc0 match, the autom atic transmission/reception ends, and an interrupt request flag (acsiif) is set (intac si is generated). adtc0 and bit 0 (tsf0) of serial status register 0 (csis0) are cleared to 0. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 538 jul 15, 2010 figure 17-16. internal buffer ram operation in automatic transmi ssion/reception mode (end of transmission/reception) <1> end of 6th byte transmission/reception transmit data 6 (t6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) 4 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) data reception +1 <2> end of automatic transmission/reception 5 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) receive data 6 (r6) match 5 1 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) receive data 6 (r6) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 539 jul 15, 2010 (b) automatic transmission mode in this mode, the specified data is transmitted in 8-bit unit. serial communication is started when bit 0 (atsta0) of se rial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), and bit 3 (txea0) of serial oper ation mode specification regi ster 0 (csima0) are set to 1. when the final byte has been transmitted, an interrupt request flag (acsiif) is set. the termination of automatic transmission can also be judged by bit 0 (tsf0) of serial status register 0 (csis0). if a receive operation, busy control and strobe control are not exec uted, the sia0/p143, busy0/buz/intp7/p141, and stb0/p145 pins can be used as normal i/o port pins. figure 17-17 shows the example of the automatic transmission mode operation timing, and figure 17-18 shows the operation flowchart. figure 17-17. example of automatic transmission mode operation timing scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 interval cautions 1. because, in the auto matic transmission mode, the auto matic transmit/receive function reads data from the internal buffer ram after 1- byte transmission, an interval is inserted until the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) ( see (5) automatic tran smit/receive interval time). 2. if an access to the buffer ram by the cp u conflicts with an access to the buffer ram by serial interface csia0 during the interval period, the interval time sp ecified by automatic data transfer interval specification register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 540 jul 15, 2010 figure 17-18. automatic tr ansmission mode flowchart start set csiae0 to 1 set the communication rate write transmit data in internal buffer ram note set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no tsf0 = 0 no end yes yes increment adtc0 software execution hardware execution software execution csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0) note a wait state may be generated when data is written to the buffer ram. for details, see chapter 36 cautions for wait . 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 541 jul 15, 2010 (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial communication is started when bit 0 (atsta0) of se rial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), bit 5 (atm0), and bit 3 (txea0) of serial operation mode specification register 0 (csima0) are set to 1. unlike the automatic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (acsiif) is not set, autom atic data transfer address count regist er 0 (adtc0) is reset to 0, and the internal buffer ram contents are transmitted again. when a reception operation, busy control and st robe control are not per formed, the sia0/p143, busy0/buz/intp7/p141, and st b0/p145 pins can be used as ordinary i/o port pins. the example of the repeat transmissi on mode operation timing is shown in figure 17-19, and the operation flowchart in figure 17-20. figure 17-19. example of repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 scka0 soa0 cautions 1. because, in the rep eat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon auto matic data transfer interval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (5) automati c transmit/receive interval time). 2. if an access to the buffer ram by the cp u conflicts with an access to the buffer ram by serial interface csia0 during the interval period, the interval time sp ecified by automatic data transfer interval specification register 0 (adti0) may be extended. 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 542 jul 15, 2010 figure 17-20. repeat transmission mode flowchart start set csiae0 to 1 set the communication rate write transmit data in internal buffer ram note set adtp0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes set the repeat transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no yes increment adtc0 software execution hardware execution reset adtc0 to 0 csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 note a wait state may be generated when data is written to the buffer ram. for details, see chapter 36 cautions for wait . 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 543 jul 15, 2010 (d) data format data is changed in synchronization with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data transfer di rection can be switched by the specification of bit 1 (dir0) of serial operation mode s pecification register 0 (csima0). figure 17-21. format of csia0 transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 544 jul 15, 2010 (e) automatic transmission/rece ption suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1. during 8-bit data communication, the transmission/ reception is not suspended. it is suspended upon completion of 8-bit data communication. when suspended, bit 0 (tsf0) of serial status register 0 (csis0) is cleared to 0 after transfer of the 8th bit. cautions 1. if the halt inst ruction is executed during automa tic transmission/reception, communication is suspended and the halt mode is set if during 8-bit data communication. when the halt mode is cl eared, automatic tran smission/reception is restarted from the suspended point. 2. when suspending automati c transmission/recepti on, do not change the operating mode to 3-wire serial i/o mode while tsf0 = 1. figure 17-22. automatic transmissi on/reception suspension and restart scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command (after each register setting, atsta0 = 1) suspend suspend command (atstp0 = 1) atstp0: bit 1 of serial trigger register 0 (csit0) atsta0: bit 0 of csit0 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 545 jul 15, 2010 (4) synchronization control busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. by using these functions, a shift in bits bei ng transmitted or received can be detected. (a) busy control option busy control is a function to keep the serial transmissi on/reception by the master device waiting while the busy signal output by a slave device to the master is active. when using this busy control option, the fo llowing conditions must be satisfied. ? bit 6 (ate0) of serial operation mode specif ication register 0 (csima0) is set to 1. ? bit 4 (busye0) of serial status register 0 (csis0) is set to 1. figure 17-23 shows the system confi guration of the master device and slave devic e when the busy control option is used. figure 17-23. system configuration when busy control option is used scka0 soa0 sia0 scka sia soa busy0 master device (78k0/kf2) slave device busy output the master device inputs the busy signal output by th e slave device to the busy0/buz/intp7/p141 pin. the master device samples the input busy signal in synchronizati on with the falling of the serial clock. even if the busy signal becomes active while 8-bit data is being tr ansmitted or received, transmission/reception by the master is not kept waiting. if the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. after that, the master transmission/reception is kept waiting while the busy signal is active. the active level of the busy signal is set by bit 3 (busylv0) of csis0. busylv0 = 1: active-high busylv0 = 0: active-low when using the busy control option, select the mast er mode. control with the busy signal cannot be implemented in the slave mode. figure 17-24 shows the example of the operati on timing when the busy control option is used. caution busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (adti0). 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 546 jul 15, 2010 figure 17-24. example of operation timing when bu sy control option is used (when busylv0 = 1) scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 tsf0 busy input released busy input valid wait remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) when the busy signal becomes inactive, waiting is re leased. if the sampled busy signal is inactive, transmission/reception of the next 8-bit data is start ed at the falling edge of the next serial clock. because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. it ta kes 0.5 clock until data transfe r is started after the busy signal was sampled. to accurately release the waiting, keep the busy si gnal inactive at the slave side, until scka0 falls. figure 17-25 shows the example of the timing of the busy signal and releasi ng the waiting. this figure shows an example in which the busy signal is active as soon as transmission/reception has been started. figure 17-25. busy signal and wa it release (when busylv0 = 1) scka0 d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 (active-high) 1.5 clocks (max.) busy input released busy input valid wait if made inactive immediately after sampled 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 547 jul 15, 2010 (b) busy & strobe control option strobe control is a function used to synchronize dat a transmission/reception between the master and slave devices. the master device outputs the str obe signal from the stb0/p145 pin when 8-bit transmission/reception has been completed. by this si gnal, the slave device can determine the timing of the end of data transmission. therefore, synchronization is es tablished even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of t he next byte is not affected by the bit shift. to use the strobe control opt ion, the following conditions must be satisfied: ? bit 6 (ate0) of the serial operation mode spec ification register 0 (csima0) is set to 1. ? bit 5 (stbe0) of serial status register 0 (csis0) is set to 1. usually, the busy control and strobe c ontrol options are simultaneously used as handshake signals. in this case, the strobe signal is output from the stb0 /p145 pin, the busy0/buz/intp7/p141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. a high level lasting for one transfer clock is output fr om the stb0/p145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. the busy signal is detec ted at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. figure 17-26 shows the example of the operation timi ng when the busy & strobe cont rol options are used. when the strobe control option is us ed, the interrupt request flag (acs iif) that is set on completion of transmission/reception is set after the strobe signal is output. figure 17-26. example of operation timing when busy & strobe control options are used (when busylv0 = 1) stb0 scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 tsf0 busy input released busy input valid caution when tsf0 is cleared, the soa0 pin goes low. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 548 jul 15, 2010 (c) bit shift detection by busy signal during automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal outpu t by the master device. unless the strobe control option is used at this time, the bit shift affects transmi ssion of the next byte. in this case, the master can detect the bit shift by checking the busy signal dur ing transmission by using the busy control option. a bit shift is detected by using the busy signal as follows: the slave outputs the busy signal after the rising of the eighth serial cl ock during data transmission/reception (to not keep transmission/reception wait ing by the busy signal at this time, make the busy signal inactive within 2 clocks). the master samples the busy signal in synchronizatio n with the falling edge of the serial clock if bit 2 (erre0) of serial status register 0 (csis0) is set to 1. if a bit shift does not occur, all the eight serial clocks that have been samp led are inactive. if the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (e rrf0) of serial status regi ster 0 (csis0) to 1, and communication is suspended and an interrupt request signal (intacsi) is output). although communication is suspended after completion of 1-byte data communica tion, slave signal output, wait due to the busy signal, and wait due to the in terval time specified by adti0 are not executed. if erre0 = 0, errf0 cannot become 1 even if a bit shift occurs. figure 17-27 shows the example of the operation timing of the bit shift detection function by the busy signal. figure 17-27. example of operation timing of bit shift detection function by busy signal (when busylv0 = 1) scka0 d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 acsiif csiae0 errf0 d7 d7 busy not detected error interrupt request generated error detected bit shift due to noise (slave) scka0 (master) acsiif: interrupt request flag csiae0: bit 7 of serial operation mode specification register 0 (csima0) errf0: bit 1 of serial status register 0 (csis0) 78k0/kx2 chapter 17 serial interface csia0 r01uh0008ej0401 rev.4.01 549 jul 15, 2010 (5) automatic transmit/receive interval time when using the automatic transmit/receive function, the read/write operations from/to the internal buffer ram are performed after transmitting/receiving one byte. therefore, an interval is inserted before the next transmit/receive operation. since the read/write operations from/to the buffer ra m are performed in parallel with the cpu processing when using the automatic transmit/receive function by the intern al clock, the interval depends on the value which is set in automatic data transfer interval specification regist er 0 (adti0) and bits 5 (stbe0) and 4 (busye0) of serial status register 0 (csis0). when adti0 is cleared to 00h, an interval time based on the to stbe0 and busye0 settings is inserted. if adti0 = 00h and stbe0 = busye0 = 1, for example, then an interval time of two clocks is inserted, and the interval time can be further extended by using an external busy signal. if an inte rval time of two clocks or more is set by using adti0, then the interval time set by ad ti0 is inserted, regardless of the settings of stbe0 and busye0. when busye0 = 1, the interval time can be further extended by an external busy signal. example interval time when adti0 = 00h and busy signal is not generated <1> when stbe0 = 1, busye0 = 0: interval time of two serial clocks is generated <2> when stbe0 = 0, busye0 = 1: interv al time of one serial clock is generated <3> when stbe0 = 1, busye0 = 1: interval time of two serial clocks is generated figure 17-28. example of interval ti me for automatic transmission/reception (when adti0 = 00h, stbe0 = 1, busye0 = 0 (two clocks)) interval scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif: interrupt request flag 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 550 jul 15, 2010 chapter 18 serial interface iic0 caution do not use serial interface iic0 and the mult iplier/divider simultaneously, because various flags corresponding to interrupt request sources ar e shared among serial interface iic0 and the multiplier/divider. remark the multiplier/divider is mounted onl y onto the 78k0/kx2 microcontroller pr oducts whose flash memory is at least 48 kb. 18.1 functions of serial interface iic0 serial interface iic0 are mounted onto all 78k0/kx2 microcontroller products. serial interface iic0 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generated ?start condition?, ?address?, ?transfer direction specificatio n?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects thes e received status and data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since the scl0 and sda0 pins are used for open drain output s, iic0 requires pull-up resistors for the serial clock line and the serial data bus line. figure 18-1 shows a block diagram of serial interface iic0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 551 jul 15, 2010 figure 18-1. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator bus status detector match signal iic shift register 0 (iic0) so latch iice0 dq set clear cl01, cl00 trc0 dfc0 dfc0 sda0/ p61 scl0/ p60 data hold time correction circuit start condition generator stop condition generator ack generator wake-up controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 iic shift register 0 (iic0) iicc0.stt0, spt0 iics0.msts0, exc0, coi0 iics0.msts0, exc0, coi0 f prs lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx0 iic clock selection register 0 (iiccl0) stcf iicbsy stcen iicrsv iic flag register 0 (iicf0) iic function expansion register 0 (iicx0) n-ch open- drain output pm61 output latch (p61) n-ch open- drain output pm60 output latch (p60) exscl0/ p62 remark the 78k0/kb2 products are no t mounted with the exscl0 pin. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 552 jul 15, 2010 figure 18-2 shows a serial bus configuration example. figure 18-2. serial bus c onfiguration example using i 2 c bus master cpu1 slave cpu1 address 0 sda0 scl0 serial data bus serial clock + v dd + v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 master cpu2 slave cpu2 address 1 slave cpu3 address 2 slave ic address 3 slave ic address n 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 553 jul 15, 2010 18.2 configuration of serial interface iic0 serial interface iic0 includes the following hardware. table 18-1. configuration of serial interface iic0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) port mode register 6 (pm6) port register 6 (p6) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. iic0 can be used for both transmission and reception. the actual transmit and receive operations can be contro lled by writing and reading operations to iic0. cancel the wait state and start data transfer by writing data to iic0 during the wait period. iic0 is set by an 8-bit memory manipulation instruction. reset signal generation clears iic0 to 00h. figure 18-3. format of iic shift register 0 (iic0) symbol iic0 address: ffa5h after reset: 00h r/w 76543210 cautions 1. do not write data to iic0 during data transfer. 2. write or read iic0 only during the wait pe riod. accessing iic0 in a communication state other than during the wait period is prohibited. when the device serves as the master, however, iic0 can be written only once after the communi cation trigger bit (stt0) is set to 1. 3. when communication is reser ved, write data to the iic0 regist er after the interrupt triggered by a stop condition is detected. (2) slave address register 0 (sva0) this register stores seven bits of local addresse s {a6, a5, a4, a3, a2, a1, a0} when in slave mode. this register can be set by an 8-bit memory manipulation instruction. however, rewriting to this register is prohibited wh ile std0 = 1 (while the start condition is detected). reset signal generation clears sva0 to 00h. figure 18-4. format of slave address register 0 (sva0) symbol sva0 address: ffa7h after reset: 00h r/w 76543210 0 note note bit 0 is fixed to 0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 554 jul 15, 2010 (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wake-up controller this circuit generates an interrupt request (intiic0) when the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or in put during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated by the following two triggers. ? falling edge of eighth or ninth clock of the serial clock (set by wtim0 bit) ? interrupt request generated when a stop cond ition is detected (set by spie0 bit) remark wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits generate and detect each status. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start conditi on when the stt0 bit is set to 1. however, in the communication reservat ion disabled status (iicrsv bit = 1) , when the bus is not released (iicbsy bit = 1), start condition requests are ignor ed and the stcf bit is set to 1. (13) stop condition generator this circuit generates a stop condition when the spt0 bit is set to 1. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 555 jul 15, 2010 (14) bus status detector this circuit detects whether or not the bus is releas ed by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcen bit. remark stt0 bit: bit 1 of iic control register 0 (iicc0) spt0 bit: bit 0 of iic control register 0 (iicc0) iicrsv bit: bit 0 of iic flag register 0 (iicf0) iicbsy bit: bit 6 of iic flag register 0 (iicf0) stcf bit: bit 7 of iic flag register 0 (iicf0) stcen bit: bit 1 of iic flag register 0 (iicf0) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 556 jul 15, 2010 18.3 registers to control serial interface iic0 serial interface iic0 is controlled by the following seven registers. ? iic control register 0 (iicc0) ? iic flag register 0 (iicf0) ? iic status register 0 (iics0) ? iic clock selection register 0 (iiccl0) ? iic function expansion register 0 (iicx0) ? port mode register 6 (pm6) ? port register 6 (p6) (1) iic control register 0 (iicc0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 register is set by a 1-bit or 8-bit memory manipu lation instruction. however, set the spie0, wtim0, and acke0 bits while iice0 bit = 0 or during the wait period. these bits can be set at the same time when the iice0 bit is set from ?0? to ?1?. reset signal generation clears iicc0 to 00h. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 557 jul 15, 2010 figure 18-5. format of iic control register 0 (iicc0) (1/4) address: ffa6h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stop operation. reset iic status register 0 (iics0) note 1 . stop internal operation. 1 enable operation. be sure to set this bit (1) while the scl0 and sda0 lines are at high level. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) ? cleared by instruction ? reset ? set by instruction lrel0 note s 2, 3 exit from communications 0 normal operation 1 this exits from the current communications and sets sta ndby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags of iic control register 0 (iicc0) and iic status register 0 (iics0) are cleared to 0. ? stt0 ? spt0 ? msts0 ? exc0 ? coi0 ? trc0 ? ackd0 ? std0 the standby mode following exit from communications remains in effect until the following co mmunications en try conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rece ption occurs after the start condition. condition for clearing (lrel0 = 0) condition for setting (lrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction wrel0 note s 2, 3 wait cancellation 0 do not cancel wait 1 cancel wait. this setting is automatic ally cleared after wait is canceled. when wrel0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (trc0 = 1), the sda0 line goes into the high impedance state (trc0 = 0). condition for clearing (wrel0 = 0) condition for setting (wrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, the st cf0 and iicbsy bits of the iicf0 register , and the cld0 and dad0 bits of the iiccl0 register are reset. 2. the signals of these bits are in valid while the iice0 bit is 0. 3. when the lrel0 and wrel0 bits are read, 0 is always read. caution if the operation of i 2 c is enabled (iice0 = 1) when the scl0 line is high level, the sda0 line is low level, and the digital filter is turned on (dfc0 of the iiccl0 register = 1), a start condition will be inadvertently detected immediately. in this case , set (1) the lrel0 bit by using a 1-bit memory manipulation instruction immediately after enabling operation of i 2 c (iice0 = 1). 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 558 jul 15, 2010 figure 18-5. format of iic control register 0 (iicc0) (2/4) spie0 note 1 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) condition for setting (spie0 = 1) ? cleared by instruction ? reset ? set by instruction wtim0 note 1 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, cloc k output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bi t. the setting of this bit is valid when the address transfer is comp leted. when in master mode, a wait is inserted at the fallin g edge of the ninth clock during address transfers. for a slave devi ce that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) condition for setting (wtim0 = 1) ? cleared by instruction ? reset ? set by instruction acke0 notes 1, 2 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda0 line is set to low level. condition for clearing (acke0 = 0) condition for setting (acke0 = 1) ? cleared by instruction ? reset ? set by instruction notes 1. this flag?s signal is invalid when iice0 = 0. 2. the set value is invalid during address transfer and if the code is not an extension code. when the device serves as a slave and the addresse s match, an acknowledge is generated regardless of the set value. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 559 jul 15, 2010 figure 18-5. format of iic control register 0 (iicc0) (3/4) stt0 note start condition trigger 0 do not generate a start condition. 1 when bus is released (in standby state, when iicbsy = 0): if this bit is set (1), a start conditi on is generated (startup as the master). when a third party is communicating: ? when communication reservation function is enabled (iicrsv = 0) functions as the start condition reservation flag. w hen set to 1, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsv = 1) even if this bit is set (1), the stt0 is cleared and the stt0 clear flag (stcf) is se t (1). no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be genera ted normally during the acknowledge period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as stop condition trigger (spt0). ? setting the stt0 bit to 1 and then setting it again before it is cleared to 0 is prohibited. condition for clearing (stt0 = 0) condition for setting (stt0 = 1) ? cleared by setting sst0 bit to 1 while communication reservation is prohibited. ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction note the signal of this bit is invalid while iice0 is 0. remarks 1. bit 1 (stt0) becomes 0 when it is read after data setting. 2. iicrsv: bit 0 of iic flag register (iicf0) stcf: bit 7 of iic flag register (iicf0) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 560 jul 15, 2010 figure 18-5. format of iic control register 0 (iicc0) (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device?s transfer). cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a stop condition cannot be generat ed normally during the acknowledge period. therefore, set it during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as start condition trigger (stt0). ? spt0 bit can be set to 1 only when in master mode. ? when wtim0 has been cleared to 0, if spt0 bit is set to 1 duri ng the wait period that follows output of eight clocks, note tha t a stop condition will be generated during the high-level period of the ninth clock. wtim0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and spt0 bit should be set to 1 during the wait period that follow s the output of the ninth clock. ? setting spt0 bit to 1 and then setting it again bef ore it is cleared to 0 is prohibited. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction caution when bit 3 (trc0) of the iic st atus register 0 (iics0) is set to 1 (transmission status), bit 5 (wrel0) of the iicc0 register is set to 1 during the ninth cl ock and wait is canceled, after which the trc0 bit is cleared (reception status) and the sda0 line is set to high impedance. re lease the wait performed while the trc bit is 1 (transmission status ) by writing to the iic shift register. remark bit 0 (spt0) becomes 0 when it is read after data setting. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 561 jul 15, 2010 (2) iic status register 0 (iics0) this register indicates the status of i 2 c. iics0 is read by a 1-bit or 8-bit memory manipulation in struction only when stt0 = 1 and during the wait period. reset signal generation clears iics0 to 00h. caution if data is read from iics0 re gister, a wait cycle is generated. do not read data from iics0 register when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. figure 18-6. format of iic status register 0 (iics0) (1/3) address: ffaah after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) ? when a stop condition is detected ? when ald0 = 1 (arbitration loss) ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration re sult was a ?loss?. msts0 bit is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) ? automatically cleared after iics0 register is read note ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a 1-bit memory m anipulation instruction is ex ecuted for bits other than iics0 register. therefore, when using the ald0 bit, read the data of this bit before the data of the other bits. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 562 jul 15, 2010 figure 18-6. format of iic status register 0 (iics0) (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (slave address register 0 (sva0)) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is ena bled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 563 jul 15, 2010 figure 18-6. format of iic status register 0 (iics0) (3/3) ackd0 detection of acknowledge (ack) 0 acknowledge was not detected. 1 acknowledge was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? after the sda0 line is set to low level at the rising edge of ninth clock of scl0 line std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 = 0) condition for setting (std0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s co mmunication is terminated and the bus is released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) (3) iic flag register 0 (iicf0) this register sets the operation mode of i 2 c and indicates the status of the i 2 c bus. this register can be set by a 1-bit or 8-bit memory mani pulation instruction. however, the stt0 clear flag (stcf) and i 2 c bus status flag (iicbsy) are read-only. the iicrsv bit can be used to enable/disabl e the communication reservation function. the stcen bit can be used to set the initial value of the iicbsy bit. the iicrsv and stcen bits can be wr itten only when the operation of i 2 c is disabled (bit 7 (iice0) of the iic control register 0 (iicc0) = 0). when operati on is enabled, the iicf0 register can be read. reset signal generation clea rs this register to 00h. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 564 jul 15, 2010 figure 18-7. format of iic flag register 0 (iicf0) <7> stcf condition for clearing (stcf = 0) ? cleared by stt0 = 1 ? when iice0 = 0 (operation stop) ? reset condition for setting (stcf = 1) ? generating start condition unsuccessful and stt0 bit cleared to 0 when communication reservation is disabled (iicrsv = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag stt0 clear flag iicf0 symbol <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv address: ffabh after reset: 00h r/w note condition for clearing (iicbsy = 0) ? detection of stop condition ? when iice0 = 0 (operation stop) ? reset condition for setting (iicbsy = 1) ? detection of start condition ? setting of iice0 bit when stcen = 0 iicbsy 0 1 bus release status (communication initial status when stcen = 1) bus communication status (communication initial status when stcen = 0) i 2 c bus status flag condition for clearing (stcen = 0) ? detection of start condition ? reset condition for setting (stcen = 1) ? set by instruction stcen 0 1 after operation is enabled (iice0 = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv = 0) ? cleared by instruction ? reset condition for setting (iicrsv = 1) ? set by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only. cautions 1. write to stcen bit only when the operation is stopped (iice0 = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating the first st art condition (stt0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to iicrsv bit only when the operation is stopped (iice0 = 0). remark stt0: bit 1 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 565 jul 15, 2010 (4) iic clock selection register 0 (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 is set by a 1-bit or 8-bit memory manipulation instru ction. however, the cld0 and dad0 bits are read-only. the smc0, cl01, and cl00 bits are set in combination with bit 0 (clx0) of iic function expansion register 0 (iicx0) (see 18.3 (6) i 2 c transfer clock setting method ). set iiccl0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation clears iiccl0 to 00h. figure 18-8. format of iic clock selection register 0 (iiccl0) address: ffa8h after reset: 00h r/w note symbol 7 6 <5> <4> <3> <2> 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iice0 = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) ? when the scl0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad0 detection of sda0 pin level (valid only when iice0 = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) ? when the sda0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not va ry regardless of dfc0 bit set (1)/clear (0). the digital filter is used for noise elimination in high-speed mode. note bits 4 and 5 are read-only. remark iice0: bit 7 of iic control register 0 (iicc0) 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 566 jul 15, 2010 (5) iic function expansi on register 0 (iicx0) this register sets the function expansion of i 2 c. iicx0 is set by a 1-bit or 8-bit memory manipulation instruct ion. the clx0 bit is set in combination with bits 3, 1, and 0 (smc0, cl01, and cl00) of iic clo ck selection register 0 (iiccl0) (see 18.3 (6) i 2 c transfer clock setting method ). set iicx0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation clears iicx0 to 00h. figure 18-9. format of iic functi on expansion register 0 (iicx0) address: ffa9h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 (6) i 2 c transfer clock setting method the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 44, 66, 86 (see table 18-2 selection clock setting ) t: 1/f w t r : scl0 rise time t f : scl0 fall time for example, the i 2 c transfer clock frequency (f scl ) when f w = f prs /2 = 4.19 mhz, m = 86, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(88 238.7 ns + 200 ns + 50 ns) ? 48.1 khz m t + t r + t f m/2 t m/2 t t f t r scl0 scl0 inversion scl0 inversion scl0 inversion 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 567 jul 15, 2010 the selection clock is set using a combination of bits 3, 1, and 0 (smc0, cl01, and cl00) of iic clock selection register 0 (iiccl0) and bit 0 (clx0) of iic function expansion register 0 (iicx0). table 18-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock (f w ) notes 1, 2 transfer clock (f w /m) settable selection clock (f w ) range operation mode 0 0 0 0 f prs /2 f w /44 2.00 to 4.19 mhz 0 0 0 1 f prs /2 f w /86 0 0 1 0 f prs /4 f w /86 4.19 to 8.38 mhz 0 0 1 1 f exscl0 notes 3, 4 f w /66 6.4 mhz normal mode (smc0 bit = 0) 0 1 0 f prs /2 f w /24 0 1 1 0 f prs /4 f w /24 4.00 to 8.38 mhz 0 1 1 1 f exscl0 note 3, 4 f w /18 6.4 mhz high-speed mode (smc0 bit = 1) 1 0 setting prohibited 1 1 0 f prs /2 f w /12 1 1 1 0 f prs /4 f w /12 4.00 to 4.19 mhz high-speed mode (smc0 bit = 1) 1 1 1 1 setting prohibited notes 1. the frequency that can be used for t he peripheral hardware clock (f prs ) differs depending on the power supply voltage and product specifications. supply voltage conventional-specification products ( pd78f05xx and 78f05xxd) expanded-specification products ( pd78f05xxa and 78f05xxda) 4.0 v v dd 5.5 v f prs 20 mhz 2.7 v v dd < 4.0 v f prs 10 mhz f prs 20 mhz 1.8 v v dd < 2.7 v (standard products and (a) grade products only) f prs 5 mhz f prs 5 mhz (the values shown in the table above are those when f prs = f xh (xsel = 1).) 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f xh ) (xsel = 0), set clx0, smc0, cl01 and cl00 as follows. iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock (f w ) transfer clock (f w /m) settable selection clock (f w ) range operation mode 0 0 0 0 f prs /2 f w /44 normal mode (smc0 bit = 0) 0 1 0 f prs /2 f w /24 3.8 mhz to 4.2 mhz high-speed mode (smc0 bit = 1) 3. this must not be set, because the 78k0/kb2 pr oducts are not mounted with the exscl0 pin. 4. do not start communication with t he external clock from the exscl0 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the cpu operates with the subsystem clock, or when in the stop mode. caution determine the transfer clock frequency of i 2 c by using clx0, smc0, cl01, and cl00 before enabling the operation (by setting bit 7 (iice0 ) of iic control register 0 (iicc0) to 1). to change the transfer clock frequency, clear iice0 once to 0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 568 jul 15, 2010 remarks 1. : don?t care 2 . f prs : peripheral hardware clock frequency 3 . f exscl0 : external clock frequency from exscl0 pin (7) port mode register 6 (pm6) this register sets the input/output of port 6 in 1-bit units. when using the p60/scl0 pin as cloc k i/o and the p61/sda0 pin as serial data i/o, clear pm60 and pm61, and the output latches of p60 and p61 to 0. set iice0 (bit 7 of iic control register 0 (iicc0)) to 1 before setting the output m ode because the p60/scl0 and p61/sda0 pins output a low level (fixed) when iice0 is 0. pm6 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generati on sets pm6 to ffh. figure 18-10. format of port mode register 6 (pm6) pm60 pm61 pm62 pm63 pm64 pm65 pm66 pm67 p6n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm6n 0 1 0 1 2 3 4 5 6 7 pm6 address: ff26h after reset: ffh r/w symbol remark the figure shown above presents the format of port mode register 6 of 78k0/kf2 products. for the format of port mode register 6 of other products, see (1) port mode registers (pmxx) in 5.3 registers controlling port function . 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 569 jul 15, 2010 18.4 i 2 c bus mode functions 18.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0....... this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 ...... this pin is used fo r serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial da ta bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 18-11. pin configuration diagram master device clock output (clock input) data output data input v ss v ss scl0 sda0 v dd v dd (clock output) clock input data output data input v ss v ss slave device scl0 sda0 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 570 jul 15, 2010 18.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 18-12 shows the transfer timing for the ?start conditi on?, ?address?, ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus. figure 18-12. i 2 c bus serial data transfer timing scl0 sda0 start condition address r/w ack data 1-7 8 9 1-8 ack data ack stop condition 9 1-8 9 the master device generates the start c ondition, slave address, and stop condition. the acknowledge (ack) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. howeve r, in the slave device, the scl0?s low level period can be extended and a wait can be inserted. 18.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device generates to the slave device when starting a serial transfer. when the device is us ed as a slave, start conditions can be detected. figure 18-13. start conditions scl0 sda0 h a start condition is output when bit 1 (stt0) of iic control r egister 0 (iicc0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in iic status re gister 0 (iics0)). when a start condition is detected, bit 1 (std0) of iics0 is set (to 1). 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 571 jul 15, 2010 18.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via the bus lines. theref ore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware t hat detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in slave address register 0 ( sva0). if the address data matc hes the sva0 register values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. figure 18-14. address scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which spec ifies the transfer direction as described in 18.5.3 transfer direction specification below, are together written to iic shift register 0 (iic0) and are then output. re ceived addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0 register. 18.5.3 transfer di rection specification in addition to the 7-bit address data, the master device s ends 1 bit that specifies t he transfer direction. when this transfer direction spec ification bit has a value of ?0?, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of ?1?, it indicate s that the master device is receiving data from a slave device. figure 18-15. transfer direction specification scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 572 jul 15, 2010 18.5.4 acknowledge (ack) ack is used to check the status of serial data at the transmission and reception sides. the reception side returns ack each time it has received 8-bit data. the transmission side usually receives ack after transmitting 8- bit data. when ack is returned from the reception side, it is assumed that reception has been correctly performed a nd processing is continued. whether ack has been detected can be checked by using bit 2 (ackd0) of iic status register 0 (iics0). when the master receives the last data item, it does not return ack and instead ge nerates a stop condition. if a slave does not return ack after receiving data, the master outputs a stop condition or restart condit ion and stops transmission. if ack is not returned, the possible causes are as follows. <1> reception was not performed normally. <2> the final data item was received. <3> the reception side specified by the address does not exist. to generate ack, the reception side makes the sda0 line low at the ninth clock (indicating normal reception). automatic generation of ack is enabled by setting bit 2 (acke0) of iic control register 0 (iicc0) to 1. bit 3 (trc0) of the iics0 register is set by the data of the eighth bit that follows 7-bit address in formation. usually, se t acke0 bit to 1 fo r reception (trc0 = 0). if a slave can receive no more data during reception (trc0 = 0) or does not require the next data item, then the slave must inform the master, by clearing acke0 bit to 0, that it will not receive any more data. when the master does not require the next data item during rec eption (trc0 = 0), it must cl ear acke0 bit to 0 so that ack is not generated. in this way, the master informs a slav e at the transmission side that it does not require any more data (transmission will be stopped). figure 18-16. ack scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, ack is automatically generated, regardless of the value of acke0 bit. when an address other than that of t he local address is received, ack is not generated (nack). when an extension code is received, ack is generated if acke0 bit is set to 1 in advance. how ack is generated when data is received differs as follows depending on the setting of the wait timing. ? when 8-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 0): by setting acke0 bit to 1 before releasing the wait state, ack is generated at the falling edge of the eighth clock of the scl0 pin. ? when 9-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 1): ack is generated by setting acke0 bit to 1 in advance. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 573 jul 15, 2010 18.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device generates to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 18-17. stop condition scl0 sda0 h a stop condition is generated when bit 0 (spt 0) of iic control register 0 (iicc0) is set to 1. when the stop condition is detected, bit 0 (spd0) of iic status r egister 0 (iics0) is set to 1 and intiic0 is generated when bit 4 (spie0) of iicc0 register is set to 1. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 574 jul 15, 2010 18.5.6 wait the wait is used to notify the communicati on partner that a device (mast er or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifie s the communication partner of the wait state. when wait state has been canceled for both the master and slave devices, the next data transfer can begin. figure 18-18. wait (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) wait after output of eighth clock wait from slave wait from master ffh is written to iic0 or wrel0 is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 575 jul 15, 2010 figure 18-18. wait (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait from master and slave wait from slave iic0 data write (cancel wait) ffh is written to iic0 or wrel0 is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 generate according to previously set acke0 value remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, the receiving side cancels the wait state when bit 5 (wrel0) of iicc0 register is set to 1 or when ffh is written to iic shift register 0 (iic0), and the transmitting side cancels the wait state when dat a is written to iic0 register. the master device can also cancel the wait state via either of the following methods. ? by setting bit 1 (stt0) of iicc0 register to 1 ? by setting bit 0 (spt0) of iicc0 register to 1 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 576 jul 15, 2010 18.5.7 canceling wait the i 2 c usually cancels a wait stat e by the following processing. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only when the above wait canceling processing is executed, the i 2 c cancels the wait state and communication is resumed. to cancel a wait state and transmit data (including addresses), write the data to iic0 register. to receive data after canceling a wait state, or to comp lete data transmission, set bit 5 (wrel0) of the iic0 control register 0 (iicc0) to 1. to generate a restart condition after canceling a wait state, set bit 1 (stt0) of iicc0 register to 1. to generate a stop condition after canceling a wait st ate, set bit 0 (spt0) of iicc0 register to 1. execute the canceling processing only once for one wait state. if, for example, data is written to iic0 register after cancelin g a wait state by setting wrel0 bit to 1, an incorrect value may be output to sda0 line because the timing for changing the sda0 line conflicts with the ti ming for writing iic0 register. in addition to the above, communication is stopped if iice0 bit is cleared to 0 when communication has been aborted, so that the wait st ate can be canceled. if the i 2 c bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (lrel0) of iicc0 register, so that the wait state can be canceled. 18.5.8 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) of iic control register 0 (iic c0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown in table 18-3. table 18-3. intiic0 generation timing and wait control during slave device operation during master device operation wtim0 address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is generated regardless of the value set to bit 2 (acke0) of the iicc0 register. for a slave device that has received an extension code, intiic 0 occurs at the falling edge of the eighth clock. however, if the address does not match after restart, in tiic0 is generated at the fa lling edge of the 9th clock, but wait does not occur. 2. if the received address does not matc h the contents of slave address regi ster 0 (sva0) and extension code is not received, neither intiic0 nor a wait occurs. remark the numbers in the table indicate t he number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 577 jul 15, 2010 (1) during address transmission/reception ? slave device operation: interrupt and wait timi ng are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim0 bit. ? master device operation: interrupt and wait timing oc cur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only. when an 8-clock wait has been selected (wtim0 = 0), the presence/absence of ack generation must be determined prior to wait cancellation. (5) stop condition detection intiic0 is generated when a stop condit ion is detected (only when spie0 = 1). 18.5.9 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by trans mitting the corresponding slave address. address match can be detected automatically by hardware. an interrupt request (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.10 error detection in i 2 c bus mode, the status of the serial dat a bus (sda0) during data transmission is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission erro r is judged as having occurred when the compared data values do not match. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 578 jul 15, 2010 18.5.11 extension code (1) when the higher 4 bits of the receive address are either ?0000? or ?1111?, the extension code reception flag (exc0) is set to 1 for extension code reception and an interrupt r equest (intiic0) is issued at t he falling edge of the eighth clock. the local address stored in slave ad dress register 0 (sva0) is not affected. (2) if ?11110 0? is set to sva0 register by a 10-bit address transfer and ?11110 0? is transferred from the master device, the results are as follows. note that in tiic0 occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc0 = 1 ? seven bits of data match: coi0 = 1 remark exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs di ffers according to the data that follows the extension code, such processing is performed by software. if the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (lrel0) of the iic control register 0 (iicc0) to 1 to set the standby mode for the next communication operation. table 18-4. bit definitions of main extension code slave address r/w bit description 0 0 0 0 0 0 0 0 general call address 1 1 1 1 0 x x 0 10-bit slave address sp ecification (for address authentication) 1 1 1 1 0 x x 1 10-bit slave address specification (for read command issuance after address match) remark for extension codes other than the above, refer to the i 2 c-bus specification published by nxp. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 579 jul 15, 2010 18.5.12 arbitration when several master devices simultaneously generate a start c ondition (when stt0 is set to 1 before std0 is set to 1), communication among the master devices is performed as the num ber of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in ar bitration, an arbitration loss flag (ald0) in iic status register 0 (iics0) is set (1) via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on th e timing of the next interrupt request (t he eighth or ninth clock, when a stop condition is detected, etc.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 18.5.17 timing of i 2 c interrupt request (intiic0) occurrence . remark std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0) figure 18-19. arbitration timing example scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 loses arbitration master 1 master 2 transfer lines 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 580 jul 15, 2010 table 18-5. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data transmission when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a stop condition when scl0 is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim0 bit (bit 3 of iic control register 0 (iicc0 )) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that ar bitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 4 of iic control register 0 (iicc0) 18.5.13 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signal (intiic0) when a local address and extension code have been received. this function makes processing more efficient by prev enting unnecessary intiic0 signal from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbi tration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detected, bit 4 (spie0) of iic control register 0 (iicc0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 581 jul 15, 2010 18.5.14 communication reservation (1) when communication reservation func tion is enabled (bit 0 (iicrsv) of iic flag register 0 (iicf0) = 0) to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. if an address is written to iic shift register 0 (iic0) after bi t 4 (spie0) of iicc0 was set to 1, and it was detected by generation of an interrupt request signal (intiic0) that the bus was released ( detection of the stop condition), then the device automatically starts communication as the mast er. data written to iic0 before the stop condition is detected is invalid. when stt0 has been set to 1, the operation mode (as st art condition or as communication reservation) is determined according to the bus status. ? if the bus has been released ........................................ a start c ondition is generated ? if the bus has not been released (stand by mode)......... communication reservation check whether the communication reservation operates or not by using msts0 bit (bit 7 of iic status register 0 (iics0)) after stt0 bit is set to 1 and the wait time elapses. the wait periods, which should be set via software, are listed in table 18-6. table 18-6. wait periods clx0 smc0 cl01 cl00 wait period 0 0 0 0 46 clocks 0 0 0 1 86 clocks 0 0 1 0 172 clocks 0 0 1 1 34 clocks 0 1 0 0 0 1 0 1 30 clocks 0 1 1 0 60 clocks 0 1 1 1 12 clocks 1 1 0 0 1 1 0 1 18 clocks 1 1 1 0 36 clocks figure 18-20 shows the communication reservation timing. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 582 jul 15, 2010 figure 18-20. communication reservation timing 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 = 1 communi- cation reservation set std0 generate by master device with bus mastership remark iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following ti ming. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected. figure 18-21. timing for accep ting communication reservations scl0 sda0 std0 spd0 standby mode figure 18-22 shows the communication reservation protocol. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 583 jul 15, 2010 figure 18-22. communication reservation protocol di set1 stt0 define communication reservation wait msts0 = 0? (communication reservation) note yes no (generate start condition) cancel communication reservation mov iic0, # h ei sets stt0 flag (communication reservation) defines that communication reservation is in effect (defines and sets user flag to any part of ram) secures wait period set by software (see table 18-6 ). confirmation of communication reservation clear user flag iic0 write operation note the communication reservation operation executes a write to iic shift regi ster 0 (iic0) when a stop condition interrupt request occurs. remark stt0: bit 1 of iic control register 0 (iicc0) msts0: bit 7 of iic status register 0 (iics0) iic0: iic shift register 0 (2) when communication reservation function is disabled (b it 0 (iicrsv) of iic flag register 0 (iicf0) = 1) when bit 1 (stt0) of iic control register 0 (iicc0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start cond ition is not generated. the following two statuses are included in the status where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iicc0 register was set to 1) to confirm whether the start condition was generated or request was rejected, check stcf flag (bit 7 of iicf0). the time shown in table 18-7 is required until stcf flag is set to 1 after setting stt0 = 1. therefore, secure the time by software. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 584 jul 15, 2010 table 18-7. wait periods cl01 cl00 wait period 0 0 6 clocks 0 1 6 clocks 1 0 12 clocks 1 1 3 clocks 18.5.15 cautions (1) when stcen (bit 1 of iic flag register 0 (iicf0)) = 0 immediately after i 2 c operation is enabled (iice0 = 1), the bus co mmunication status (iicbsy flag (bit 6 of iicf0) = 1) is recognized regardless of the ac tual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to per form master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iic clock selection register 0 (iiccl0). <2> set bit 7 (iice0) of iic c ontrol register 0 (iicc0) to 1. <3> set bit 0 (spt0) of iicc0 to 1. (2) when stcen = 1 immediately after i 2 c operation is enabled (iice0 = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the firs t start condition (stt0 (bit 1 of iic control register 0 (iicc0)) = 1), it is necessary to confirm that the bus ha s been released, so as to not disturb other communications. (3) if other i 2 c communications are already in progress if i 2 c operation is enabled and the device part icipates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time can be re cognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie0) of iicc0 register to 0 to disa ble generation of an interrupt request signal (intiic0) when the stop condition is detected. <2> set bit 7 (iice0) of iicc0 register to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel0) of iicc0 register to 1 before ack is returned (4 to 80 clocks afte r setting iice0 bit to 1), to forcibly disable detection. (4) determine the transfer clock frequency by using smc0, cl01, cl00 bits (bits 3, 1, and 0 of iicl0 register), and clx0 bit (bit 0 of iicx0 register) before enabling the ope ration (iice0 = 1). to change the transfer clock frequency, clear iice0 bit to 0 once. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 585 jul 15, 2010 (5) setting stt0 and spt0 bits (bits 1 and 0 of iicc0 registe r) again after they are set and before they are cleared to 0 is prohibited. (6) when transmission is reserved, set spie0 bit (bit 4 of ii cl0 register) to 1 so that an interrupt request is generated when the stop condition is detected. trans fer is started when communication data is written to iic status register 0 (iics0) after the interrupt request is generated. unle ss the interrupt is generated when the stop condition is detected, the device stops in the wait state because t he interrupt request is not generated when communication is started. however, it is not necessary to set spie0 bit to 1 when msts0 bit (bit 7 of iic status register 0 (iics0) is detected by software. 18.5.16 communication operations the following shows three operatio n procedures with the flowchart. (1) master operation in single master system the flowchart when using the 78k0/kx2 microcontrollers as the master in a single master system is shown below. this flowchart is broadly divided into the initial settings and communication processing. execute the initial settings at startup. if communication wit h the slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the 78k0/kx2 microcontrollers takes part in a communication with bus released state. this flowchart is broadly divided into the initial settings , communication waiting, and communication processing. the processing when the 78k0/kx2 microcontrollers looses in arbitration and is specifi ed as the slave is omitted here, and only the processing as the ma ster is shown. execute the initial settings at startup to take part in a communication. then, wait for the communication request as t he master or wait for the s pecification as the slave. the actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) slave operation an example of when the 78k0/kx2 microcontrollers is used as the i 2 c bus slave is shown below. when used as the slave, operation is star ted by an interrupt. execute the initial settings at startup, then wait for the intiic0 interrupt occurrence (communication waiting). when an intiic0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 586 jul 15, 2010 (1) master operation in single-master system figure 18-23. master operation in single-master system spt0 = 1 spt0 = 1 wrel0 = 1 start end acke0 = 0 wtim0 = wrel0 = 1 no no yes no no no yes yes yes yes stcen = 1? acke0 = 1 wtim0 = 0 trc0 = 1? ackd0 = 1? ackd0 = 1? no yes no yes yes no yes no yes no yes no yes no stt0 = 1 iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen, iicrsv = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port initializing i 2 c bus note sva0 xxh writing iic0 writing iic0 reading iic0 intiic0 interrupt occurs? end of transfer? end of transfer? restart? sets each pin in the i 2 c mode (see 18.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. prepares for starting communication (generates a start condition). starts communication (specifies an address and transfer direction). waits for detection of acknowledge. waits for data transmission. starts transmission. communication processing initial setting starts reception. waits for data reception. intiic0 interrupt occurs? waits for detection of acknowledge. prepares for starting communication (generates a stop condition). waits for detection of the stop condition. intiic0 interrupt occurs? intiic0 interrupt occurs? intiic0 interrupt occurs? note release (scl0 and sda0 pins = high level) the i 2 c bus in conformance with the specifications of the product that is communicating. if eeprom is outputting a low le vel to the sda0 pin, for example, set the scl0 pin in the output port mode, and output a clock pu lse from the output port until the sda0 pin is constantly at high level. remark conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 587 jul 15, 2010 (2) master operation in multi-master system figure 18-24. master operation in multi-master system (1/3) iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen and iicrsv iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port spt0 = 1 sva0 xxh spie0 = 1 start slave operation slave operation releases the bus for a specific period. bus status is being checked. yes checking bus status note master operation starts? enables reserving communication. disables reserving communication. spd0 = 1? stcen = 1? iicrsv = 0? a sets each pin in the i 2 c mode (see 18.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. (communication start request) (no communication start request) prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiic0 interrupt occurs? intiic0 interrupt occurs? yes no yes no spd0 = 1? yes no slave operation no intiic0 interrupt occurs? yes no 1 b spie0 = 0 yes no waits for a communication request. waits for a communication initial setting ? waiting to be specified as a slave by other master ? waiting for a communication start request (depends on user program) note confirm that the bus is released (cld0 bit = 1, dad0 bit = 1) for a specific period (for example, for a period of one frame). if the sda0 pin is constantly at low level, decide whether to release the i 2 c bus (scl0 and sda0 pins = high level) in conformance with the specif ications of the product that is communicating. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 588 jul 15, 2010 figure 18-24. master operation in multi-master system (2/3) stt0 = 1 wait slave operation yes msts0 = 1? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). secure wait time by software (see table 18-6 ). waits for bus release (communication being reserved). wait state after stop condition was detected and start condition was generated by the communication reservation function. no intiic0 interrupt occurs? yes yes no no a c stt0 = 1 wait slave operation yes iicbsy = 0? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). disables reserving communication. enables reserving communication. secure wait time by software (see table 18-7 ). waits for bus release detects a stop condition. no no intiic0 interrupt occurs? yes yes no yes stcf = 0? no b d c d communication processing communication processing 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 589 jul 15, 2010 figure 18-24. master operation in multi-master system (3/3) writing iic0 wtim0 = 1 wrel0 = 1 reading iic0 acke0 = 1 wtim0 = 0 wtim0 = wrel0 = 1 acke0 = 0 writing iic0 yes trc0 = 1? restart? msts0 = 1? starts communication (specifies an address and transfer direction). starts transmission. no yes waits for data reception. starts reception. yes no intiic0 i nterrupt occurs? yes no transfer end? waits for detection of ack. yes no intiic0 i nterrupt occurs? waits for data transmission. does not participate in communication. yes no intiic0 i nterrupt occurs? no yes ackd0 = 1? no yes no c 2 yes msts0 = 1? no yes transfer end? no yes ackd0 = 1? no 2 yes msts0 = 1? no 2 waits for detection of ack. yes no intiic0 i nterrupt occurs? yes msts0 = 1? no c 2 yes exc0 = 1 or coi0 = 1? no 1 2 spt0 = 1 stt0 = 1 slave operation end communication processing communication processing remarks 1. conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. to use the device as a master in a multi-master system, read the msts0 bit each time interrupt intiic0 has occurred to check the arbitration result. 3. to use the device as a slave in a multi-master system, check the status by using the iics0 and iicf0 registers each time interrupt intiic0 has occurred, and determine the processing to be performed next. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 590 jul 15, 2010 (3) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefore, processing by the intiic0 interrupt (processing that must substantially change the operation st atus such as detection of a stop c ondition during communication) is necessary. in the following explanation, it is a ssumed that the extension c ode is not supported for data communication. it is also assumed that the intiic0 interrupt servicing only pe rforms status transition proc essing, and that actual data communication is performed by the main processing. iic0 interrupt servicing main processing intiic0 flag setting data setting therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of intiic0. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data commun ication is performed (from valid address detection to stop condition detection, no detection of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiic0 interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communicati on is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communic ation. its value is the same as trc0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 591 jul 15, 2010 the main processing of the slave operation is explained next. start serial interface iic0 and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. he re, check the status by using the flags). the transmission operation is repeated unt il the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after that, the master generates a stop condition or restart condition. exit from the communication status occurs in this way. figure 18-25. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no wrel0 = 1 ackd0 = 1? no yes no yes no start communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? reading iic0 clearing ready flag clearing ready flag communication direction flag = 1? clearing communication mode flag wrel0 = 1 writing iic0 iicc0 xxh acke0 = wtim0 = 1 spie0 = 0, iice0 = 1 sva0 xxh sets a local address. iicx0 0xh iiccl0 xxh selects a transfer clock. iicf0 0xh setting iicrsv sets a start condition. starts transmission. starts reception. communication mode flag = 1? ready flag = 1? setting port sets each pin to the i 2 c mode (see 18.3 (7) port mode register 6 (pm6) ). communication processing initial setting remark conform to the specifications of the product t hat is in communication, regarding the transmission and reception formats. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 592 jul 15, 2010 an example of the processing procedure of the slave wit h the intiic0 interrupt is explained below (processing is performed assuming that no extension code is used). th e intiic0 interrupt checks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is che cked and communication is completed if the address does not match. if the address matches, the communication mo de is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the i 2 c bus remaining in the wait state. remark <1> to <3> above correspond to <1> to <3> in figure 18-26 slave operation flowchart (2) . figure 18-26. slave operation flowchart (2) yes yes yes no no no intiic0 generated set ready flag interrupt servicing completed spd0 = 1? std0 = 1? coi0 = 1? communication direction flag trc0 set communication mode flag clear ready flag clear c ommunication direction flag, ready flag, and communication mode flag <1> <2> <3> 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 593 jul 15, 2010 18.5.17 timing of i 2 c interrupt request (intiic0) occurrence the timing of transmitting or receiving data and generation of interrupt request signal in tiic0, and the value of the iics0 register when the intiic0 signal is generated are shown below. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 594 jul 15, 2010 (1) master device operation (a) start ~ address ~ data ~ data ~ stop (transmission/reception) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b 3: iics0 = 1000000b (sets wtim0 to 1 note ) 4: iics0 = 100000b (sets spt0 to 1) 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b 3: iics0 = 100000b (sets spt0 to 1) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 595 jul 15, 2010 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 7 2 1 5 6 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1 note 1 ) 3: iics0 = 100000b (clears wtim0 to 0 note 2 , sets stt0 to 1) 4: iics0 = 1000110b 5: iics0 = 1000000b (sets wtim0 to 1 note 3 ) 6: iics0 = 100000b (sets spt0 to 1) 7: iics0 = 00000001b notes 1. to generate a start condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. 2. clear wtim0 to 0 to restore the original setting. 3. to generate a stop condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 1000110b 4: iics0 = 100000b (sets spt0 to 1) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 596 jul 15, 2010 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1010110b 2: iics0 = 1010000b 3: iics0 = 1010000b (sets wtim0 to 1 note ) 4: iics0 = 101000b (sets spt0 to 1) 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1010110b 2: iics0 = 1010100b 3: iics0 = 101000b (sets spt0 to 1) 4: iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 597 jul 15, 2010 (2) slave device operation (slave address data reception) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 598 jul 15, 2010 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0001110b 4: iics0 = 000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 599 jul 15, 2010 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 5 6 2 1 4 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0010010b 4: iics0 = 0010110b 5: iics0 = 001000b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 600 jul 15, 2010 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 601 jul 15, 2010 (3) slave device operation (w hen receiving extension code) the device is always participating in communication when it receives an extension code. (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 602 jul 15, 2010 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 6 2 1 5 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0001110b 5: iics0 = 000100b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 603 jul 15, 2010 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 7 2 1 5 6 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0010010b 5: iics0 = 0010110b 6: iics0 = 001000b 7: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 604 jul 15, 2010 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 00100010b 2: iics0 = 00100000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 00100010b 2: iics0 = 00100110b 3: iics0 = 0010000b 4: iics0 = 00000110b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 605 jul 15, 2010 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 1 1: iics0 = 00000001b remark : generated only when spie0 = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) when the device is used as a master in a multi-master system, read the msts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occurs durin g transmission of slave address data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 606 jul 15, 2010 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (b) when arbitration loss occurs dur ing transmission of extension code (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0110010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 607 jul 15, 2010 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0110010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (6) operation when arbitration loss occurs (no communication after arbitration loss) when the device is used as a master in a multi-master system, read the msts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occu rs during transmission of slave address data (when wtim0 = 1) st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 01000110b 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 608 jul 15, 2010 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 0110010b sets lrel0 = 1 by software 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (c) when arbitration loss occu rs during transmission of data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000000b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 609 jul 15, 2010 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000100b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (d) when loss occurs due to rest art condition during data transfer (i) not extension code (example: unmatches with sva0) st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01000110b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 610 jul 15, 2010 (ii) extension code st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01100010b sets lrel0 = 1 by software 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 (e) when loss occurs due to st op condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 2 1 1: iics0 = 10000110b 2: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 611 jul 15, 2010 (f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets stt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 612 jul 15, 2010 (g) when arbitration loss occurs due to a stop cond ition when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 100000b (sets stt0 to 1) 4: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 2 3 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 613 jul 15, 2010 (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets spt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 614 jul 15, 2010 18.6 timing charts when using the i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer di rection, and then starts serial communication with the slave device. figures 18-27 and 18-28 show timing charts of the data communication. iic shift register 0 (iic0)?s shift operation is synchronized wi th the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 615 jul 15, 2010 figure 18-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 note 2 processing by master device transfer lines processing by slave device iic0 address iic0 data note 1 iic0 ffh note 2 transmit start condition receive notes 1. write data to iic0, not setting wrel0, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iic0 or set wrel0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 616 jul 15, 2010 figure 18-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 ack ack processing by master device transfer lines processing by slave device iic0 data note 1 iic0 ffh note 2 iic0 ffh note 2 iic0 data note 1 transmit receive note 2 note 2 notes 1. write data to iic0, not setting wrel0, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iic0 or set wrel0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 617 jul 15, 2010 figure 18-27. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 ack processing by master device transfer lines processing by slave device iic0 data note 1 iic0 address iic0 ffh note 2 iic0 ffh note 2 stop condition start condition transmit note 2 note 2 (when spie0 = 1) receive (when spie0 = 1) notes 1. write data to iic0, not setting wrel0, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iic0 or set wrel0. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 618 jul 15, 2010 figure 18-28. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d4 d3 d2 d5 d6 d7 ack r processing by master device transfer lines processing by slave device iic0 address iic0 ffh note 1 note 1 iic0 data note 2 transmit transmit receive receive notes 1. to cancel master wait, write ?ffh? to iic0 or set wrel0. 2. write data to iic0, not setting wrel0, in order to cancel a wait state during slave transmission. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 619 jul 15, 2010 figure 18-28. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l l h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 1 89 2345678 9 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 processing by master device transfer lines processing by slave device note 1 note 1 receive transmit iic0 data note 2 iic0 data note 2 iic0 ffh note 1 iic0 ffh note 1 notes 1. to cancel master wait, write ?ffh? to iic0 or set wrel0. 2. write data to iic0, not setting wrel0, in order to cancel a wait state during slave transmission. 78k0/kx2 chapter 18 serial interface iic0 r01uh0008ej0401 rev.4.01 620 jul 15, 2010 figure 18-28. example of slave to master communication (when 8-clock and 9-clock wait is selected for m aster, 9-clock wait is selected for slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 nack processing by master device transfer lines processing by slave device iic0 address iic0 ffh note 1 iic0 ffh note 1 note 1 note 3 notes 1, 3 iic0 data note 2 stop condition start condition (when spie0 = 1) (when spie0 = 1) receive receive transmit notes 1. to cancel wait, write ?ffh? to iic0 or set wrel0. 2. write data to iic0, not setting wrel0, in order to cancel a wait state during slave transmission. 3. if a wait state during slave transmission is canceled by setting wrel0, trc0 will be cleared. 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 621 jul 15, 2010 chapter 19 multiplier/divider 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 multiplier/divider ? products whose flash memory is less than 32 kb: ? products whose flash memory is at least 48 kb: remark : mounted, ? : not mounted caution do not use serial interface iic0 and the mult iplier/divider simultane ously, because various flags corresponding to interrupt re quest sources are shared among serial interface iic0 and the multiplier/divider. 19.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 16 bits = 32 bits, 16-bit remainder (division) 19.2 configuration of multiplier/divider the multiplier/divider incl udes the following hardware. table 19-1. configuration of multiplier/divider item configuration registers remainder data register 0 (sdr0) multiplication/division data r egisters a0 (mda0h, mda0l) multiplication/division dat a registers b0 (mdb0) control register multiplier/divider control register 0 (dmuc0) figure 19-1 shows the block diagram of the multiplier/divider. 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 622 jul 15, 2010 figure 19-1. block diagra m of multiplier/divider internal bus f prs start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h + mdb0l) remainder data register 0 (sdr0 (sdr0h + sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 ( mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll) ) controller dmue mda000 intdmu 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 623 jul 15, 2010 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. this register stor es 0 in the multip lication mode and the remainder of an operation result in the division mode. sdr0 can be read by an 8-bit or 16-bit memory manipulation instruction. reset signal generation clears sdr0 to 0000h. figure 19-2. format of remainder data register 0 (sdr0) address: ff60h, ff61h after reset: 0000h r symbol ff61h (sdr0h) ff60h (sdr0l) sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 during operati on processing (while bit 7 (dmu e) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1). (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a 32-bit register that sets a 16-bit multiplier a in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the oper ation (higher 16 bits: mda0h, lower 16 bits: mda0l). figure 19-3. format of mult iplication/division data regi ster a0 (mda0h, mda0l) address: ff62h, ff63h, ff64h, ff65h after reset: 0000h, 0000h r/w symbol ff65h (mda0hh) ff64h (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff63h (mda0lh) ff62h (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control regist er 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 during operation pr ocessing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1). even in th is case, the operation is executed, but the result is undefined. 3. the value read from mda0 during operation processi ng (while dmue is 1) is not guaranteed. 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 624 jul 15, 2010 the functions of mda0 when an operation is executed are shown in the table below. table 19-2. functions of mda0 during operation execution dmusel0 operation mode setting operation result 0 division mode di vidend division result (quotient) 1 multiplication mode higher 16 bits: 0, lower 16 bits: multiplier a multiplication result (product) remark dmusel0: bit 0 of multiplier/divider control register 0 (dmuc0) the register configuratio n differs between when multiplication is ex ecuted and when division is executed, as follows. ? register configuration during multiplication 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 625 jul 15, 2010 19.3 register controlling multiplier/divider the multiplier/divider is controlled by mult iplier/divider control register 0 (dmuc0). (1) multiplier/divider c ontrol register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. dmuc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears dmuc0 to 00h. figure 19-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff68h after reset: 00h r/w symbol 4 3 2 1 0 6 <7> 5 note when dmue is set to 1, the operat ion is started. dmue is automatically cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during operati on processing (when dmue is 1) , the operation result is not guaranteed. if the operation is completed while the clearing instru ction is being executed, the operation result is gua ranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (while dmue is 1). if it is changed, undefined operation resu lts are stored in multiplicati on/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during operation processing (while dmue is 1), the operation processing is stopped. to execute the operation again, set mu ltiplication/division data register a0 (mda0), multiplication/division data register b0 (mdb0), and multiplier/divider cont rol register 0 (dmuc0), and start the operation (by setting dmue to 1). 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 626 jul 15, 2010 19.4 operations of multiplier/divider 19.4.1 multiplication operation ? initial setting 1. set operation data to multiplication/ division data register a0l (mda0l) and mu ltiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divi der control register 0 (dmuc0) to 1. operation will start. ? during operation 3. the operation will be completed when 16 peripheral hardware clocks (f prs ) have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0h register s during operation, and therefore the read values of these registers are not guaranteed). ? end of operation 4. the operation result data is stor ed in the mda0l and mda0h registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 19.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 19.4.2 division operation . 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 627 jul 15, 2010 figure 19-6. timing chart of multiplication operation (00dah 0093h) f prs mda0 sdr0 mdb0 1 2 345 6 78 9a b cd e f 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006d 0000 00da xxxx 00da xxxx xxxx xxxx 0049 8036 0024 c01b 005b e00d 0077 7006 003b b803 0067 5c01 007d 2e00 003e 9700 001f 4b80 000f a5c0 0007 d2e0 0003 e970 0001 f4b8 0000 fa5c 0000 7d2e 0093 xxxx internal clock dmue dmusel0 counter intdmu 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 628 jul 15, 2010 19.4.2 division operation ? initial setting 1. set operation data to multiplication/ division data register a0 (mda0l and mda0h) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. operation will start. ? during operation 3. the operation will be completed when 32 peripheral hardware clocks (f prs ) have been issued after the start of the operation (intermediate data is stored in the mda0l and md a0h registers and remainder data register 0 (sdr0) during operation, and therefore the read values of these re gisters are not guaranteed). ? end of operation 4. the result data is stored in th e mda0l, mda0h, and sdr0 registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 19.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 19.4.2 division operation . 78k0/kx2 chapter 19 multiplier/divider r01uh0008ej0401 rev.4.01 629 jul 15, 2010 figure 19-7. timing chart of division operation (dcba2586h 0018h) f prs mda0 sdr0 mdb0 12345678 19 1a 1b 1c 1d 1e 1f 20 0 0 0000 0001 0003 0006 000d 0003 0007 000e 0004 000b 0016 0014 0010 0008 0011 000b 0016 b974 4b0c dcba 2586 xxxx xxxx xxxx 72e8 9618 e5d1 2c30 cba2 5860 9744 b0c1 2e89 6182 5d12 c304 ba25 8609 0c12 64d8 1824 c9b0 3049 9361 6093 26c3 c126 4d87 824c 9b0e 0499 361d 0932 6c3a 0018 xxxx internal clock dmue dmusel0 counter intdmu ?0? 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 630 jul 15, 2010 chapter 20 interrupt functions 78k0/ke2 78k0/kb2 78k0/kc2 78k0/kd2 products whose flash memory is less than 32 kb products whose flash memory is at least 48 kb 78k0/kf2 external 6 38/44 pins: 7 ch 48 pins: 8 ch 8 9 9 9 maskable interrupts internal 14 16 16 16 19 20 20.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority s pecification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority in terrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priori ty, are simultaneously generat ed, then they are processed according to the priority of vectored interrupt servicing. for the priority order, see table 20-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instru ction. it is acknowle dged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 20.2 interrupt sources and configuration the interrupt sources consist of maskable interrupts and softw are interrupts. in addition, they also have up to four reset sources (see table 20-1 ). 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 631 jul 15, 2010 table 20-1. interrupt source list (1/2) interrupt source interrupt type internal/ external basic configuration type note 1 default priority note 2 name trigger vector table address k b 2 k c 2 k d 2 k e 2 k f 2 internal (a) 0 intlvi low-voltage detection note 3 0004h 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh external (b) 6 intp5 pin input edge detection 0010h 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad end of a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intwti watch timer reference time interval signal 0028h ? maskable internal (a) 19 inttm51 note 4 match between tm51 and cr51 (when compare register is specified) 002ah notes 1. basic configuration types (a) to (d) correspond to (a) to (d) in figure 20-1 . 2. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 28 indicates the lowest priority. 3. when bit 1 (lvimd) of the low-voltage det ection register (lvim) is cleared to 0. 4. when 8-bit timer/event counter 51 is used in the carrie r generator mode, an interrupt is generated upon the timing when the inttm5h1 signal is generated (see figure 9-13 transfer timing ). 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 632 jul 15, 2010 table 20-1. interrupt source list (2/2) interrupt source interrupt type internal/ external basic configuration type note 1 default priority note 2 name trigger vector table address k b 2 k c 2 k d 2 k e 2 k f 2 external (c) 20 intkr key interrupt detection 002ch ? internal (a) 21 intwt watch timer overflow 002eh ? 22 intp6 0030h ? note 4 external (b) 23 intp7 pin input edge detection 0032h ? ? ? 24 intiic0/ intdmu end of iic0 communication/end of multiply/divide operation 0034h note 5 note 5 note 5 note 5 25 intcsi11 end of csi11 communication 0036h ? ? ? note 6 26 inttm001 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 0038h ? ? ? note 6 27 inttm011 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) 003ah ? ? ? note 6 maskable internal (a) 28 intacsi end of csia0 communication 003ch ? ? ? ? software ? (d) ? brk brk instruction execution 003eh reset reset input poc power-on clear lvi low-voltage detection note 3 reset ? ? ? wdt wdt overflow 0000h notes 1. basic configuration types (a) to (d) correspond to (a) to (d) in figure 20-1 . 2. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 28 indicates the lowest priority. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. 4. 48-pin products only. 5. intiic0: products with the flash memory of 32 kb or less intiic0/intdmu: products with the flash memory of 48 kb or more 6. products with the flash memory of 48 kb or more only. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 633 jul 15, 2010 figure 20-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable interrupt (intpn) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector remark n = 0 to 5: 78k0/kb2, 38-pin and 44-pin products of 78k0/kc2 n = 0 to 6: 78k0/kd2, 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/ke2, 78k0/kf2 if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 634 jul 15, 2010 figure 20-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk krmn ie pr1 isp1 internal bus krn pin input priority controller vector table address generator standby release signal key interrupt detector key return mode register (krm) remark n = 0, 1: 38-pin products of 78k0/kc2 n = 0 to 3: 44-pin and 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/kd2, 78k0/ke2, 78k0/kf2 (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 635 jul 15, 2010 20.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regist er (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 20-2 shows a list of interrupt request flags, interrupt ma sk flags, and priority specification flags corresponding to interrupt request sources. table 20-2. flags corresponding to interrupt request sources (1/2) interrupt request flag interrupt mask flag priority specification flag k b 2 k c 2 k d 2 k e 2 k f 2 interrupt source register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 csiif10 note 1 csimk10 note 2 csipr10 note 3 intst0 stif0 note 1 dualif0 note 1 stmk0 note 2 dualmk0 note 2 stpr0 note 3 dualpr0 note 3 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 notes 1. if either interrupt source intcsi10 or ints t0 is generated, bit 2 of if0h is set (1). 2. bit 2 of mk0h supports both interrupt sources intcsi10 and intst0. 3. bit 2 of pr0h supports both interrupt sources intcsi10 and intst0. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 636 jul 15, 2010 table 20-2. flags corresponding to interrupt request sources (2/2) interrupt request flag interrupt mask flag priority specification flag k b 2 k c 2 k d 2 k e 2 k f 2 interrupt source register register register intad adif if1l admk mk1l adpr pr1l intsr0 srif0 srmk0 srpr0 ? intwti wtiif wtimk wtipr inttm51 note 4 tmif51 tmmk51 tmpr51 ? intkr krif krmk krpr ? intwt wtif wtmk wtpr ? note 1 intp6 pif6 pmk6 ppr6 ? intp7 pif7 pmk7 ppr7 intiic0 note 5 iicif0 note 6 if1h iicmk0 note 7 mk1h iicpr0 note 8 pr1h note 2 note 2 note 2 note 2 intdmu note 5 dmuif note 6 dmumk note 7 dmupr note 8 ? ? ? note 3 intcsi11 csiif11 csimk11 csipr11 ? ? ? note 3 inttm001 tmif001 tmmk001 tmpr001 ? ? ? note 3 inttm011 tmif011 tmmk011 tmpr011 ? ? ? ? intacsi acsiif acsimk acsipr notes 1. 48-pin products only. 2. intiic0: products whose flash memory is less than 32 kb intiic0/intdmu: products whose flash memory is at least 48 kb 3. products whose flash memory is at least 48 kb only. 4. when 8-bit timer/event counter 51 is used in the ca rrier generator mode, an interrupt is generated upon the timing when the inttm5h1 signal is generated (see figure 9-13 transfer timing ). 5. do not use serial interface iic0 and multiplier/divider simultaneously, because the flags corresponding to the interrupt request sources of serial interface iic0 and mult iplier/divider support both of these interrupt request sources. if software which operates serial interface iic0 is developed by cc78k0 which is c compiler, do not select the check box of ?using mu ltiplier/divider? on gui of pm+. 6. if either interrupt source intiic0 or intd mu is generated, bit 0 of if1h is set (1). 7. bit 0 of mk1h supports both interrupt sources intiic0 and intdmu. 8. bit 0 of pr1h supports both interrupt sources intiic0 and intdmu. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 637 jul 15, 2010 (1) interrupt request flag regist ers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspondi ng interrupt request is generated or an instruction is executed. they are cleared to 0 w hen an instruction is executed upon a cknowledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are set by a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. cautions 1. when operating a timer, serial interface, or a/d converter a fter standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 2. when manipulating a flag of the interrupt requ est flag register, use a 1-bit memory manipulation instruction (clr1). when describing in c langua ge, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the compiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becom es the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if 0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exercis ed when using an 8-bit memory manipulation instruction in c language. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 638 jul 15, 2010 figure 20-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (78k0/kb2) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol 7 6 5 4 <3> 2 <1> <0> if1l 0 0 0 0 tmif51 0 srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> if1h 0 0 0 0 0 0 0 iicif0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution be sure to clear bits 2, 4 to 7 of if1l and bits 1 to 7 of if1h to 0. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 639 jul 15, 2010 figure 20-3. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (78k0/kc2) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> if1l 0 pif6 note 1 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> if1h 0 0 0 0 0 0 0 iicif0 dmuif note 2 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. 48-pin products only. 2. products whose flash memory is at least 48 kb only. cautions 1. be sure to clear bits 6 and 7 of if1l to 0 in the 38-pin and 44-pin products. be sure to clear bit 7 of if1l to 0 in the 48-pin products. 2. be sure to clear bits 1 to 7 of if1h to 0. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 640 jul 15, 2010 figure 20-4. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (78k0/kd2) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> if1l 0 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> if1h 0 0 0 0 0 0 0 iicif0 dmuif note xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status note products whose flash memory is at least 48 kb only. caution be sure to clear bit 7 of 1f1l and bits 1 to 7 of if1h to 0. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 641 jul 15, 2010 figure 20-5. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (78k0/ke2) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 4 <3> <2> <1> <0> if1h 0 0 0 0 tmif011 note tmif001 note csiif11 note iicif0 dmuif note xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status note products whose flash memory is at least 48 kb only. caution be sure to clear bits 1 to 7 of if1h to 0 fo r the products whose flash memo ry is less than 32 kb. be sure to clear bits 4 to 7 of if1h to 0 for the products whose flash memory is at least 48 kb. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 642 jul 15, 2010 figure 20-6. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (78k0/kf2) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if1h 0 0 0 acsiif tmif011 tmif001 csiif11 iicif0 dmuif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution be sure to clear bits 5 to 7 of if1h to 0. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 643 jul 15, 2010 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit register s mk0 and mk1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 20-7. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h) (78k0/kb2) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol 7 6 5 4 <3> 2 <1> <0> mk1l 1 1 1 1 tmmk51 1 srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> mk1h 1 1 1 1 1 1 1 iicmk0 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 2, 4 to 7 of mk1l and bits 1 to 7 of mk1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 644 jul 15, 2010 figure 20-8. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h) (78k0/kc2) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> mk1l 1 pmk6 note 1 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> mk1h 1 1 1 1 1 1 1 iicmk0 dmumk note 2 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. 48-pin products only. 2. products whose flash memory is at least 48 kb only. cautions 1. be sure to set bits 6 and 7 of mk1l to 1 in the 38-pin and 44-pin products. be sure to set bit 7 of mk1l to 1 in the 48-pin products. 2. be sure to set bits 1 to 7 of mk1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 645 jul 15, 2010 figure 20-9. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h) (78k0/kd2) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> mk1l 1 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> mk1h 1 1 1 1 1 1 1 iicmk0 dmumk note xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note products whose flash memory is at least 48 kb only. caution be sure to set bit 7 of mk1l and bits 1 to 7 of mk1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 646 jul 15, 2010 figure 20-10. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h) (78k0/ke2) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 4 <3> <2> <1> <0> mk1h 1 1 1 1 tmmk011 note tmmk001 note csimk11 note iicmk0 dmumk note xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note products whose flash memory is at least 48 kb only. caution be sure to set bits 1 to 7 of mk1h to 1 for the products whose fl ash memory is less than 32 kb. be sure to set bits 4 to 7 of mk1h to 1 for th e products whose flash memory is at least 48 kb. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 647 jul 15, 2010 figure 20-11. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h) (78k0/kf2) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk1h 1 1 1 acsimk tmmk011 tmmk001 csimk11 iicmk0 dmumk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 5 to 7 of mk1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 648 jul 15, 2010 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bit me mory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 20-12. format of priority specification flag registers (pr0 l, pr0h, pr1l, pr1h) (78k0/kb2) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol 7 6 5 4 <3> 2 <1> <0> pr1l 1 1 1 1 tmpr51 1 srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> pr1h 1 1 1 1 1 1 1 iicpr0 xxprx priority level selection 0 high priority level 1 low priority level caution be sure to set bits 2, 4 to 7 of pr1l and bits 1 to 7 of pr1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 649 jul 15, 2010 figure 20-13. format of priority specification flag registers (pr0 l, pr0h, pr1l, pr1h) (78k0/kc2) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> pr1l 1 ppr6 note 1 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> pr1h 1 1 1 1 1 1 1 iicpr0 dmupr note 2 xxprx priority level selection 0 high priority level 1 low priority level notes 1. 48-pin products only. 2. products whose flash memory is at least 48 kb only. cautions 1. be sure to set bits 6 and 7 of pr1l to 1 in the 38- pin and 44-pin products. be sure to set bit 7 of pr1l to 1 in the 48-pin products. 2. be sure to set bits 1 to 7 of pr1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 650 jul 15, 2010 figure 20-14. format of priority specification flag registers (pr0 l, pr0h, pr1l, pr1h) (78k0/kd2) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol 7 <6> <5> <4> <3> <2> <1> <0> pr1l 1 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> pr1h 1 1 1 1 1 1 1 iicpr0 dmupr note xxprx priority level selection 0 high priority level 1 low priority level note products whose flash memory is at least 48 kb only. caution be sure to set bit 7 of pr1l and bits 1 to 7 of pr1h to 1. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 651 jul 15, 2010 figure 20-15. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) (78k0/ke2) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 4 <3> <2> <1> <0> pr1h 1 1 1 1 tmpr011 note tmpr001 note csipr11 note iicpr0 dmupr note xxprx priority level selection 0 high priority level 1 low priority level note products whose flash memory is at least 48 kb only. caution be sure to set bits 1 to 7 of pr1h to 1 for the products whose fl ash memory is less than 32 kb. be sure to set bits 4 to 7 of pr1h to 1 for th e products whose flash memory is at least 48 kb. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 652 jul 15, 2010 figure 20-16. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) (78k0/kf2) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr1h 1 1 1 acsipr tmpr011 tmpr001 csipr11 iicpr0 dmupr xxprx priority level selection 0 high priority level 1 low priority level caution be sure to set bits 5 to 7 of pr1h to 1. (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intpn. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. remark n = 0 to 5: 78k0/kb2, 38-pin and 44-pin products of 78k0/kc2 n = 0 to 6: 78k0/kd2, 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/ke2, 78k0/kf2 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 653 jul 15, 2010 figure 20-17. format of external interrupt rising edge enable register (egp) and external interrupt falling e dge enable register (egn) (1/2) (1) 78k0/kb2 address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 (2) 38-pin and 44-pin products of 78k0/kc2 address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 (3) 48-pin products of 78k0/kc2, 78k0/kd2 address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges caution be sure to clear bits 6 and 7 of eg p and egn to 0 in 78k0/kb2, and 38-pin and 44-pin products of 78k0/kc2. be sure to clear bit 7 of egp and egn to 0 in 78k0/kd2, and 48-pin products of 78k0/kc2. remark n = 0 to 5: 78k0/kb2, 38-pin and 44-pin products of 78k0/kc2 n = 0 to 6: 78k0/kd2, 48-pin products of 78k0/kc2 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 654 jul 15, 2010 figure 20-17. format of external interrupt rising edge enable register (egp) and external interrupt falling e dge enable register (egn) (2/2) (4) 78k0/ke2, 78k0/kf2 address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges remark n = 0 to 7: 78k0/ke2, 78k0/kf2 table 20-3 shows the ports corresponding to egpn and egnn. table 20-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7 notes 1. 78k0/kb2, and 38-pin and 44-pin products of 78k0/kc2 2. 78k0/kd2, and 48-pin products of 78k0/kc2 3. 78k0/ke2 and 78k0/kf2 caution select the port mode by clearing egpn and eg nn to 0 because an edge m ay be detected when the external interrupt function is switched to the port function. remark n = 0 to 5: 78k0/kb2, 38-pin and 44-pin products of 78k0/kc2 n = 0 to 6: 78k0/kd2, 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/ke2, 78k0/kf2 note 1 note 2 note 3 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 655 jul 15, 2010 (5) program status word (psw) the program status word is a register used to hold the instruction executio n result and the current status for an interrupt request. the ie flag that sets maskable interru pt enable/disable and the isp flag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out operations using bit m anipulation instructions and dedicated instructions (ei and di). when a vector ed interrupt request is acknowledged, if the brk instructio n is executed, the contents of the psw are automatic ally saved into a stack and the ie flag is re set to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the ackn owledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instru ction. they are restored from the stack with the reti, retb, and pop psw instructions. reset signal generation sets psw to 02h. figure 20-18. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 656 jul 15, 2010 20.4 interrupt servicing operations 20.4.1 maskable interrupt acknowledgment a maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cl eared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). howeve r, a low-priority interrupt r equest is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request unt il vectored interrupt servicing is performed are listed in table 20-4 below. for the interrupt request acknowledgment timing, see figures 20-20 and 20-21 . table 20-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated si multaneously, the request with a higher priority level specified in the priority specification flag is acknowledged fi rst. if two or more interrupts requests have the same priority level, the request with the highest defau lt priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 20-19 shows the interrupt requ est acknowledgment algorithm. if a maskable interrupt request is ackno wledged, the contents are sa ved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corre sponding to the acknowledged interrupt are transferred to the isp flag. the vector table data determined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 657 jul 15, 2010 figure 20-19. interrupt request acknowledgment pr ocessing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority leve l of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing) 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 658 jul 15, 2010 figure 20-20. interrupt request a cknowledgment timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 20-21. interrupt request a cknowledgment timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 20.4.2 software interrupt request acknowledgment a software interrupt acknowledge is acknowledged by br k instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the content s are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 659 jul 15, 2010 20.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the interr upt request acknowledgment ena bled state is selected (ie = 1). when an interrupt request is acknowledged, interrupt requ est acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei inst ruction during interrupt servici ng to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority c ontrol and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an interr upt request with a priority equal to or hi gher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple inte rrupt servicing. if an interrupt with a priority lower than t hat of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrup t servicing. interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. when servicing of the current interrupt ends, t he pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 20-22 shows multiple interrupt servicing examples. table 20-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { u u u { maskable interrupt isp = 1 { u { u { software interrupt { u { u { remarks 1. : multiple interrupt servicing enabled 2. u : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr0l, pr0h, pr1l, and pr1h. pr = 0: higher priority level pr = 1: lower priority level 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 660 jul 15, 2010 figure 20-22. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt requests , intyy and intzz, are acknowl edged, and multiple interrupt servicing takes place. before each interrupt request is ackn owledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt in txx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt se rvicing does not take place. the int yy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 661 jul 15, 2010 figure 20-22. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing do es not take place. the intyy interrupt request is held pending, and is acknowledged following executi on of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled 78k0/kx2 chapter 20 interrupt functions r01uh0008ej0401 rev.4.01 662 jul 15, 2010 20.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending un til the end of executi on of the next instruction. t hese instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers. caution the brk instruction is not one of the above-listed interrupt requ est hold instructions. however, the software interrupt activated by executing the brk instruction causes th e ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. figure 20-23 shows the timing at which interrupt requests are held pending. figure 20-23. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). 78k0/kx2 chapter 21 key interrupt function r01uh0008ej0401 rev.4.01 663 jul 15, 2010 chapter 21 key interrupt function 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 key interrupt ? 38 pins: 2 ch 44/48 pins: 4 ch 8 ch 21.1 functions of key interrupt a key interrupt (intkr) can be generated by setting the ke y return mode register (krm) and inputting a falling edge to the key interrupt input pins (krn). table 21-1. assignment of k ey interrupt detection pins flag description krmn controls krn signal in 1-bit units. remark n = 0, 1: 38-pin products of 78k0/kc2 n = 0 to 3: 44-pin and 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/kd2, 78k0/ke2, 78k0/kf2 78k0/kx2 chapter 21 key interrupt function r01uh0008ej0401 rev.4.01 664 jul 15, 2010 21.2 configuration of key interrupt the key interrupt includes the following hardware. table 21-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 21-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 remark kr0, kr1, krm0, krm1: 38-pin products of 78k0/kc2 kr0 to kr3, krm0 to krm3: 44-pin and 48-pin products of 78k0/kc2 kr0 to kr7, krm0 to krm7: 78k0/kd2, 78k0/ke2, 78k0/kf2 78k0/kx2 chapter 21 key interrupt function r01uh0008ej0401 rev.4.01 665 jul 15, 2010 21.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krmn bit using the krn signal. krm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears krm to 00h. figure 21-2. format of key return mode register (krm) (1) 38-pin products of 78k0/kc2 0 krm 0 0 0 0 0 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 (2) 44-pin and 48-pin products of 78k0/kc2 0 krm 0 0 0 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 (3) 78k0/kd2, 78k0/ke2, 78k0/kf2 krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krmn bits used is set to 1, set bit n (pu7n) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the interr upt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. 4. for the 38-pin products of 78k0 /kc2, be sure to set bits 2 to 7 of krm to ?0?. for the 44-pin and 48-pin products of 78k0/kc2, be sure to set bits 4 to 7 of krm to ?0?. remark n = 0, 1: 38-pin products of 78k0/kc2 n = 0 to 3: 44-pin and 48-pin products of 78k0/kc2 n = 0 to 7: 78k0/kd2, 78k0/ke2, 78k0/kf2 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 666 jul 15, 2010 chapter 22 standby function 22.1 standby function and configuration 22.1.1 standby function the standby function is mounted onto all 78k0/kx2 microcontroller products. the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. in the ha lt mode, the cpu operation cl ock is stopped. if the high- speed system clock oscillator, internal high-speed oscillat or, internal low-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clo ck continues. in this mode, the operating current is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. note the 78k0/kb2 is not provided wit h a subsystem clock oscillator. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole s ystem, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure the o scillation stabilization time after the stop mode is released when the x1 clock is selected, select t he halt mode if it is necessary to star t processing immediately upon interrupt request generation. in either of these two modes, all the co ntents of registers, flags and data memo ry just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operat ing on the main system clock. the subsystem clock oscillation cannot be stopped. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. 2. when shifting to the stop mode, be sure to stop the peripheral hard ware operation operating with main system clock before executing stop instruction. 3. the following sequence is recommended for ope rating current reductio n of the a/d converter when the standby function is u sed: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d c onversion operation, and then execute the stop instruction. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 667 jul 15, 2010 22.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 6 clock generator . (1) oscillation stabilization time c ounter status register (ostc) this is the register that indi cates the count status of the x1 clock oscill ation stabilization time counter. when x1 clock oscillation starts with the internal high -speed oscillatio n clock or subsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 668 jul 15, 2010 figure 22-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the oper ation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confi rm with ostc that the desired oscillation stabilization time has elapsed after the stop m ode is released. the oscillati on stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 669 jul 15, 2010 figure 22-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 204.8 s 102.4 s 0 1 0 2 13 /f x 819.2 s 409.6 s 0 1 1 2 14 /f x 1.64 ms 819.2 s 1 0 0 2 15 /f x 3.27 ms 1.64 ms 1 0 1 2 16 /f x 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 cl ock is used as the cpu cl ock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency 22.2 standby function operation 22.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. ha lt mode can be set regardless of whether the cpu clock before the setting was the high-speed system clock, inte rnal high-speed oscillation clock, or subsystem clock note . the operating statuses in t he halt mode are shown below. note the 78k0/kb2 is not provi ded with a subsystem clock. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 670 jul 15, 2010 table 22-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh operation continues (cannot be stopped) status before halt mode was set is retained f x status before halt mode was set is retained operation continues (cannot be stopped) status before halt mode was set is retained main system clock f exclk operates or stops by external cl ock input operation continues (cannot be stopped) f xt status before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before halt mode was set is retained cpu flash memory operation stopped ram port (latch) status before halt mode was set is retained 00 16-bit timer/event counter 01 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output buzzer output a/d converter uart0 uart6 csi10 csi11 csia0 serial interface iic0 multiplier/divider power-on-clear function low-voltage detection function external interrupt operable remarks 1. f rh : internal high-speed oscillation clock, f x : x1 clock f exclk : external main system clock, f xt : xt1 clock f exclks : external subsystem clock, f rl : internal low-speed oscillation clock 2. the functions mounted de pend on the product. see 1.7 block diagram and 1.8 outline of functions . 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 671 jul 15, 2010 table 22-1. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) when cpu is operating on external subsystem clock (f exclks ) system clock clock supply to the cpu is stopped f rh f x status before halt mode was set is retained main system clock f exclk operates or stops by external clock input f xt operation continues (cannot be stopped) stat us before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input operation continues (cannot be stopped) f rl status before halt mode was set is retained cpu flash memory operation stopped ram port (latch) status before halt mode was set is retained 00 note 16-bit timer/event counter 01 note 50 note 8-bit timer/event counter 51 note h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable buzzer output a/d converter operable. however, operation dis abled when peripheral hardware clock (f prs ) is stopped. uart0 uart6 csi10 note csi11 note csia0 note serial interface iic0 note multiplier/divider power-on-clear function low-voltage detection function external interrupt operable note when the cpu is operating on the subsystem clock and the internal high-speed oscillation clock and high-speed system clock have been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. remarks 1. f rh : internal high-speed oscillation clock, f x : x1 clock f exclk : external main system clock, f xt : xt1 clock f exclks : external subsystem clock, f rl : internal low-speed oscillation clock 2. the functions mounted de pend on the product. see 1.7 block diagram and 1.8 outline of functions . 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 672 jul 15, 2010 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the ha lt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 22-3. halt mode release by interrupt request generation halt instruction wait note 1 normal operation halt mode normal operation oscillation high-speed system clock, internal high-speed oscillation clock, or subsystem clock note 2 status of cpu standby release signal interrupt request notes 1. the wait time is as follows: ? when vectored interrupt servicing is carried out: 11 or 12 clocks ? when vectored interrupt servicing is not carried out: 4 or 5 clocks 2. the 78k0/kb2 is not provi ded with a subsystem clock. remark the broken lines indicate the case when the interr upt request which has released the standby mode is acknowledged. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 673 jul 15, 2010 (b) release by reset signal generation when the reset signal is generated, halt mode is rele ased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 22-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (11 to 45 s) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization (86 to 361 s) reset processing (11 to 45 s) (3) when subsystem clock is used as cpu clock note 1 halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (11 to 45 s) oscillation stabilization time (measure by the user) note 2 notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. oscillation stabilization time is not requir ed when using the external subsystem clock (f exclks ) as the subsystem clock. remark f x : x1 clock oscillation frequency 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 674 jul 15, 2010 table 22-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset ? ? reset processing : don?t care 22.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standb y mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus , the stop mode is reset to the halt mode immediately after execution of the stop instructi on and the system returns to th e operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 675 jul 15, 2010 table 22-3. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh f x stopped main system clock f exclk input invalid f xt status before stop mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before stop mode was set is retained cpu flash memory operation stopped ram port (latch) status before stop mode was set is retained 00 note 1 16-bit timer/event counter 01 note 1 operation stopped 50 note 1 operable only when ti50 is se lected as the count clock 8-bit timer/event counter 51 note 1 operable only when ti51 is se lected as the count clock h0 operable only when tm50 output is selected as the count clock during 8- bit timer/event counter 50 operation 8-bit timer h1 operable only when f rl , f rl /2 7 , f rl /2 9 is selected as the count clock watch timer operable only when subsystem clock is selected as the count clock watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable only w hen subsystem clock is selected as the count clock buzzer output a/d converter operation stopped uart0 uart6 operable only when tm50 output is selected as the serial clock during 8-bi t timer/event counter 50 operation csi10 note 1 csi11 note 1 operable only when external clock is selected as the serial clock csia0 note 1 operation stopped serial interface iic0 note 1 operable only when the external clock from exscl0/p62 pin is selected as the serial clock note 2 multiplier/divider operation stopped power-on-clear function low-voltage detection function external interrupt operable notes 1. do not start operation of these functions on the external clock input from peripheral hardware pins in the stop mode. 2. the operation of 78k0/kb2 produc ts is stopped (the external clock from the exscl0/p62 pin cannot be selected, because the exscl0/p62 pin is not mounted.). remarks 1. f rh : internal high-speed oscillation clock, f x : x1 clock f exclk : external main system clock, f xt : xt1 clock f exclks : external subsystem clock, f rl : internal low-speed oscillation clock 2. the functions mounted de pend on the product. see 1.7 block diagram and 1.8 outline of functions . 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 676 jul 15, 2010 cautions 1. to use the peripheral hard ware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops osc illating in the stop mode after th e stop mode is released, restart the peripheral hardware. 2. even if ?internal low-speed oscillator can be stopped by software? is sel ected by the option byte, the internal low-speed oscillation cl ock continues in the stop mode in the status before the stop mode is set. to stop the internal low-speed osc illator?s oscillation in the stop mode, stop it by software and then execute the stop instruction. 3. to shorten oscillation stabilization time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation), switch the cpu clock to the inte rnal high-speed oscillation clock before the execution of the stop instruction using the following procedure. <1> set rstop to 0 (starting oscillation of the internal high-speed oscillator) <2> set mcm0 to 0 (switching the cpu from x1 oscillation to internal high-speed oscillation) <3> check that mcs is 0 (checking the cpu clock) <4> check that rsts is 1 (checki ng internal high-speed oscillation operation) <5> execute the stop instruction before changing the cpu clock from the internal high-speed o scillation clock to the high-speed system clock (x1 oscillation) after the stop mode is released, check the o scillation stabilization time with the oscillation stabilization ti me counter status register (ostc). 4. if the stop instruction is executed when amph = 1, supply of th e cpu clock is stopped for 4.06 to 16.12 s after the stop mode is released when the internal high-speed oscillation clock is selected as the cpu clock, or for the dur ation of 160 external clocks when the high-speed system clock (external clock input) is sel ected as the cpu clock. 5. execute the stop instruction after having conf irmed that the internal high-speed oscillator is operating stably (rsts = 1). 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 677 jul 15, 2010 (2) stop mode release figure 22-5. operation timing when stop mode is released (when unmasked interrupt request is generated) stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization (86 to 361 s) halt status (oscillation stabilization time set by osts) clock switched by software clock switched by software high-speed system clock high-speed system clock wait note2 wait note2 supply of the cpu clock is stopped (4.06 to 16.12 s) note1 high-speed system clock supply of the cpu clock is stopped (160 external clocks) note1 internal high-speed oscillation clock notes 1. when amph = 1 2. the wait time is as follows: ? when vectored interrupt servicing is carried out: 17 or 18 clocks ? when vectored interrupt servicing is not carried out: 11 or 12 clocks the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is ge nerated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 678 jul 15, 2010 figure 22-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock in put) is used as cpu clock ? when amph = 1 interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) oscillates normal operation (high-speed system clock) stop mode oscillation stopped oscillates normal operation (high-speed system clock) wait note supply of the cpu clock is stopped (160 external clocks) ? when amph = 0 interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) normal operation (high-speed system clock) oscillates stop mode oscillation stopped wait note normal operation (high-speed system clock) oscillates note the wait time is as follows: ? when vectored interrupt servicing is carried out: 17 or 18 clocks ? when vectored interrupt servicing is not carried out: 11 or 12 clocks remark the broken lines indicate the case when the inte rrupt request that has released the standby mode is acknowledged. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 679 jul 15, 2010 figure 22-6. stop mode release by interrupt request generation (2/2) (3) when internal high-speed osc illation clock is used as cpu clock ? when amph = 1 (4.06 to 16.12 s) standby release signal status of cpu internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) oscillates stop mode oscillation stopped wait for oscillation accuracy stabilization (86 to 361 s) interrupt request stop instruction wait note normal operation (internal high-speed oscillation clock) supply of the cpu clock is stopped oscillates ? when amph = 0 wait note wait for oscillation accuracy stabilization (86 to 361 s) oscillates normal operation (internal high-speed oscillation clock) stop mode oscillation stopped oscillates normal operation (internal high-speed oscillation clock) internal high-speed oscillation clock status of cpu standby release signal stop instruction interrupt request note the wait time is as follows: ? when vectored interrupt servicing is carried out: 17 or 18 clocks ? when vectored interrupt servicing is not carried out: 11 or 12 clocks remark the broken lines indicate the case when the inte rrupt request that has released the standby mode is acknowledged. 78k0/kx2 chapter 22 standby function r01uh0008ej0401 rev.4.01 680 jul 15, 2010 (b) release by reset signal generation when the reset signal is generated, stop mode is rel eased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 22-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 11 /f x to 2 16 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (11 to 45 s) note note oscillation stabilization time is not requir ed when using the external main system clock (f exclk ) as the high- speed system clock. (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization (86 to 361 s) reset processing (11 to 45 s) remark f x : x1 clock oscillation frequency table 22-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset ? ? reset processing : don?t care 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 681 jul 15, 2010 chapter 23 reset function the reset function is mounted onto all 78k0/kx2 microcontroller products. the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences. in both cases, program execut ion starts at the address at 0000h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in tables 23-1 and 23-2. each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a reset release, except for p130, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released fr om the reset status when a high level is input to the reset pin and program ex ecution is started with the internal high-speed oscillation clock after reset processing. a reset by the watchdog timer is automatically released, and program execution starts using the internal high- speed oscillation clock (see figures 23-2 to 23-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 24 power-on-clear circuit and chapter 25 low- voltage detector ) after reset processing. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset signal generati on, the x1 clock, xt1 clock note 1 , internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating. extern al main system clock input and external subsystem clock note 1 input become invalid. 3. when the stop mode is released by a rese t, the stop mode contents are held during reset input. however, the port pins beco me high-impedance, except for p130 note 2 , which is set to low- level output. notes 1. the 78k0/kb2 is not prov ided with xt1 clock and external subsystem clock. 2. p130 pin is not mounted onto 38-pin and 44- pin products of the 78k0/kc2 and 78k0/kb2. 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 682 jul 15, 2010 figure 23-1. block di agram of reset function lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set resf register read signal caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 683 jul 15, 2010 figure 23-2. timing of reset by reset input delay delay (5 s (typ.)) hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p130) port pin (p130 note 1 ) note 2 high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (11 to 45 s) wait for oscillation accuracy stabilization (86 to 361 s) notes 1. p130 pin is not mounted onto 78k0/kb2, and 38-pin and 44-pin products of the 78k0/kc2. 2. set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be dummy -output as the cpu reset signal. 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 684 jul 15, 2010 figure 23-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin (except p130) port pin (p130 note 1 ) note 2 high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (11 to 45 s) wait for oscillation accuracy stabilization (86 to 361 s) notes 1. p130 pin is not mounted onto 78k0/kb2, and 38-pin and 44-pin products of the 78k0/kc2. 2. set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 685 jul 15, 2010 figure 23-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin (except p130) port pin (p130 note 1 ) note 2 starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (11 to 45 s) delay (5 s (typ.)) wait for oscillation accuracy stabilization (86 to 361 s) notes 1. p130 pin is not mounted onto 78k0/kb2, and 38-pin and 44-pin products of the 78k0/kc2. 2. set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 2. for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 24 power- on-clear circuit and chapter 25 low-voltage detector . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 686 jul 15, 2010 table 23-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f rh operation stopped f x operation stopped (pin is i/o port mode) main system clock f exclk clock input invalid (pin is i/o port mode) f xt operation stopped (pin is i/o port mode) subsystem clock f exclks clock input invalid (pin is i/o port mode) f rl cpu flash memory ram port (latch) 00 16-bit timer/event counter 01 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer watchdog timer clock output buzzer output a/d converter uart0 uart6 csi10 csi11 csia0 serial interface iic0 multiplier/divider operation stopped power-on-clear f unction operable low-voltage detection function external interrupt operation stopped remarks 1. f rh : internal high-speed oscillation clock, f x : x1 clock f exclk : external main system clock, f xt : xt1 clock f exclks : external subsystem clock, f rl : internal low-speed oscillation clock 2. the functions mounted de pend on the product. see 1.7 block diagram and 1.8 outline of functions . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 687 jul 15, 2010 table 23-2. hardware statuses after reset acknowledgment (1/4) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p7, p12 to p14) (output latches) 00h port mode registers (pm0 to pm7, pm12, pm14) ffh pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu14) 00h internal expansion ram size switching register (ixs) 0ch notes 3, 4 internal memory size switching register (ims) cfh notes 3, 4 notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. the initial values of the internal memory size s witching register (ims) and internal expansion ram size switching register (ixs) after a reset release are consta nt (ims = cfh, ixs = 0ch) in all products of the 78k0/kx2 microcontrollers, regardle ss of the internal memory capacit y. therefore, set the value corresponding to each product as indicated in tables 3-1 and 3-2. 4. the rom and ram capacities of t he products with the on-chip debug function can be debugged by setting ims and ixs, according to the debug target products . set ims and ixs according to the debug target products. remark the special function register (sfr ) mounted depend on the product. see 3.2.3 special function registers (sfrs) . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 688 jul 15, 2010 table 23-2. hardware statuses after reset acknowledgment (2/4) hardware status after reset acknowledgment note 1 memory bank select register (bank) 00h clock operation mode select register (oscctl) 00h processor clock control register (pcc) 01h internal oscillation mode register (rcm) 80h main osc control register (moc) 80h main clock mode register (mcm) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 05h timer counters 00, 01 (tm00, tm01) 0000h capture/compare registers 000, 010, 001, 011 (cr000, cr010, cr001, cr011) 0000h mode control registers 00, 01 (tmc00, tmc01) 00h prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h 16-bit timer/event counters 00, 01 timer output control registers 00, 01 (toc00, toc01) 00h timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection regist ers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 2 00h watch timer operation m ode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h watchdog timer enable register (wdte) 1ah/9ah note 3 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h mode register (adm) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h asynchronous serial interface reception error status register 0 (asis0) 00h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. 8-bit timer h1 only. 3. the reset value of wdte is dete rmined by the option byte setting. remark the special function register (sfr ) mounted depend on the product. see 3.2.3 special function registers (sfrs) . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 689 jul 15, 2010 table 23-2. hardware statuses after reset acknowledgment (3/4) hardware status after reset acknowledgment note receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmis sion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface control register 6 (asicl6) 16h serial interface uart6 input switch control register (isc) 00h transmit buffer registers 10, 11 (sotb10, sotb11) 00h serial i/o shift registers 10, 11 (sio10, sio11) 00h serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi11 serial clock selection register s 10, 11 (csic10, csic11) 00h serial operation mode specification register 0 (csima0) 00h serial status register 0 (csis0) 00h serial trigger register 0 (csit0) 00h divisor value selection r egister 0 (brgca0) 03h automatic data transfer address point specification register 0 (adtp0) 00h automatic data transfer interval specification register 0 (adti0) 00h serial i/o shift register 0 (sioa0) 00h serial interface csia0 automatic data transfer address count register 0 (adtc0) 00h shift register 0 (iic0) 00h control register 0 (iicc0) 00h slave address register 0 (sva0) 00h clock selection register 0 (iiccl0) 00h function expansion register 0 (iicx0) 00h status register 0 (iics0) 00h serial interface iic0 flag register 0 (iicf0) 00h remainder data register 0 (sdr0) 0000h multiplication/division data regi ster a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider multiplier/divider control register 0 (dmuc0) 00h key interrupt key return mode register (krm) 00h note during reset signal generation or oscillation stabiliz ation time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. remark the special function register (sfr ) mounted depend on the product. see 3.2.3 special function registers (sfrs) . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 690 jul 15, 2010 table 23-2. hardware statuses after reset acknowledgment (4/4) hardware status after reset acknowledgment note 1 reset function reset control flag register (resf) 00h note 2 low-voltage detection register (lvim) 00h note 2 low-voltage detector low-voltage detection level selection register (lvis) 00h note 2 request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l, 1h (mk0l, mk0h, mk1l, mk1h) ffh priority specification fl ag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf flag set (1) held resf lvirf flag cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held remark the special function register (sfr ) mounted depend on the product. see 3.2.3 special function registers (sfrs) . 78k0/kx2 chapter 23 reset function r01uh0008ej0401 rev.4.01 691 jul 15, 2010 23.1 register for confirming reset source many internal reset generation sources exist in the 78k0/kx2 mi crocontrollers. the reset cont rol flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circuit, and reading resf set resf to 00h. figure 23-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 23-3. table 23-3. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 692 jul 15, 2010 chapter 24 power-on-clear circuit 24.1 functions of power-on-clear circuit the power-on-clear circuit (poc) is mounted onto all 78k0/kx2 microcontroller products. the power-on-clear circuit has the following functions. ? generates internal reset signal at power on. in the 1.59 v poc mode (option byte: pocmode = 0), the reset signal is released when the supply voltage (v dd ) exceeds 1.59 v 0.15 v. in the 2.7 v/1.59 v poc mode (option byte: pocmode = 1), the reset signal is released when the supply voltage (v dd ) exceeds 2.7 v 0.2 v. ? compares supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v), generates internal reset signal when v dd < v poc . caution if an internal reset signal is generated in the poc circuit, the r eset control flag register (resf) is cleared to 00h. remark 78k0/kx2 microcontrollers incorporate multiple hardware functions that generate an internal reset signal. a flag that indicates the reset source is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog time r (wdt) or low-voltage-detector (lvi). resf is not cleared to 00h and the flag is set to 1 when an in ternal reset signal is generated by wdt or lvi. for details of resf, see chapter 23 reset function . 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 693 jul 15, 2010 24.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 24-1. figure 24-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 24.3 operation of power-on-clear circuit (1) in 1.59 v poc mode (option byte: pocmode = 0) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.59 v 0.15 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v ddpoc = 2.7 v 0.2 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v ddpoc . the timing of generation of the internal reset signal by th e power-on-clear circuit and low-voltage detector is shown below. 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 694 jul 15, 2010 figure 24-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) note 4 note 4 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. operation stops wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock) note 5 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization (86 to 361 s) normal operation (internal high-speed oscillation clock) note 5 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v notes 1, 2, 3 wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock ) note 5 0.5 v/ms (min.) note 2, 3 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt internal reset signal reset processing (11 to 45 s) reset processing (11 to 45 s) reset processing (11 to 45 s) v poc = 1.59 v (typ.) v lvi notes 1. the guaranteed operation range for the standard and (a) grade products is 1.8 v v dd 5.5 v, and 2.7 v v dd 5.5 v for the (a2) grade products. to set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls, use t he reset function of the low-voltage detector, or input a low level to the reset pin. 2. with the standard and (a) grade products, if the voltage rises to 1.8 v at a rate slower than 0.5 v/ms (min.) on power application, input a low level to the reset pin after power application and before the voltage reaches 1.8 v, or set the 2. 7 v/1.59 v poc mode by using an option byte (pocmode = 1). 3. with the (a2) grade products, if the voltage rises to 2.7 v at a rate slower t han 0.75 v/ms (min.) on power application, input a low level to the reset pin after power application and before the voltage reaches 2.7 v. 4. the oscillation accuracy stabilization time of the in ternal high-speed oscillation clock is included in the internal voltage stabilization time. 5. the cpu clock can be switched from the internal hi gh-speed oscillation clock to the high-speed system clock or to the subsystem clock note 6 . to use the x1 clock, use the ostc register to confirm the lapse of the oscillation stabilization time . to use the xt1 clock note 6 , use the timer function for confirmation of the lapse of the stabilization time. 6. the 78k0/kb2 is not provided wit h subsystem clock and xt1 clock. caution set the low-voltage detector by software after the reset stat us is released (see chapter 25 low- voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 695 jul 15, 2010 figure 24-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. internal reset signal v ddpoc = 2.7 v (typ.) v poc = 1.59 v (typ.) v lvi operation stops normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 reset processing (11 to 45 s) reset processing (11 to 45 s) reset processing (11 to 45 s) set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) notes 1. the guaranteed operation range for the standard and (a) grade products is 1.8 v v dd 5.5 v, and 2.7 v v dd 5.5 v for the (a2) grade products. to set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls, use t he reset function of the low-voltage detector, or input a low level to the reset pin. 2. the cpu clock can be switched from the internal hi gh-speed oscillation clock to the high-speed system clock or subsystem clock note 3 . to use the x1 clock, use the ostc register to confirm the lapse of the oscillation stabilization time . to use the xt1 clock note 3 , use the timer function for confirmation of the lapse of the stabilization time. 3. the 78k0/kb2 is not provided wit h subsystem clock and xt1 clock. cautions 1. set the low-voltage det ector by software after the reset status is released (see chapter 25 low-voltage detector). 2. a voltage oscillation stabilization time of 1. 93 to 5.39 ms is required after the supply voltage reaches 1.59 v (typ.). if the supply voltage ri ses from 1.59 v (typ.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automati cally generated before reset processing. remark v lvi : lvi detection voltage v poc : poc detection voltage 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 696 jul 15, 2010 24.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. 78k0/kx2 chapter 24 power-on-clear circuit r01uh0008ej0401 rev.4.01 697 jul 15, 2010 figure 24-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 698 jul 15, 2010 chapter 25 low-voltage detector 25.1 functions of low-voltage detector the low-voltage detector (lvi) is mounted onto all 78k0/kx2 microcontroller products. the low-voltage detector has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v (typ.): fixed), and generates an internal reset or internal interrupt signal. ? the supply voltage (v dd ) or input voltage from an external input pin (exlvi) can be selected by software. ? reset or interrupt function can be selected by software. ? detection levels (16 levels note ) of supply voltage can be changed by software. ? operable in stop mode. note standard products and (a) grade products: 16 levels (a2) grade products: 10 levels the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by readi ng the low-voltage detection fl ag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, see chapter 23 reset function . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 699 jul 15, 2010 25.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 25-1. figure 25-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 25.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears th is register to 00h. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 700 jul 15, 2010 figure 25-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 3 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. this bit is cleared to 00h upon a reset other than an lvi reset. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 4. when lvion is set to 1, operation of the comparator in the lvi circ uit is started. use software to wait for an operation stabilization time (10 s (min.)) from when lvion is set to 1 until operation is stabilized. after operation has st abilized, the external input of 200 s (min.) (minimum pulse width: 200 s (min.)) is required from when a state below lvi detection voltage has been entered, until lvif is set (1). cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 701 jul 15, 2010 cautions 3. when using lvi as an interrupt, if lvion is cleared (0) in a stat e below the lvi detection voltage, an intlvi signal is ge nerated and lviif becomes 1. 4. with the conventiona l-specification products ( pd78f05xx and 78f05xxd), after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears th is register to 00h. figure 25-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h note 1 r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.24 v 0.1 v) 0 0 0 1 v lvi1 (4.09 v 0.1 v) 0 0 1 0 v lvi2 (3.93 v 0.1 v) 0 0 1 1 v lvi3 (3.78 v 0.1 v) 0 1 0 0 v lvi4 (3.62 v 0.1 v) 0 1 0 1 v lvi5 (3.47 v 0.1 v) 0 1 1 0 v lvi6 (3.32 v 0.1 v) 0 1 1 1 v lvi7 (3.16 v 0.1 v) 1 0 0 0 v lvi8 (3.01 v 0.1 v) 1 0 0 1 v lvi9 (2.85 v 0.1 v) 1 0 1 0 v lvi10 (2.70 v 0.1 v) note 2 1 0 1 1 v lvi11 (2.55 v 0.1 v) note 2 1 1 0 0 v lvi12 (2.39 v 0.1 v) note 2 1 1 0 1 v lvi13 (2.24 v 0.1 v) note 2 1 1 1 0 v lvi14 (2.08 v 0.1 v) note 2 1 1 1 1 v lvi15 (1.93 v 0.1 v) note 2 notes 1. the value of lvis is not reset but retained as is, upon a reset by lvi. it is cleared to 00h upon other resets. 2. do not set v lvi10 to v lvi15 for (a2) grade products. cautions 1. be sure to cl ear bits 4 to 7 to ?0?. 2. do not change the value of lvis during lvi operation. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefor e, setting of lvis is not necessary. 4. with the conventiona l-specification products ( pd78f05xx and 78f05xxd), after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 702 jul 15, 2010 (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for ex ternal low-voltage detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm12 to ffh. figure 25-4. format of port mode register 12 (pm12) 0 pm120 1 pm121 2 pm122 3 pm123 4 pm124 5 1 6 1 7 1 symbol pm12 address: ff2ch after reset: ffh r/w pm12n p12n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) remark the format of port mode register 12 of 78k0/ kb2 products is different from the above format. see 5.3 registers controlling port func tion (1) port mode registers (pmxx) . 25.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the i nput voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the i nput voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). while the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by readi ng the low-voltage detection fl ag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 703 jul 15, 2010 25.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (min.)). <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 25-5 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvim k = 0, an interrupt may oc cur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 704 jul 15, 2010 figure 25-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> v lvi v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 23 reset function . remark <1> to <7> in figure 25-5 above correspond to <1> to <7> in the description of ?when starting operation? in 25.4.1 (1) when detecting level of supply voltage (v dd ) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 705 jul 15, 2010 figure 25-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) v lvi <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> 2.7 v (typ.) v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 23 reset function . remark <1> to <7> in figure 25-5 above correspond to <1> to <7> in the description of ?when starting operation? in 25.4.1 (1) when detecting level of supply voltage (v dd ) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 706 jul 15, 2010 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects le vel of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (min.)). <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 25-6 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvim k = 0, an interrupt may oc cur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 707 jul 15, 2010 figure 25-6. timing of low-voltage dete ctor internal reset signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) lvi detection voltage (v exlvi ) <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <3> <6> lvion flag (set by software) lvimd flag (set by software) h note 1 lvisel flag (set by software) <5> <2> not cleared not cleared <4> wait time not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 23 reset function . remark <1> to <6> in figure 25-6 above correspond to <1> to <6> in the description of ? when starting operation? in 25.4.1 (2) when detecting level of inpu t voltage from external input pin (exlvi) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 708 jul 15, 2010 25.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to wait for an operation stabilization time (10 s (min.)). <7> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <8> clear the interrupt request flag of lvi (lviif) to 0. <9> release the interrupt mask flag of lvi (lvimk). <10> execute the ei instruction (w hen vector interrupts are used). figure 25-7 shows the timing of the interrupt signal gener ated by the low-voltage detec tor. the numbers in this timing chart correspond to <1> to <9> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 709 jul 15, 2010 figure 25-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) time <1> note 1 <9> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <5> <7> <8> cleared by software <6> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <4> note 2 note 3 note 3 v lvi v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detec tion voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <9> in figure 25-7 above correspond to <1> to <9> in the description of ?when starting operation? in 25.4.2 (1) when detecting level of supply voltage (v dd ) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 710 jul 15, 2010 figure 25-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) time <1> note 1 <9> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <5> <7> <8> cleared by software <6> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <4> 2.7 v(typ.) note 2 note 3 note 3 v lvi v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detec tion voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <9> in figure 25-7 above correspond to <1> to <9> in the description of ?when starting operation? in 25.4.2 (1) when detecting level of supply voltage (v dd ) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 711 jul 15, 2010 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects le vel of input voltage from external input pin (exlvi)). <3> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (min.)). <6> confirm that ?input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)? when detecting the falling edge of exlvi, or ?input voltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.)? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> execute the ei instruction (w hen vector interrupts are used). figure 25-8 shows the timing of the interrupt signal gener ated by the low-voltage detec tor. the numbers in this timing chart correspond to <1> to <8> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 712 jul 15, 2010 figure 25-8. timing of low-voltage detector interrupt signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 lvisel flag (set by software) <2> lvimd flag (set by software) l <3> note 2 note 3 note 3 v exlvi notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detec tion voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <8> in figure 25-8 above correspond to <1> to <8> in the description of ?when starting operation? in 25.4.2 (2) when detecting level of inpu t voltage from external input pin (exlvi) . 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 713 jul 15, 2010 25.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of t he microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take (b) of action (2) below. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 714 jul 15, 2010 figure 25-9. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source note initialize the port. reset initialization processing <1> 50 ms has passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer or a/d converter yes no clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer h1 (tmhe1 = 0 tmhe1 = 1) no ; the timer counter is cleared and the timer is started. lvi reset ;f prs = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f prs (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (tmhe1 = 1). note a flowchart is shown on the next page. 78k0/kx2 chapter 25 low-voltage detector r01uh0008ej0401 rev.4.01 715 jul 15, 2010 figure 25-9. example of software processing after reset release (2/2) ? checking reset source yes: reset generation by lvi no: reset generation other than by lvi set lvi (set lvim and lvis registers) check reset source lvion of lvim register = 1? 78k0/kx2 chapter 26 option byte r01uh0008ej0401 rev.4.01 716 jul 15, 2010 chapter 26 option byte 26.1 functions of option bytes the flash memory at 0080h to 0084h of the 78k0/kx2 microc ontrollers is an option byte area. when power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. when using the product, be sure to set the following functions by using the option bytes. when the boot swap operation is used dur ing self-programming, 0080h to 0084h are switched to 1080h to 1084h. therefore, set values that are the same as thos e of 0080h to 0084h to 1080h to 1084h in advance. caution be sure to set 00h to 0082h and 0083h (0082h/1082h and 0083h/1083h when the boot swap function is used). (1) 0080h/1080h { internal low-speed oscillator operation ? can be stopped by software ? cannot be stopped { watchdog timer overflow time setting { watchdog timer counter operation ? enabled counter operation ? disabled counter operation { watchdog timer window open period setting caution set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. (2) 0081h/1081h { selecting poc mode ? during 2.7 v/1.59 v poc mode operation (pocmode = 1) the device is in the reset state upon power application and until the supply vo ltage reaches 2.7 v (typ.). it is released from the reset state when t he voltage exceeds 2.7 v (typ.). afte r that, poc is not detected at 2.7 v but is detected at 1.59 v (typ.). with standard and (a) grade products, if the supply voltage ri ses to 1.8 v after power application at a rate slower than 0.5 v/ms (min.), us e of the 2.7 v/1.59 v poc mode is recommended. ? during 1.59 v poc mode operation (pocmode = 0) the device is in the reset state upon power application an d until the supply voltage reaches 1.59 v (typ.). it is released from the reset state when the voltage exceeds 1. 59 v (typ.). after that, poc is detected at 1.59 v (typ.), in the same manner as on power application. caution pocmode can only be writte n by using a dedicated flash memory programmer. it cannot be set during self-programming or boot swap operati on during self-programmi ng. however, because the value of 1081h is copied to 0081h during the b oot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. 78k0/kx2 chapter 26 option byte r01uh0008ej0401 rev.4.01 717 jul 15, 2010 (3) 0084h/1084h { on-chip debug operation control ? disabling on-chip debug operation ? enabling on-chip debug operation and erasing data of the flash memory in case authentication of the on-chip debug security id fails ? enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security id fails cautions 1. be sure to set 00h (disabling on-chip debug operation) to 0084h for products not equipped with the on-chip debug function ( pd78f05xx and 78f05xxa). also set 00h to 1084h because 0084h and 1084h are switch ed during the boot operation. 2. to use the on-chip debug function with a product equipped with the on- chip debug function ( pd78f05xxd and 78f05xxda), set 02h or 03h to 008 4h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h are switched during the boot operation. 26.2 format of option byte the format of the option byte is shown below. 78k0/kx2 chapter 26 option byte r01uh0008ej0401 rev.4.01 718 jul 15, 2010 figure 26-1. format of option byte (1/2) address: 0080h/1080h note 7 6 5 4 3 2 1 0 0 window1 window0 wdton wdcs2 wdcs1 wdcs0 lsrosc window1 window0 watchdog timer window open period 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped afte r reset), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) lsrosc internal low-speed oscillator operation 0 can be stopped by software (stopped when 1 is written to bit 1 (lsrstop) of rcm register) 1 cannot be stopped (not stopped even if 1 is written to lsrstop bit) note set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. setting window1 = window0 = 0 is prohi bited when using the watchdog timer at 1.8 v v dd < 2.7 v. 3. the watchdog timer continues its operati on during self-programming a nd eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledg e time is delayed. set the overflow time and window size taki ng this delay into consideration. 4. if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, regardless of the setting of bit 0 (lsrstop) of the internal oscillation mode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clo ck, the count clock is supplied to 8-bit timer h1 even in the halt/stop mode. 5. be sure to clear bit 7 to 0. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) 78k0/kx2 chapter 26 option byte r01uh0008ej0401 rev.4.01 719 jul 15, 2010 figure 26-1. format of option byte (2/2) address: 0081h/1081h notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 pocmode pocmode poc mode selection 0 1.59 v poc mode (default) 1 2.7 v/1.59 v poc mode notes 1. pocmode can only be written by using a dedicated fl ash memory programmer. it cannot be set during self-programming or boot swap operation during self-p rogramming. however, because the value of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. 2. to change the setting for the poc mode, set the value to 0081h again after batch erasure (chip erasure) of the flash memory. the setting cannot be changed afte r the memory of the specified block is erased. caution be sure to clea r bits 7 to 1 to ?0?. address: 0082h/1082h, 0083h/1083h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 note be sure to set 00h to 0082h and 0083h, as these addresses are reserved areas. also set 00h to 1082h and 1083h because 0082h and 0083h are switched with 1082h and 1083h when the boot swap operation is used. address: 0084h/1084h notes1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ocden1 ocden0 ocden1 ocden0 on-chip debug operation control 0 0 operation disabled 0 1 setting prohibited 1 0 operation enabled. does not erase data of the flash memory in case authentication of the on-chip debug security id fails. 1 1 operation enabled. erases data of the flash memory in case authentication of the on-chip debug security id fails. notes 1. be sure to set 00h (on-chip debug operation disabled) to 0084h for products not equipped with the on-chip debug function ( pd78f05xx and 78f05xxa). also set 00h to 1084h because 0084h and 1084h are switched during the boot swap operation. 2. to use the on-chip debug function with a pr oduct equipped with the on-chip debug function ( pd78f05xxd and 78f05xxda), set 02h or 03h to 0084h. set a valu e that is the same as that of 0084h to 1084h because 0084h and 1084h are switched during the boot swap operation. remark for the on-chip debug security id, see chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only) . 78k0/kx2 chapter 26 option byte r01uh0008ej0401 rev.4.01 720 jul 15, 2010 here is an example of description of t he software for setting the option bytes. opt cseg at 0080h option: db 30h ; enables watchdog timer operation (illegal access detection operation), ; window open period of watchdog timer: 50%, ; overflow time of watchdog timer: 2 10 /f rl , ; internal low-speed oscillator can be stopped by software. db 00h ; 1.59 v poc mode db 00h ; reserved area db 00h ; reserved area db 00h ; on-chip debug operation disabled remark referencing of the option byte is performed during re set processing. for the reset processing timing, see chapter 23 reset function . 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 721 jul 15, 2010 chapter 27 flash memory the 78k0/kx2 microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 27.1 internal memory size switching register select the internal memory capacity using the inte rnal memory size switching register (ims). ims is set by an 8-bit memory manipulation instruction. reset signal generation sets ims to cfh. caution be sure to set each produc t to the values shown in table 27-1 after a reset release. figure 27-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal hi gh-speed ram capacity selection 0 0 0 768 bytes 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 0 0 1 0 8 kb 0 1 0 0 16 kb 0 1 1 0 24 kb 1 0 0 0 32 kb 1 1 0 0 48 kb 1 1 1 1 60 kb other than above setting prohibited caution to set the memory size, set im s and then ixs. set th e memory size so that the internal rom and internal expansion ram areas do not overlap. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 722 jul 15, 2010 table 27-1. internal memory si ze switching register settings 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 ims setting pd78f0500, 78f0500a ? ? ? ? 42h pd78f0501, 78f0501a pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? 04h pd78f0502, 78f0502a pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? c6h pd78f0503, 78f0503a, 78f0503d note 1 , 78f0503da note 1 pd78f0513, 78f0513a, 78f0513d note 1 , 78f0513da note 1 pd78f0523, 78f0523a pd78f0533, 78f0533a ? c8h ? pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a cch ? pd78f0515, 78f0515a, 78f0515d note 1 , 78f0515da note 1 pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a cfh ? ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a cch note 2 ? ? pd78f0527, 78f0527a, 78f0527d note 1 , 78f0527da note 1 pd78f0537, 78f0537a, 78f0537d note 1 , 78f0537da note 1 pd78f0547, 78f0547a, 78f0547d note 1 , 78f0547da note 1 cch note 2 notes 1. the internal rom capacity and internal high-speed ram capacity of the products with the on-chip debug function can be debugged according to the debug target products. set ims according to the debug target products. 2. the pd78f05x6 and 78f05x6a (x = 2 to 4) have internal roms of 96 kb, and the pd78f05x7, 78f05x7a, 78f05x7d, and 78f05x7da (x = 2 to 4) have those of 128 kb. however, the set value of ims of these devices is the same as those of the 48 kb product because memory banks are used. for how to set the memory banks, see 4.3 memory bank select register (bank) . 27.2 internal expansion ram size switching register select the internal expansion ram capacity using the in ternal expansion ram size switching register (ixs). ixs is set by an 8-bit memory manipulation instruction. reset signal generation sets ixs to 0ch. caution be sure to set each produc t to the values shown in table 27-2 after a reset release. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 723 jul 15, 2010 figure 27-2. format of internal expans ion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 7 6 5 4 3 2 1 0 ixs 0 0 0 0 ixram3 ixram2 ixram1 ixram0 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 1 1 0 0 0 bytes 1 0 1 0 1024 bytes 1 0 0 0 2048 bytes 0 1 0 0 4096 bytes 0 0 0 0 6144 bytes other than above setting prohibited caution to set memory size, set ims and then ixs. se t memory size so that th e internal rom area and internal expansion ram area do not overlap. table 27-2. internal expansion ram size switching register settings 48-pin products of 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 ixs setting pd78f0511, 78f0511a pd78f0521, 78f0521a pd78f0531, 78f0531a ? 0ch pd78f0512, 78f0512a pd78f0522, 78f0522a pd78f0532, 78f0532a ? 0ch pd78f0513, 78f0513a pd78f0523, 78f0523a pd78f0533, 78f0533a ? 0ch pd78f0514, 78f0514a pd78f0524, 78f0524a pd78f0534, 78f0534a pd78f0544, 78f0544a 0ah pd78f0515, 78f0515a, 78f0515d note , 78f0515da note pd78f0525, 78f0525a pd78f0535, 78f0535a pd78f0545, 78f0545a 08h ? pd78f0526, 78f0526a pd78f0536, 78f0536a pd78f0546, 78f0546a 04h ? pd78f0527, 78f0527a, 78f0527d note , 78f0527da note pd78f0537, 78f0537a, 78f0537d note , 78f0537da note pd78f0547, 78f0547a, 78f0547d note , 78f0547da note 00h note the internal expansion ram capacity of the products with the on-chip debug function can be debugged according to the debug target products. set ixs according to the debug target products. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 724 jul 15, 2010 27.3 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory c an be rewritten after the 78k0/kx2 mi crocontrollers have been mounted on the target system. the connectors that connect the dedicated flash memory progr ammer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedi cated program adapter (fa series) before the 78k0/kx2 microcontrollers are mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. 27.4 programming environment the environment required for writing a program to the flash memory of the 78k0/kx2 microcontrollers are illustrated below. figure 27-3. environment for wr iting program to flash memory rs-232c usb 78k0/kx2 microcontrollers flmd0 v dd v ss reset csi10/uart6 host machine dedicated flash memory programmer pg-fp5 start power pass busy ng a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory programmer and the 78k0/kx2 microcontrollers, csi10 or uart6 is used for manipulation such as writing and erasing. to writ e the flash memory off-board, a dedicated program adapter (fa series) is necessary. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 725 jul 15, 2010 27.5 communication mode communication between the dedicated flash memory progra mmer and the 78k0/kx2 microcontrollers is established by serial communication via csi10 or ua rt6 of the 78k0/kx2 microcontrollers. (1) csi10 transfer rate: 2.4 khz to 2.5 mhz figure 27-4. communication with dedica ted flash memory programmer (csi10) v dd /ev dd /av ref v ss /ev ss /av ss reset so10 si10 sck10 flmd0 flmd0 v dd gnd /reset si/rxd so/txd sck dedicated flash memory programmer 78k0/kx2 microcontrollers pg-fp5 start power pass busy ng (2) uart6 transfer rate: 115200 bps figure 27-5. communication with dedica ted flash memory programmer (uart6) v dd /ev dd /av ref v ss /ev ss /av ss reset txd6 rxd6 v dd gnd /reset si/rxd so/txd exclk clk dedicated flash memory programmer flmd0 flmd0 78k0/kx2 microcontrollers pg-fp5 start power pass busy ng 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 726 jul 15, 2010 the dedicated flash memory programmer generates the follo wing signals for the 78k0/kx2 microcontrollers. for details, refer to the user?s manual for the pg-fp5, fl-pr5, pg-fp4, or fl-pr4. table 27-3. pin connection dedicated flash memory programmer 78k0/kx2 microcontrollers connection signal name i/o pin function pin name csi10 uart6 flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output to 78k0/kx2 microcontrollers exclk/x2/p122 note 1 { note 2 /reset output reset signal reset si/rxd input receive signal so10/txd6 so/txd output transmit signal si10/rxd6 sck output transfer clock sck10 notes 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 727 jul 15, 2010 for the pins not to be used when the ded icated program adapter (fa series) is used, perform the processing described under the recommended connection of unused pins shown in table 2-3 pin i/o circuit types , or those described in table 27-4 processing of unused pi ns when the flash memory write adapter is connected (required) . table 27-4. processing of unused pi ns when the flash memory write adapter is connected (required) pin name pin processing p00, p01 independently connect to ev ss via a resistor. notes 1, 5 p03 to p06 independently connect to ev ss via a resistor. notes 2, 5 p10, p11 independently connect to ev ss via a resistor. notes 3, 5 p14 independently connect to ev ss via a resistor. notes 4, 5 p16, p17 p30 to p33 independently connect to ev ss via a resistor. notes 1, 5 p60 to p63 independently connect to ev ss via a resistor, or connect directly to ev ss . note 5 p70 to p77 p120 p140 to p143 independently connect to ev ss via a resistor. notes 1, 5 notes 1. these pins may be directly connected to ev ss , without using a resistor, when design is performed so that operation is not swit ched to the normal operation mode on the flash memory write adapter board during flash memory programming. 2. these pins may be left open with the pd78f053n and 78f053na (n = 1 to 3) of the 78k0/ke2 as well as the 78k0/kd2. 3. connect these pins with the program mer when communicating with the dedicated flash memory programmer via serial communication by csi10. 4. connect this pin with the programmer when communicating with the dedicated flash memory programmer via serial communication by uart6. 5. with products without an ev ss pin, connect them to v ss . with products without an ev dd pin, connect them to v dd . 27.6 connection of pins on board to write the flash memory on-board, connectors that connect the dedicate d flash memory programmer must be provided on the target system. first provide a function that selects the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pi ns not used for programming t he flash memory are in the same status as immediately after reset. therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 728 jul 15, 2010 27.6.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an flmd0 pin connection example is shown below. figure 27-6. flmd0 pin connection example 78k0/kx2 microcontrollers flmd0 10 k (recommended) dedicated flash memory programmer connection pin 27.6.2 serial interface pins the pins used by each serial interface are listed below. table 27-5. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 uart6 txd6, rxd6 to connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 729 jul 15, 2010 (1) signal collision if the dedicated flash memory programmer (output) is connect ed to a pin (input) of a serial interface connected to another device (output), signal collision ta kes place. to avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. figure 27-7. signal collision (i nput pin of serial interface) input pin signal collision dedicated flash memory programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. therefore, isolate the signal of the other device. 78k0/kx2 microcontrollers (2) malfunction of other device if the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input ), a signal may be output to the other device , causing the device to malfunction. to avoid this malfunction, isolate t he connection with the other device. figure 27-8. malfunction of other device pin dedicated flash memory programmer connection pin other device input pin if the signal output by the 78k0/kx2 microcontrollers in the flash memory programming mode affects the other device, isolate the signal of the other device. pin dedicated flash memory programmer connection pin other device input pin if the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 78k0/kx2 microcontrollers 78k0/kx2 microcontrollers 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 730 jul 15, 2010 27.6.3 reset pin if the reset signal of the dedicated flash memory programmer is connected to the reset pin that is connected to the reset signal generator on the board, signal collision takes place. to prevent this collision, isolate the connection with the reset signal generator. if the reset signal is input from the us er system while the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash memory programmer. figure 27-9. signal collision (reset pin) 27.6.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. if external devi ces connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to ev dd note or ev ss note via a resistor. note with products without an ev ss pin, connect them to v ss . with products without an ev dd pin, connect them to v dd . 27.6.5 regc pin connect the regc pin to v ss via a capacitor (0.47 to 1 f) in the same manner as during normal operation. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 731 jul 15, 2010 27.6.6 other signal pins connect x1 and x2 in the same status as in t he normal operation mode when using the on-board clock. to input the operating clock from the dedicated flash me mory programmer, however, connect clk of the programmer to exclk/x2/p122. cautions 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. 3. for the product with an on-chip debug function ( pd78f05xxd and 78f 05xxda), connect p31/intp2/ocd1a and p121/x1/ocd0a as follows wh en writing the flash memory with a flash memory programmer. ? p31/intp2/ocd1a: connect to ev ss note via a resistor. ? p121/x1/ocd0a: connect to v ss note via a resistor. note with products without an ev ss pin, connect them to v ss . 27.6.7 power supply to use the supply voltage output of t he flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power monitor function with the flash memory programme r, even when using the on-board supply voltage. supply the same other power supplies (ev dd , ev ss , av ref , and av ss ) as those in the normal operation mode. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 732 jul 15, 2010 27.7 programming method 27.7.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 27-10. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes flmd0 pulse supply no end flash memory programming mode is set 27.7.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78k0/kx2 microcontrollers in the flash memory programming mo de. to set the mode, set the flmd0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 27-11. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flash memory programming mode flmd0 flmd0 pulse v dd 0 v table 27-6. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 733 jul 15, 2010 27.7.3 selecting communication mode in the 78k0/kx2 microcontrollers, a communication mode is selected by inputting pulses to the flmd0 pin after the dedicated flash memory programming mode is entered. these flmd0 pulses are generated by the flash memory programmer. the following table shows the relationship between the number of pulses and communication modes. table 27-7. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used peripheral clock number of flmd0 pulses uart-ext-osc f x 0 uart (uart6) uart-ext-fp5ck 115,200 bps note 3 2 to 20 mhz note 2 txd6, rxd6 f exclk 3 3-wire serial i/o (csi10) csi-internal-osc 2.4 khz to 2.5 mhz ? 1.0 so10, si10, sck10 f rh 8 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. the possible setting range differs depending on the voltage. for details, refer to the chapter of electrical specifications. 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. caution when uart6 is select ed, the receive clock is calculated b ased on the reset command sent from the dedicated flash memory programmer afte r the flmd0 pulse h as been received. remark f x : x1 clock f exclk : external main system clock f rh : internal high-speed oscillation clock 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 734 jul 15, 2010 27.7.4 communication commands the 78k0/kx2 microcontrollers communica te with the dedicated flash memory programmer by using commands. the signals sent from the flash memory programmer to the 78k 0/kx2 microcontrollers are ca lled commands, and the signals sent from the 78k0/kx2 microcontro llers to the dedicated flash memory programmer are called response. figure 27-12. communication commands command response 78k0/kx2 microcontrollers dedicated flash memory programmer pg-fp5 start power pass busy ng the flash memory control commands of the 78k0/kx2 microcontrollers are lis ted in the table below. all these commands are issued from the programmer and the 78k0/kx2 mi crocontrollers perform processing corresponding to the respective commands. table 27-8. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. status gets the current operating status (status data). silicon signature gets 78k0/kx2 information (such as the part number and flash memory configuration). version get gets the 78k0/kx2 version and firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others oscillating frequency set specifies an oscillation frequency. the 78k0/kx2 microcontrollers return a response for the co mmand issued by the dedicated flash memory programmer. the response names sent from the 78k0/ kx2 microcontrollers are listed below. table 27-9. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 735 jul 15, 2010 27.8 security settings the 78k0/kx2 microcontrollers support a security function t hat prohibits rewriting the us er program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be performed using the securi ty set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board programming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for th e batch erase is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be writ ten, because the erase command is disabled. ? disabling block erase execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the block eras e command and write command on boot cluster 0 (0000h to 0fffh) in the flash memory is prohibited by this setting. execution of the batch eras e (chip erase) command is also prohibited by this setting. caution if a security setting that rewrites boot cluster 0 has been applied, the rewr iting of boot cluster 0 and the batch erase (chip erase) will not be executed for the device. the batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. prohibition of erasing blocks and wr iting is cleared by ex ecuting the batch erase (chip erase) command. table 27-10 shows the relationship between the eras e and write commands when the 78k0/kx2 microcontroller security function is enabled. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 736 jul 15, 2010 table 27-10. relationship between enabling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because dat a cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. table 27-11 shows how to perform security settings in each programming mode. table 27-11. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) prohibition of rewriting boot cluster 0 set by using information library. cannot be disabled after set. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 737 jul 15, 2010 27.9 processing time for each command when pg-fp4 or pg-fp5 is used (reference) the following table shows the processing time for each comm and (reference) when the pg-fp4 or pg-fp5 is used as a dedicated flash memory programmer. table 27-12. processing time for each command when pg-fp4 or pg-fp5 is used (reference) (1/2) (1) products with internal roms of the 32 kb port: uart-ext-fp4ck (external main system clock (f exclk )), speed: 115,200 bps command of pg-fp4 port: csi-internal-osc (internal high-speed oscillation clock (f rh )), speed: 2.5 mhz frequency: 2.0 mhz frequency: 20 mhz signature 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) blankcheck 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) erase 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) program 2.5 s (typ.) 5 s (typ.) 5 s (typ.) verify 1.5 s (typ.) 4 s (typ.) 3.5 s (typ.) e.p.v 3.5 s (typ.) 6 s (typ.) 6 s (typ.) checksum 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) security 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) (2) products with internal roms of the 60 kb port: uart-ext-fp4ck (external main system clock (f exclk )), speed: 115,200 bps command of pg-fp4 port: csi-internal-osc (internal high-speed oscillation clock (f rh )), speed: 2.5 mhz frequency: 2.0 mhz frequency: 20 mhz signature 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) blankcheck 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1 s (typ.) 1 s (typ.) 1 s (typ.) program 5 s (typ.) 9 s (typ.) 9 s (typ.) verify 2 s (typ.) 6.5 s (typ.) 6.5 s (typ.) e.p.v 6 s (typ.) 10.5 s (typ.) 10.5 s (typ.) checksum 0.5 s (typ.) 1 s (typ.) 1 s (typ.) security 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) caution when executing boot swapping, do not use th e e.p.v. command with the dedicated flash memory programmer. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 738 jul 15, 2010 table 27-12. processing time for each command when pg-fp4 or pg-fp5 is used (reference) (2/2) (3) products with internal roms of the 128 kb port: uart-ext-fp4ck (external main system clock (f exclk )), speed: 115,200 bps command of pg-fp4 port: csi-internal-osc (internal high-speed oscillation clock (f rh )), speed: 2.5 mhz frequency: 2.0 mhz frequency: 20 mhz signature 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) blankcheck 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) program 9.5 s (typ.) 18 s (typ.) 18 s (typ.) verify 4.5 s (typ.) 13.5 s (typ.) 13.5 s (typ.) e.p.v 11 s (typ.) 19.5 s (typ.) 19.5 s (typ.) checksum 1 s (typ.) 1 s (typ.) 1 s (typ.) security 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) caution when executing boot swapping, do not use th e e.p.v. command with the dedicated flash memory programmer. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 739 jul 15, 2010 27.10 flash memory programming by self-programming the 78k0/kx2 microcontrollers support a se lf-programming function that can be used to rewrite the flash memory via a user program. because this function allows a user applicat ion to rewrite the flash memory by using a self-programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self-progr amming can be temporarily stopped and interrupt servicing can be executed. to execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute the ei inst ruction. after the self-programming mode is later restored, self-programming can be resumed. remark for details of the self-programming function and the self-programming library, refer to 78k0 microcontrollers self programming li brary type01 user?s manual (u18274e) . cautions 1. the self-programming f unction cannot be used when the cp u operates with the subsystem clock. 2. oscillation of the internal high-speed oscillato r is started during self pr ogramming, regardless of the setting of the rstop flag (bit 0 of the internal oscillation mode register (rcm)). oscillation of the internal high-speed oscillator cannot be stoppe d even if the stop inst ruction is executed. 3. input a high level to the fl md0 pin during self-programming. 4. be sure to execute the di instru ction before starting self-programming. the self-programming function checks the interrupt re quest flags (if0l, if0h, if1l, and if1h). if an interrupt request is genera ted, self-programming is stopped. 5. self-programming is also stopped by an interrupt request that is not masked even in the di status. to prevent this, mask the interrupt by using the interrupt mask flag registers (mk0l, mk0h, mk1l, and mk1h). 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 740 jul 15, 2010 caution 6. allocate the entry program for self-programming in th e common area of 0000h to 7fffh. figure 27-13. operation mode and memory map for se lf-programming ( pd78f0547 and 78f0547a) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 normal mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh c000h bfffh f800h f7ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved reserved flash memory control firmware rom disable accessing flash memory (memory bank 0) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 self-programming mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh fa20h fa1fh fa20h fa1fh c000h bfffh f800h f7ffh fa00h f9ffh fa00h f9ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved reserved buffer ram buffer ram reserved reserved flash memory control firmware rom disable accessing enable accessing instructions can be fetched from common area and selected memory bank. instructions can be fetched from common area and firmware rom. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 741 jul 15, 2010 the following figure illustrates a flow of rewriting t he flash memory by using a self-programming library. figure 27-14. flow of self programming (rewriting flash memory) start of self programming flashstart normal completion? no setting operating environment flashenv checkflmd flashblockblankcheck yes flashblockerase flashwordwrite flashblockverify flashend end of self programming normal completion? no yes normal completion? normal completion error no yes flashblockerase flashwordwrite flashblockverify remark for details of the self-programming library, refer to 78k0 microcontrollers self programming library type01 user?s manual (u18274e) . 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 742 jul 15, 2010 the following table shows the processing time and interrupt response time for the self-programming library. table 27-13. processing time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (1/4) (1) when internal high-speed oscillation clock is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.25 initialize library 977.75 mode check library 753.875 753.125 block blank check library 12770.875 12765.875 block erase library 36909.5 356318 36904.5 356296.25 word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375) block verify library 25618.875 25613.875 self programming end library 4.25 option value: 03h 871.25 (871.375) 866 (866.125) option value: 04h 863.375 (863.5) 858.125 (858.25) get information library option value: 05h 1024.75 (1043.625) 1037.5 (1038.375) set information library 105524.75 790809.375 105523.75 790808.375 eeprom write library 1496.5 (1496.875) 2691.5 (2691.875) 1489.5 (1489.875) 2684.5 (2684.875) remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 743 jul 15, 2010 table 27-13. processing time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (2/4) (2) when internal high-speed oscillati on clock is used and entry ram is locat ed in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.25 initialize library 443.5 mode check library 219.625 218.875 block blank check library 12236.625 12231.625 block erase library 36363.25 355771.75 36358.25 355750 word write library 679.75 (680.125) 1874.75 (1875.125) 672.75 (673.125) 1867.75 (1868.125) block verify library 25072.625 25067.625 self programming end library 4.25 option value: 03h 337 (337.125) 331.75 (331.875) option value: 04h 329.125 (239.25) 323.875 (324) get information library option value: 05h 502.25 (503.125) 497 (497.875) set information library 104978.5 541143.125 104977.5 541142.125 eeprom write library 962.25 (962.625) 2157.25 (2157.625) 955.25 (955.625) 2150.25 (2150.625) remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 744 jul 15, 2010 table 27-13. processing time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (3/4) (3) when high-speed system clock (x1 oscillation or external clock input) is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 49/f cpu + 485.8125 mode check library 35/f cpu + 374.75 29/f cpu + 374.75 block blank check library 174/f cpu + 6382.0625 134/f cpu + 6382.0625 block erase library 174/f cpu + 31093.875 174/f cpu + 298948.125 134/f cpu + 31093.875 134/f cpu + 298948.125 word write library 318 (321)/f cpu + 644.125 318 (321)/f cpu + 1491.625 262 (265)/f cpu + 644.125 262 (265)/f cpu + 1491.625 block verify library 174/f cpu + 13448.5625 134/f cpu + 13448.5625 self programming end library 34/f cpu option value: 03h 171 (172 )/f cpu + 432.4375 129 (130)/f cpu + 432.4375 option value: 04h 181 (182)/f cpu + 427.875 139 (140)/f cpu + 427.875 get information library option value: 05h 404 (411)/f cpu + 496.125 362 (369)/f cpu + 496.125 set information library 75/f cpu + 79157.6875 75/f cpu + 652400 67f cpu + 79157.6875 67f cpu + 652400 eeprom write library 318 (321)/f cpu + 799.875 318 (321)/f cpu + 1647.375 262 (265)/f cpu + 799.875 262 (265)/f cpu + 1647.375 remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. f cpu : cpu operation clock frequency 4. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 745 jul 15, 2010 table 27-13. processing time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (4/4) (4) when high-speed system clock (x1 oscillation or externa l clock input) is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 49/f cpu + 224.6875 mode check library 35/f cpu + 113.625 29/f cpu + 113.625 block blank check library 174/f cpu + 6120.9375 134/f cpu + 6120.9375 block erase library 174/f cpu + 30820.75 174/f cpu + 298675 134/f cpu + 30820.75 134/f cpu + 298675 word write library 318 (321)/f cpu + 383 318 (321)/f cpu + 1230.5 262 (265)/f cpu + 383 262 (265)/f cpu + 1230.5 block verify library 174/f cpu + 13175.4375 134/f cpu + 13175.4375 self programming end library 34/f cpu option value: 03h 171 (172)/f cpu + 171.3125 129 (130)/f cpu + 171.3125 option value: 04h 181 (182)/f cpu + 166.75 139 (140)/f cpu + 166.75 get information library option value: 05h 404 (411)/f cpu + 231.875 362 (369)/f cpu + 231.875 set information library 75/f cpu + 78884.5625 75/f cpu + 527566.875 67f cpu + 78884.5625 67f cpu + 527566.875 eeprom write library 318 (321)/f cpu + 538.75 318 (321)/f cpu + 1386.25 262 (265)/f cpu + 538.75 262 (265)/f cpu + 1386.25 remarks 1. values in parentheses indicate values when a write start address structure is located other than in the internal high-speed ram. 2. the above processing times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 3. f cpu : cpu operation clock frequency 4. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 746 jul 15, 2010 table 27-14. processing time for self programming library (expanded-specification products ( pd78f05xxa and 78f05xxda)) (1/3) (1) when internal high-speed oscillation clock is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.0 4.5 4.0 4.5 initialize library 1105.9 1106.6 1105.9 1106.6 mode check library 905.7 906.1 904.9 905.3 block blank check library 12776.1 12778.3 12770.9 12772.6 block erase library 26050.4 349971.3 26045.3 349965.6 word write library 1180.1 + 203 w 1184.3 + 2241 w 1172.9 + 203 w 1176.3 + 2241 w block verify library 25337.9 25340.2 25332.8 25334.5 self programming end library 4.0 4.5 4.0 4.5 option value: 03h 1072.9 1075.2 1067.5 1069.1 option value: 04h 1060.2 1062.6 1054.8 1056.6 get information library option value: 05h 1023.8 1028.2 1018.3 1022.1 set information library 70265.9 759995.0 70264.9 759994.0 eeprom write library 1316.8 + 347 w 1320.9 + 2385 w 1309.0 + 347 w 1312.4 + 2385 w (2) when internal high-speed oscillati on clock is used and entry ram is locat ed in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 4.0 4.5 4.0 4.5 initialize library 449.5 450.2 449.5 450.2 mode check library 249.3 249.7 248.6 248.9 block blank check library 12119.7 12121.9 12114.6 12116.3 block erase library 25344.7 349266.4 25339.6 349260.8 word write library 445.8 + 203 w 449.9 + 2241 w 438.5 + 203 w 441.9 + 2241 w block verify library 24682.7 24684.9 24677.6 24679.3 self programming end library 4.0 4.5 4.0 4.5 option value: 03h 417.6 419.8 412.1 413.8 option value: 04h 405.0 407.4 399.5 401.3 get information library option value: 05h 367.4 371.8 361.9 365.8 set information library 69569.3 759297.3 69568.3 759296.2 eeprom write library 795.1 + 347 w 799.3 + 2385 w 787.4 + 347 w 790.8 + 2385 w remarks 1. the above processing times are those when a write st art address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 747 jul 15, 2010 table 27-14. processing time for self programming library (expanded-specification products ( pd78f05xxa and 78f05xxda)) (2/3) (3) when high-speed system clock (x1 oscillation or external clock input) is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 55/f cpu + 594 mode check library 36/f cpu + 495 30/f cpu + 495 block blank check library 179/f cpu + 6429 136/f cpu + 6429 block erase library 179/f cpu + 19713 179/f cpu + 268079 136/f cpu + 19713 136/f cpu + 268079 word write library 333/f cpu + 647 + 136 w 333/f cpu + 647 + 1647 w 272/f cpu + 647 + 136 w 272/f cpu + 647 + 1647 w block verify library 179/f cpu + 13284 136/f cpu + 13284 self programming end library 34/f cpu option value: 03h 180/f cpu + 581 134/f cpu + 581 option value: 04h 190/f cpu + 574 144/f cpu + 574 get information library option value: 05h 350/f cpu + 535 304/f cpu + 535 set information library 80/f cpu + 43181 80/f cpu + 572934 72/f cpu + 43181 72/f cpu + 572934 eeprom write library 333/f cpu + 729 + 209 w 333/f cpu + 729 + 1722 w 268/f cpu + 729 + 209 w 268/f cpu + 729 + 1722 w remarks 1. the above processing times are those wh en a write start address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. f cpu : cpu operation clock frequency 4. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 748 jul 15, 2010 table 27-14. processing time for self programming library (expanded-specification products ( pd78f05xxa and 78f05xxda)) (3/3) (4) when high-speed system clock (x1 oscillation or externa l clock input) is used and entry ram is located in short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler library name min. max. min. max. self programming start library 34/f cpu initialize library 55/f cpu + 272 mode check library 36/f cpu + 173 30/f cpu + 173 block blank check library 179/f cpu + 6108 136/f cpu + 6108 block erase library 179/f cpu + 19371 179/f cpu + 267738 136/f cpu + 19371 136/f cpu + 267738 word write library 333/f cpu + 247 + 136 w 333/f cpu + 247 + 1647 w 272/f cpu + 247 + 136 w 272/f cpu + 247 + 1647 w block verify library 179/f cpu +12964 136/f cpu +12964 self programming end library 34/f cpu option value: 03h 180/f cpu + 261 134/f cpu + 261 option value: 04h 190/f cpu + 254 144/f cpu + 254 get information library option value: 05h 350/f cpu + 213 304/f cpu + 213 set information library 80/f cpu + 42839 80/f cpu + 572592 72/f cpu + 42839 72/f cpu + 572592 eeprom write library 333/f cpu + 516 + 209 w 333/f cpu + 516 + 1722 w 268/f cpu + 516 + 209 w 268/f cpu + 516 + 1722 w remarks 1. the above processing times are those wh en a write start address structure is located in the internal high- speed ram and during stabilized operation of t he internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) 3. f cpu : cpu operation clock frequency 4. w: number of words in write data (1 word = 4 bytes) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 749 jul 15, 2010 table 27-15. interrupt response time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (1/2) (1) when internal high-speed oscillation clock is used interrupt response time ( s (max.)) normal model of c compiler static model of c compiler/assembler library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 933.6 668.6 927.9 662.9 block erase library 1026.6 763.6 1020.9 757.9 word write library 2505.8 1942.8 2497.8 1934.8 block verify library 958.6 693.6 952.9 687.9 set information library 476.5 211.5 475.5 210.5 eeprom write library 2760.8 2168.8 2759.5 2167.5 remarks 1. the above interrupt response times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) (2) when high-speed system clock is used (normal model of c compiler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 179/f cpu + 507 179/f cpu + 407 179/f cpu + 1650 179/f cpu + 714 block erase library 179/f cpu + 559 179/f cpu + 460 179/f cpu + 1702 179/f cpu + 767 word write library 333/f cpu + 1589 333/f cpu + 1298 333/f cpu + 2732 333/f cpu + 1605 block verify library 179/f cpu + 518 179/f cpu + 418 179/f cpu + 1661 179/f cpu + 725 set information library 80/f cpu + 370 80/f cpu + 165 80/f cpu + 1513 80/f cpu + 472 29/f cpu + 1759 29/f cpu + 1468 29/f cpu + 1759 29/f cpu + 1468 eeprom write library note 333/f cpu + 834 333/f cpu + 512 333/f cpu + 2061 333/f cpu + 873 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 750 jul 15, 2010 table 27-15. interrupt response time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) (2/2) (3) when high-speed system clock is used (static model of c compiler/assembler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 136/f cpu + 507 136/f cpu + 407 136/f cpu + 1650 136/f cpu + 714 block erase library 136/f cpu + 559 136/f cpu + 460 136/f cpu + 1702 136/f cpu + 767 word write library 272/f cpu + 1589 272/f cpu + 1298 272/f cpu + 2732 272/f cpu + 1605 block verify library 136/f cpu + 518 136/f cpu + 418 136/f cpu + 1661 136/f cpu + 725 set information library 72/f cpu + 370 72/f cpu + 165 72/f cpu + 1513 72/f cpu + 472 19/f cpu + 1759 19/f cpu + 1468 19/f cpu + 1759 19/f cpu + 1468 eeprom write library note 268/f cpu + 834 268/f cpu + 512 268/f cpu + 2061 268/f cpu + 873 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 751 jul 15, 2010 table 27-16. interrupt response time for self programming library (expanded-specification products ( pd78f05xxa and 78f05xxda)) (1/2) (1) when internal high-speed oscillation clock is used interrupt response time ( s (max.)) normal model of c compiler static model of c compiler/assembler library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 1100.9 431.9 1095.3 426.3 block erase library 1452.9 783.9 1447.3 778.3 word write library 1247.2 579.2 1239.2 571.2 block verify library 1125.9 455.9 1120.3 450.3 set information library 906.9 312.0 905.8 311.0 eeprom write library 1215.2 547.2 1213.9 545.9 remarks 1. the above interrupt response times are those during stabilized operation of the internal high-speed oscillator (rsts = 1). 2. rsts: bit 7 of the internal oscillation mode register (rcm) (2) when high-speed system clock is used (normal model of c compiler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 179/f cpu + 567 179/f cpu + 246 179/f cpu + 1708 179/f cpu + 569 block erase library 179/f cpu + 780 179/f cpu + 459 179/f cpu + 1921 179/f cpu + 782 word write library 333/f cpu + 763 333/f cpu + 443 333/f cpu + 1871 333/f cpu + 767 block verify library 179/f cpu + 580 179/f cpu + 259 179/f cpu + 1721 179/f cpu + 582 set information library 80/f cpu + 456 80/f cpu + 200 80/f cpu + 1598 80/f cpu + 459 29/f cpu + 767 29/f cpu + 447 29/f cpu + 767 29/f cpu + 447 eeprom write library note 333/f cpu + 696 333/f cpu + 376 333/f cpu + 1838 333/f cpu + 700 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 752 jul 15, 2010 table 27-16. interrupt response time for self programming library (expanded-specification products ( pd78f05xxa and 78f05xxda)) (2/2) (3) when high-speed system clock is used (static model of c compiler/assembler) interrupt response time ( s (max.)) rstop = 0, rsts = 1 rstop = 1 library name entry ram location is outside short direct addressing range entry ram location is in short direct addressing range entry ram location is outside short direct addressing range entry ram location is in short direct addressing range block blank check library 136/f cpu + 567 136/f cpu + 246 136/f cpu + 1708 136/f cpu + 569 block erase library 136/f cpu + 780 136/f cpu + 459 136/f cpu + 1921 136/f cpu + 782 word write library 272/f cpu + 763 272/f cpu + 443 272/f cpu + 1871 272/f cpu + 767 block verify library 136/f cpu + 580 136/f cpu + 259 136/f cpu + 1721 136/f cpu + 582 set information library 72/f cpu + 456 72/f cpu + 200 72/f cpu + 1598 72/f cpu + 459 19/f cpu + 767 19/f cpu + 447 19/f cpu + 767 19/f cpu + 447 eeprom write library note 268/f cpu + 696 268/f cpu + 376 268/f cpu + 1838 268/f cpu + 700 note the longer value of the eeprom write library interrupt response time becomes the max. value, depending on the value of f cpu . remarks 1. f cpu : cpu operation clock frequency 2. rstop: bit 0 of the internal oscillation mode register (rcm) 3. rsts: bit 7 of the internal oscillation mode register (rcm) 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 753 jul 15, 2010 27.10.1 boot swap function if rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-pro gramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly wr itten to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78k0/kx2 microcontrollers , so that boot cluster 1 is used as a boot area. after that, erase or writ e the original boot program area, boot cluster 0. as a result, even if a power failure occurs while the boot programming area is being rewri tten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. if the program has been correctly written to boot cluster 0, re store the original boot area by using the set information function of the firmware of the 78k0/kx2 microcontrollers. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. boot cluster 0 (0000h to 0fffh ): original boot program area boot cluster 1 (1000h to 1fffh): area subject to boot swap function caution when executing boot swapping, do not use th e e.p.v command with the dedicated flash memory programmer. figure 27-15. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self programming to boot cluster 1 self programming to boot cluster 0 executing boot swapping by firmware executing boot swapping by firmware user program boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxh xxxxh 2000h 0000h 1000h 2000h 0000h 1000h boot boot boot boot boot remark boot cluster 1 becomes 0000h to 0fffh when a re set is generated after t he boot flag has been set. 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 754 jul 15, 2010 figure 27-16. example of executing boot swapping boot cluster 1 booted by boot cluster 0 booted by boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program program boot program 1000h 0000h 1000h 0000h 0000h 1000h erasing block 5 writing blocks 5 to 7 boot swap boot swap 3 2 1 0 7 6 5 4 boot program boot program boot program program program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program erasing block 6 erasing block 7 program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program erasing block 0 erasing block 1 erasing block 2 erasing block 3 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program writing blocks 0 to 3 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program 78k0/kx2 chapter 27 flash memory r01uh0008ej0401 rev.4.01 755 jul 15, 2010 27.11 creating rom code to place order for previously written product before placing an order with renesas electronics for a previ ously written product, the rom code for the order must be created. to create the rom code, use the hex co nsolidation utility (hereafter abbrevia ted to hcu) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). the hcu is a software tool that includes functions required for creating rom code. the hcu can be downloaded at t he renesas electronics website. (1) website http:www2.renesas.com/micro/en/ods click version-up service. (2) downloading the hcu to download the hcu, click software for previ ously written flash products and then hcu_gui. remark for details about how to install and use the hcu, s ee the materials (the user?s manual) that comes with the hcu at the above website. 27.11.1 procedure for using ro m code to place an order use the hcu to create the rom code by following the pr ocedure below, and then place your order with renesas electronics. for details, see the rom code ordering method information (c10302j). send the data required for the rom order. renesas electronics sends the order number and other order-related information. decide which product to order. check the rom order details and generate the required data. note use the hcu to create the rom code for the order. renesas electronics processes the rom code. create the rom code note send the order information. renesas electronics processes the product name and number and creates a record of the transaction. customer renesas electronics 78k0/kx2 chapter 28 on-chip debug function r01uh0008ej0401 rev.4.01 756 jul 15, 2010 chapter 28 on-chip debug function ( pd78f05xxd and 78f05xxda only) 28.1 connecting qb-mini2 to pd78f05xxd and 78f05xxda the pd78f05xxd and 78f05xxda use the v dd , flmd0, reset, ocd0a/x1 (or ocd1a/p31), ocd0b/x2 (or ocd1b/p32), and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). whether ocd0a/x1 and ocd1a/p31, or ocd0b/x2 and ocd1b/p32 are used can be selected. caution the pd78f05xxd and 78f05xxda have an on-chip debug function, which is provided for development and evaluation. do not use the on- chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and prod uct reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occu rring when the on-chip debug function is used. remark pd78f05xxd: pd78f0503d, 78f0513d, 78f0515d, 78f0527d, 78f0537d, 78f0547d pd78f05xxda: pd78f0503da, 78f0513da, 78f0515da, 78f0527da, 78f0537da, 78f0547da figure 28-1. connection example of qb-mini2 and pd78f05xxd and 78f05xxda (when ocd0a/x1 and ocd0b/x2 are used) v dd target device p31 flmd0 x1/ocd0a x2 /ocd0b reset signal reset_in note 1 data clk flmd0 reset v dd reset_out gnd target connector (10-pin) gnd note 2 v dd reset circuit v dd v dd gnd r.f.u. r.f.u. note 2 10 k (recommended) 1 k (recommended) (open) (open) notes 1. this connection is designed assuming that the reset si gnal is output from the n-ch open-drain buffer (output resistance: 100 or less). for details, refer to qb-mini2 user?s manual (u18371e) . 2. make pull-down resistor 470 or more (10 k : recommended). cautions 1. input the clock from the ocd0a/x1 pin during on-chip debugging. 2. control the ocd0a/x1 and o cd0b/x2 pins by externally pulling down the ocd1a/p31 pin or by using an external circuit using the p130 pin (that outputs a low le vel when the device is reset). 78k0/kx2 chapter 28 on-chip debug function r01uh0008ej0401 rev.4.01 757 jul 15, 2010 figure 28-2. connection example of qb-mini2 and pd78f05xxd and 78f05xxda (when ocd1a/p31 and ocd1b/p32 are used) v dd target device flmd0 ocd1a/p31 ocd1b/p32 reset signal reset_in note 1 data clk flmd0 reset v dd reset_out gnd target connector (10-pin) gnd note 3 v dd reset circuit v dd v dd gnd r.f.u. r.f.u. note 3 1 k (recommended) 10 k (recommended) (open) (open) v dd 3 to 10 k (recommended) note 2 notes 1. this connection is designed assuming that the reset si gnal is output from the n-ch open-drain buffer (output resistance: 100 ? or less). for details, refer to qb-mini2 user?s manual (u18371e) . 2. this is the processing of the pin when ocd1b/p32 is set as the input port (to prevent the pin from being left opened when not connected to qb-mini2). 3. make pull-down resistor 470 or more (10 k : recommended). connect the flmd0 pin as follows when performing se lf programming by means of on-chip debugging. figure 28-3. connection of flmd0 pin for self programming by means of on-chip debugging target connector flmd0 flmd0 target device port 1 k (recommended) 10 k (recommended) caution when using the port that controls the flmd0 pi n, make sure that it satis fies the values of the high- level output current and flmd0 supply voltage (minimum value: 0.8v dd ) stated in chapter 30 electrical specifications (standard products) to chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c). 78k0/kx2 chapter 28 on-chip debug function r01uh0008ej0401 rev.4.01 758 jul 15, 2010 28.2 reserved area used by qb-mini2 qb-mini2 uses the reserved areas shown in figure 28-4 below to implement communication with the pd78f05xxd and 78f05xxda, or each debug function. the shaded reserved areas are used for the respective debug functions to be used, and the other areas are always used for debugging. t hese reserved areas can be secured by using user programs and compiler options. when using a boot swap operation during self programming , set the same value to boot cluster 1 beforehand. for details on reserved area, refer to qb-mini2 user?s manual (u18371e) . figure 28-4. reserved area used by qb-mini2 debug monitor area (2 bytes) software break area (2 bytes) security id area (10 bytes) option byte area (1 byte) debug monitor area (257 bytes) pseudo rrm area (256 bytes) internal rom space internal ram space stack area for debugging (max. 16 bytes) pseudo rrm area (16 bytes) note ff7fh f7f0h 28fh 190h 18fh 8fh 8eh 85h 84h 7fh 7eh 03h 02h 00h note with products not incorporated the internal expansion ram ( pd78f0503d, 78f0503da, 78f0513d, and 78f0513da), it is not necessary to secure this area. remark shaded reserved areas: area used for the respective debug functions to be used other reserved areas: areas always used for debugging 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 759 jul 15, 2010 chapter 29 instruction set this chapter lists each instruction set of the 78k0/kx2 micr ocontrollers in table form. fo r details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 29.1 conventions used in operation list 29.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in acco rdance with the specif ication method of the instruction operand identifier (refer to the assembler specificat ions for details). when there are two or more methods, select one of them. uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function name s (x, a, c, etc.) or absolut e names (names in parentheses in the table below, r0, r1, r2, et c.) can be used for specification. table 29-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, see table 3-8 special function register list . 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 760 jul 15, 2010 29.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 29.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 761 jul 15, 2010 29.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 762 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 ax (addr16) movw !addr16, ax 3 10 12 (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) add a, [hl + c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + c a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 763 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 a, cy a ? (addr16) a, [hl] 1 4 5 a, cy a ? (hl) a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) a, [hl + b] 2 8 9 a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 a, cy a ? (addr16) ? cy a, [hl] 1 4 5 a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) 8-bit operation and a, [hl + c] 2 8 9 a a (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 764 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) or a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) xor a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 a ? (addr16) a, [hl] 1 4 5 a ? (hl) a, [hl + byte] 2 8 9 a ? (hl + byte) a, [hl + b] 2 8 9 a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 765 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 766 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 767 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (addr5 + 1), pc l (addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 768 jul 15, 2010 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1 (enable interrupt) di 2 ? 6 ie 0 (disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 769 jul 15, 2010 29.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cm p, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a? 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 770 jul 15, 2010 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 78k0/kx2 chapter 29 instruction set r01uh0008ej0401 rev.4.01 771 jul 15, 2010 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 772 jul 15, 2010 chapter 30 electrical specifications (standard products) target products conventional-specificati on products expanded-specification products 78k0/kb2 pd78f0500, 78f0501, 78f0502, 78f0503, 78f0503d pd78f0500a, 78f0501a, 78f0502a, 78f0503a, 78f0503da 78k0/kc2 pd78f0511, 78f0512, 78f0513, 78f0514, 78f0515, 78f0513d, 78f0515d pd78f0511a, 78f0512a, 78f0513a, 78f0514a, 78f0515a, 78f0513da, 78f0515da 78k0/kd2 pd78f0521, 78f0522, 78f0523, 78f0524, 78f0525, 78f0526, 78f0527, 78f0527d pd78f0521a, 78f0522a, 78f0523a, 78f0524a, 78f0525a, 78f0526a, 78f0527a, 78f0527da 78k0/ke2 pd78f0531, 78f0532, 78f0533, 78f0534, 78f0535, 78f0536, 78f0537, 78f0537d pd78f0531a, 78f0532a, 78f0533a, 78f0534a, 78f0535a, 78f0536a, 78f0537a, 78f0537da 78k0/kf2 pd78f0544, 78f0545, 78f0546, 78f0547, 78f0547d pd78f0544a, 78f0545a, 78f0546a, 78f0547a, 78f0547da the following items are described separately for conventional-specification products ( pd78f05xx, 78f05xxd) and expanded-specification products ( pd78f05xxa, 78f05xxda). ? x1 clock oscillation frequency ( x1 oscillator characteristics ) ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and exter nal main system clock input low-level width ( (1) basic operation in ac characteristics ) ? a/d conversion time ( a/d converter characteristics ) ? number of rewrites per chip ( flash memory programming characteristics ) cautions 1. the pd78f05xxd and 78f05xx da have an on-chip debug functi on, which is provided for development and evaluation. do not use the on-chip debug functi on in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability th erefore cannot be guaranteed. renesas electronics is not liable for problems o ccurring when the on-chip debug function is used. 2. the pins mounted depe nd on the product as follows. (1) port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins port 0 p00, p01 p00 to p03 p00 to p06 port 1 p10 to p17 port 2 p20 to p23 p20 to p25 p20 to p27 port 3 p30 to p33 port 4 ? p40, p41 p40 to p43 p40 to p47 port 5 ? p50 to p53 p50 to p57 port 6 p60, p61 p60 to p63 p60 to p67 port 7 ? p70, p71 p70 to p73 p70 to p75 p70 to p77 port 12 p120 to p122 p120 to p124 port 13 ? p130 port 14 ? p140 p140, p141 p140 to p145 (the remaining table is on the next page.) 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 773 jul 15, 2010 (2) non-port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins power supply, ground v dd , ev dd note 1 , v ss , ev ss note 1 , av ref , av ss v dd , av ref , v ss , av ss v dd , ev dd , v ss , ev ss , av ref , av ss regulator regc reset reset clock oscillation x1, x2, exclk x1, x2, xt1, xt2, exclk, exclks writing to flash memory flmd0 interrupt intp0 to intp5 intp0 to intp6 intp0 to intp7 key interrupt ? kr0, kr1 kr0 to kr3 kr0 to kr7 tm00 ti000, ti010, to00 tm01 ? ti001 note 2 , ti011 note 2 , to01 note 2 tm50 ti50, to50 tm51 ti51, to51 tmh0 toh0 timer tmh1 toh1 uart0 rxd0, txd0 uart6 rxd6, txd6 iic0 scl0, sda0 scl0, sda0, exscl0 csi10 sck10, si10, so10 csi11 ? sck11 note 2 , si11 note 2 , so11 note 2 , ssi11 note 2 serial interface csia0 ? scka0, sia0, soa0, busy0, stb0 a/d converter ani0 to ani3 ani0 to ani5 ani0 to ani7 clock output ? pcl buzzer output ? buz low-voltage detector (lvi) exlvi on-chip debug function ocd0a, ocd1a, ocd0b, ocd1b (mounted only onto pd78f05xxd and 78f05xxda (products with on-chip debug function)) notes 1. this is not mounted onto 30-pin products. 2. this is not mounted onto the 78k0/ke2 prod ucts whose flash memory is less than 32 kb. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 774 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc ?0.5 to +3.6 and ?0.5 to v dd v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120 to p124, p140 to p145, x1, x2, xt1, xt2, reset, flmd0 ? 0.3 to v dd + 0.3 note v input voltage v i2 p60 to p63 (n-ch open drain) ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ani0 to ani7 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even mome ntarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under condit ions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 775 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 ? 10 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 ? 25 ma total of all pins ? 80 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 ? 55 ma per pin ? 0.5 ma total of all pins p20 to p27 ? 2 ma per pin ? 1 ma output current, high i oh total of all pins p121 to p124 ? 4 ma per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p130, p140 to p145 30 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 60 ma total of all pins 200 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 140 ma per pin 1 ma total of all pins p20 to p27 5 ma per pin 4 ma output current, low i ol total of all pins p121 to p124 10 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolu te maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. 2. the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 776 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 note 2 20.0 2.7 v v dd < 4.0 v 1.0 note 2 10.0 conventional- specification products ( pd78f05xx, 78f05xxd) 1.8 v v dd < 2.7 v 1.0 5.0 2.7 v v dd 5.5 v 1.0 note 2 20.0 ceramic resonator, crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1 expanded- specification products ( pd78f05xxa, 78f05xxda) 1.8 v v dd < 2.7 v 1.0 5.0 mhz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. it is 2.0 mhz (min.) when programming on the board via uart6. cautions 1. when using the x1 oscillator, wire as follow s in the area enclosed by th e broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by th e internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the o scillation stabilization time counter status register (ostc) by the user. determine th e oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficientl y evaluating the oscillation stabilization time with the resonator to be used. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 777 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 8.0 8.4 mhz rsts = 1 1.8 v v dd < 2.7 v 7.6 8.0 10.4 mhz 8 mhz internal oscillator in ternal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 2.7 v v dd 5.5 v 216 240 264 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.7 v 192 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) xt1 oscillator characteristics note 1 (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 2 32 32.768 35 khz notes 1. the 78k0/kb2 is not provi ded with the xt1 oscillator. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscilla tor, wire as follows in the area enclo sed by the broken lines in the above figure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is design ed as a low-amplitude circuit for re ducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular ca re is therefore required with the wiring method when the xt1 clock is used. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 778 jul 15, 2010 recommended oscillato r constants (1/2) (1) x1 oscillation: ceramic resonator (t a = ? 40 to +85 c) (1/2) recommended circuit constants oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) min. (v) max. (v) cstcc2m00g56-r0 smd 2.00 internal (47) internal (47) cstls4m00g56-b0 lead internal (47) internal (47) cstcr4m00g55-r0 smd 4.00 internal (39) internal (39) cstls4m19g56-b0 lead internal (47) internal (47) cstcr4m19g55-r0 smd 4.194 internal (39) internal (39) cstls4m91g56-b0 lead internal (47) internal (47) cstcr4m91g55-r0 smd 4.915 internal (39) internal (39) 1.8 cstls5m00g56-b0 lead internal (47) internal (47) 1.9 cstcr5m00g55-r0 smd 5.00 internal (39) internal (39) 1.8 cstls6m00g56-b0 lead internal (47) internal (47) 2.4 cstcr6m00g55-r0 smd 6.00 internal (39) internal (39) 1.8 cstls8m00g56-b0 lead internal (47) internal (47) 2.3 cstce8m00g55-r0 smd 8.00 internal (33) internal (33) 1.9 cstls8m38g56-b0 lead internal (47) internal (47) 2.3 cstce8m38g55-r0 smd 8.388 internal (33) internal (33) 1.9 cstls10m0g56-b0 lead internal (47) internal (47) 2.5 cstce10m0g55-r0 smd 10.0 internal (33) internal (33) 2.3 cstce12m0g55-r0 smd 12.0 internal (33) internal (33) 2.3 cstce16m0v53-r0 smd 16.0 internal (15) internal (15) 2.3 murata mfg. co., ltd. cstce20m0v53-r0 smd 20.0 internal (15) internal (15) 2.6 5.5 cstls6m00g53-b0 lead 6.00 internal (15) internal (15) 1.8 cstls8m00g53-b0 lead 8.00 internal (15) internal (15) 1.8 cstls8m38g53-b0 lead 8.388 internal (15) internal (15) 1.8 cstls10m0g53-b0 lead 10.0 internal (15) internal (15) 1.8 cstce12m0g52-r0 smd 12.0 internal (10) internal (10) 1.8 cstce16m0v51-r0 smd 16.0 internal (5) internal (5) 1.8 murata mfg. co., ltd. (low-capacitance products) cstce20m0v51-r0 smd 20.0 internal (5) internal (5) 1.9 5.5 caution the oscillator constants shown above are refere nce values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necessar y to optimize the oscillator characteristics in the actual appl ication, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage an d oscillation frequency only indicate the oscillator characteristic. use the 78k0/k x2 so that the internal opera tion conditions are within the specifications of the dc and ac characteristics. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 779 jul 15, 2010 recommended oscillato r constants (2/2) (1) x1 oscillation: ceramic resonator (t a = ? 40 to +85 c) (2/2) recommended circuit constants oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) min. (v) max. (v) ccr4.0muc8 smd internal (27) internal (27) fcr4.0mc5 lead 4.00 internal (30) internal (30) ccr8.0mxc8 smd internal (18) internal (30) tdk corporation fcr8.0mc5 lead 8.00 internal (20) internal (20) 1.8 5.5 caution the oscillator constants shown above are refere nce values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necessar y to optimize the oscillator characteristics in the actual appl ication, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage an d oscillation frequency only indicate the oscillator characteristic. use the 78k0/k x2 so that the internal opera tion conditions are within the specifications of the dc and ac characteristics. (2) xt1 oscillation: crystal resonator (t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range v dd = 3.3 v v dd = 5.0 v manufacturer part number smd/ lead frequency (mhz) load capacitance cl (pf) c3 (pf) c4 (pf) rd (k ) c3 (pf) c4 (pf) rd (k ) min. (v) max. (v) 6.0 4 3 100 6 5 100 seiko instruments inc. vt-200 lead 32.768 12.5 15 15 100 18 15 100 1.8 5.5 caution the oscillator constants shown above are refere nce values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necessar y to optimize the oscillator characteristics in the actual appl ication, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage an d oscillation frequency only indicate the oscillator characteristic. use the 78k0/ke2 so that th e internal operation cond itions are within the specifications of the dc and ac characteristics. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 780 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. dc characteristics (1/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 2.5 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 note 3 1.8 v v dd < 2.7 v ? 10.0 ma 4.0 v v dd 5.5 v ? 50.0 ma 2.7 v v dd < 4.0 v ? 29.0 ma i oh1 total of all the pins above note 3 1.8 v v dd < 2.7 v ? 15.0 ma per pin for p20 to p27 av ref = v dd ? 0.1 ma output current, high note 1 i oh2 per pin for p121 to p124 ? 0.1 ma 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p60 to p63 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 45.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 note 3 1.8 v v dd < 2.7 v 20.0 ma 4.0 v v dd 5.5 v 65.0 ma 2.7 v v dd < 4.0 v 50.0 ma i ol1 total of all the pins above note 3 1.8 v v dd < 2.7 v 29.0 ma per pin for p20 to p27 av ref = v dd 0.4 ma output current, low note 2 i ol2 per pin for p121 to p124 0.4 ma notes 1. value of current at which the device operatio n is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the device operation is guarant eed even if the current flows from an output pin to gnd. 3. specification under conditions w here the duty factor is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be ca lculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 781 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. dc characteristics (2/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p121 to p124, p144, p145, exclk, exclks 0.7v dd v dd v v ih2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is at least 48 kb) note 1 v ih4 p60 to p63 0.7v dd 6.0 v v ih1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p121 to p124, exclk, exclks 0.7v dd v dd v v ih2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is less than 32 kb) note 2 v ih4 p60 to p63 0.7v dd 6.0 v v il1 p02, p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p121 to p124, p144, p145, exclk, exclks 0 0.3v dd v v il2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, reset 0 0.2v dd v input voltage, low (products whose flash memory is at least 48 kb) note 1 v il3 p20 to p27 av ref = v dd 0 0.3av ref v v il1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p60 to p63, p121 to p124, exclk, exclks 0 0.3v dd v v il2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, reset 0 0.2v dd v input voltage, low (products whose flash memory is less than 32 kb) note 2 v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd < 4.0 v, i oh1 = ? 2.5 ma v dd ? 0.5 v v oh1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v, i oh1 = ? 1.0 ma v dd ? 0.5 v p20 to p27 av ref = v dd , i oh2 = ? 100 a v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i oh2 = ? 100 a v dd ? 0.5 v notes 1. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is at least 48 kb, and 78k0/kf2 2. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is less than 32 kb, 78k0/kb2, and 78k0/kc2 remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 782 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. dc characteristics (3/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.7 v 1.8 v v dd < 2.7 v, i oh1 = 2.0 ma 0.5 v v ol1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v, i ol1 = 0.5 ma 0.4 v p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v v ol2 p121 to p124 i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.6 v 2.7 v v dd < 4.0 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.4 v i lih1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v dd 1 a i lih2 p20 to p27 v i = av ref = v dd 1 a i/o port mode 1 a input leakage current, high i lih3 p121 to 124 (x1, x2, xt1, xt2) v i = v dd osc mode 20 a i lil1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v ss ? 1 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 1 a i/o port mode ? 1 a input leakage current, low i lil3 p121 to 124 (x1, x2, xt1, xt2) v i = v ss osc mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 783 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. dc characteristics (4/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.2 5.5 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 4.5 6.9 ma square wave input 1.6 2.8 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 2.3 3.9 ma square wave input 1.5 2.7 ma f xh = 10 mhz, v dd = 3.0 v notes 2, 3 resonator connection 2.2 3.2 ma square wave input 0.9 1.6 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 1.3 2.0 ma square wave input 0.7 1.4 ma f xh = 5 mhz, v dd = 2.0 v notes 2, 3 resonator connection 1.0 1.6 ma f rh = 8 mhz, v dd = 5.0 v note 4 1.4 2.5 ma square wave input 6 25 a i dd1 operating mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 15 30 a square wave input 0.8 2.6 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 2.0 4.4 ma square wave input 0.4 1.3 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 1.0 2.4 ma square wave input 0.2 0.65 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.5 1.1 ma f rh = 8 mhz, v dd = 5.0 v note 4 0.4 1.2 ma square wave input 3.0 22 a i dd2 halt mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 12 25 a stop mode 1 20 a supply current note 1 i dd3 note 6 t a = ? 40 to +70 c 1 10 a a/d converter operating current i adc note 7 2.3 v av ref v dd , adcs = 1 0.86 1.9 ma watchdog timer operating current i wdt note 8 during 240 khz internal low-speed oscillation clock operation 5 10 a lvi operating current i lvi note 9 9 18 a remarks 1. f xh : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency or external subsystem clock frequency) (notes on next page) 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 784 jul 15, 2010 notes 1. total current flowing into the internal power supply (v dd, ev dd ), including the periphe ral operation current and the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the out put current of the port are not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, 240 khz internal oscillator, and xt1 oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillat or, xt1 oscillator, and 240 khz internal oscillator, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 5. not including the operating current of the x1 osc illator, 8 mhz internal oscillator, and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 7. current flowing only to the a/d converter (av ref ). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 8. current flowing only to the watchdog timer (including the operating current of the 240 khz internal oscillator). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 9. current flowing only to the lvi circuit. the current value of the 78k0/kx2 microc ontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 785 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. ac characteristics (1) basic operation (1/2) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s 2.7 v v dd < 4.0 v 0.2 32 s conventional- specification products ( pd78f05xx, 78f05xxd) 1.8 v v dd < 2.7 v 0.4 note 1 32 s 2.7 v v dd 5.5 v 0.1 32 s main system clock (f xp ) operation expanded- specification products ( pd78f05xxa, 78f05xxda) 1.8 v v dd < 2.7 v 0.4 note 1 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 2 114 122 125 s 4.0 v v dd 5.5 v 20 mhz 2.7 v v dd < 4.0 v 10 mhz conventional- specification products ( pd78f05xx, 78f05xxd) 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 20 mhz 2.7 v v dd < 4.0 v note 3 20 mhz f prs = f xh (xsel = 1) expanded- specification products ( pd78f05xxa, 78f05xxda) 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 mhz peripheral hardware clock frequency f prs f prs = f rh (xsel = 0) 1.8 v v dd < 2.7 v note 4 7.6 10.4 mhz 4.0 v v dd 5.5 v 1.0 note 5 20.0 mhz 2.7 v v dd < 4.0 v 1.0 note 5 10.0 mhz conventional-specification products ( pd78f05xx, 78f05xxd) 1.8 v v dd < 2.7 v 1.0 5.0 mhz 2.7 v v dd 5.5 v 1.0 note 5 20.0 mhz external main system clock frequency f exclk expanded-specification products ( pd78f05xxa, 78f05xxda) 1.8 v v dd < 2.7 v 1.0 5.0 mhz 4.0 v v dd 5.5 v 24 ns 2.7 v v dd < 4.0 v 48 ns conventional-specification products ( pd78f05xx, 78f05xxd) 1.8 v v dd < 2.7 v 96 ns 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exclkh , t exclkl expanded-specification products ( pd78f05xxa, 78f05xxda) 1.8 v v dd < 2.7 v 96 ns notes 1. 0.38 s when operating with the 8 mhz internal oscillator. 2. the 78k0/kb2 is not provi ded with a subsystem clock. 3. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f xh /2 (10 mhz) or less. the multiplier /divider, however, can operate on f xh (20 mhz). 4. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f rh /2 or less. 5. 2.0 mhz (min.) when using uart6 during on-board programming. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 786 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (1) basic operation (2/2) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit external subsystem clock frequency note 1 f exclks 32 32.768 35 khz external subsystem clock input high-level width, low-level width note 1 t exclksh , t exclksl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 2 s ti000, ti010, ti001, ti011 input high-level width, low-level width t tih0 , t til0 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 50 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. selection of f sam = f prs , f prs /4, f prs /256, or f prs , f prs /16, f prs /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode regi sters 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f prs. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 787 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. t cy vs. v dd (main system clock operation) <1> conventional-specification products ( pd78f05xx, 78f05xxd) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) <2> expanded-specification products ( pd78f05xxa, 78f05xxda) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 788 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. ac timing test points v ih v il test points v ih v il external main system clock timing , external subsystem clock timing exclk 0.7v dd (min.) 0.3v dd (max.) 1/f exclk t exclkl t exclkh 1/f exclks t exclksl t exclksh exclks 0.7v dd (min.) 0.3v dd (max.) ti timing ti000, ti010, ti001, ti011 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 789 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 790 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (c) iic0 standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of restart condition t su: sta 4.7 ? 0.6 ? s hold time note 1 t hd: sta 4.0 ? 0.6 ? s internal clock operation 4.7 ? 1.3 ? s hold time when scl0 = ?l? t low exscl0 clock (6.4 mhz) operation 4.7 ? 1.25 ? s hold time when scl0 = ?h? t high 4.0 ? 0.6 ? s data setup time (reception) t su: dat 250 ? 100 ? ns 0.9 note 4 f w = f xh /2 n or f w = f exscl0 selected note 3 0 3.45 0 1.00 note 5 s data hold time (transmission) note 2 t hd: dat f w = f rh /2 n selected note 3 0 3.45 0 1.05 s setup time of stop condition t su: sto 4.0 ? 0.6 ? s bus free time t buf 4.7 ? 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. f w indicates the iic0 transfer clock selected by the ii ccl and iicx0 registers. 4. when f w 4.4 mhz is selected 5. when f w < 4.4 mhz is selected 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 791 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (d) csi1n (master mode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 160 ns 2.7 v v dd < 4.0 v 250 ns sck1n cycle time t kcy1 1.8 v v dd < 2.7 v 500 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 15 note 1 ns 2.7 v v dd < 4.0 v t kcy1 /2 ? 25 note 1 ns sck1n high-/low-level width t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 50 note 1 ns 4.0 v v dd 5.5 v 55 ns 2.7 v v dd < 4.0 v 80 ns si1n setup time (to sck1n ) t sik1 1.8 v v dd < 2.7 v 170 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck1n and so1n output lines. (e) csi1n (slave mode, sck1 n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns 4.0 v v dd 5.5 v 120 ns 2.7 v v dd < 4.0 v 120 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 1.8 v v dd < 2.7 v 165 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 792 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (f) csia0 (master mode, scka0?internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy3 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v t kcy3 /2 ? 50 ns 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns scka0 high-/low-level width t kh3 , t kl3 1.8 v v dd < 2.7 v t kcy3 /2 ? 200 ns 2.7 v v dd 5.5 v 100 ns sia0 setup time (to scka0 ) t sik3 1.8 v v dd < 2.7 v 200 ns sia0 hold time (from scka0 ) t ksi3 300 ns 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 300 ns delay time from scka0 to soa0 output t kso3 c = 100 pf note 1.8 v v dd < 2.7 v 400 ns time from scka0 to stb0 t sbd t kcy3 /2 ? 100 ns 4.0 v v dd 5.5 v t kcy3 ? 30 ns 2.7 v v dd < 4.0 v t kcy3 ? 60 ns strobe signal high-level width t sbw 1.8 v v dd < 2.7 v t kcy3 ? 120 ns 2.7 v v dd 5.5 v 100 ns busy signal setup time (to busy signal detection timing) t bys 1.8 v v dd < 2.7 v 200 ns busy signal hold time (from busy signal detection timing) t byh 100 ns 4.0 v v dd 5.5 v 2t kcy3 + 100 ns 2.7 v v dd < 4.0 v 2t kcy3 + 150 ns time from busy inactive to scka0 t sps 1.8 v v dd < 2.7 v 2t kcy3 + 200 ns note c is the load capacitance of the scka0 and soa0 output lines. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 793 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (g) csia0 (slave mode, scka0?external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy4 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v 300 ns 2.7 v v dd < 4.0 v 600 ns scka0 high-/low-level width t kh4 , t kl4 1.8 v v dd < 2.7 v 900 ns sia0 setup time (to scka0 ) t sik4 100 ns sia0 hold time (from scka0 ) t ksi4 2/f w + 100 note 1 ns 4.0 v v dd 5.5 v 2/f w + 100 note 1 ns 2.7 v v dd < 4.0 v 2/f w + 200 note 1 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 2 1.8 v v dd < 2.7 v 2/f w + 300 note 1 ns scka0 rise/fall time t r4 , t f4 1000 ns notes 1. f w is the csia0 base clock selected by the csis0 register. 2. c is the load capacitance of the soa0 output line. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 794 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. serial transfer timing (1/2) iic0: t low t high t hd: sta stop condition start condition restart condition stop condition t su: dat t su: sta t hd: sta t hd: dat scl0 sda0 t buf t su: sto csi1n: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 795 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. serial transfer timing (2/2) csia0: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw csia0 (busy processing): t byh t sps t bys 789 note 10 note 10 + n note 1 scka0 busy0 (active-high) note scka0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 796 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. a/d converter characteristics (t a = ? 40 to +85 c, 2.3 v av ref v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 a inl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s 2.7 v av ref < 4.0 v 12.2 36.7 s conventional- specification products ( pd78f05xx, 78f05xxd) 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 6.1 66.6 s 2.7 v av ref < 4.0 v 12.2 66.6 s conversion time t conv expanded- specification products ( pd78f05xxa, 78f05xxda) 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr zero-scale error notes 1, 2 e zs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error notes 1, 2 e fs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 i le 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 d le 2.3 v av ref < 2.7 v 2.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 797 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. 1.59 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power supply voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s 1.59 v poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw supply voltage rise time (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) (v dd : 0 v 1.8 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) (releasing reset input v dd : 1.8 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 1.8 v t pup1 supply voltage (v dd ) time 1.8 v t pup2 v poc reset pin 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 798 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. 2.7 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v remark the operations of the poc circuit are as described below, depending on the pocmode (option byte) setting. option byte setting poc mode operation pocmode = 0 1.59 v mode operation a reset state is retained until v poc = 1.59 v (typ.) is reached after the power is turned on, and the reset is released when v poc is exceeded. after that, poc detection is performed at v poc , similarly as when the power was turned on. the power supply voltage must be raised at a time of t pup1 or t pup2 when pocmode is 0. pocmode = 1 2.7 v/1.59 v mode operation a reset state is retained until v ddpoc = 2.7 v (typ.) is reached after the power is turned on, and the reset is released when v ddpoc is exceeded. after that, poc detection is performed at v poc = 1.59 v (typ.) and not at v ddpoc . the use of the 2.7 v/1.59 v poc mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 v, is more relaxed than t pth . 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 799 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 1.98 2.08 2.18 v supply voltage level v lvi15 1.83 1.93 2.03 v detection voltage external input pin note 1 exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 800 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detection voltage. when the voltage drops, t he data is retained until a poc reset is effected, but data is not retai ned when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 78k0/kx2 chapter 30 electrical specifications (standard products) r01uh0008ej0401 rev.4.01 801 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. flash memory programming characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 11.0 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s ? when a flash memory programmer is used, and the libraries note 4 provided by renesas electronics are used ? for program update retention: 15 years 1000 times expanded- specification products ( pd78f05xxa, 78f05xxda) ? when the eeprom emulation libraries note 5 provided by renesas electronics are used ? the rewritable rom size: 4 kb ? for data update retention: 5 years 10000 times expanded- specification products ( pd78f05xxa, 78f05xxda) number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 conventional- specification products ( pd78f05xx, 78f05xxd) conditions other than the above note 6 retention: 10 years 100 times notes 1. characteristic of the flash memory. for the characte ristic when a dedicated flash programmer, pg-fp4 or pg- fp5, is used and the rewrite ti me during self programming, see tables 27-12 to 27-14 . 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. 4. the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) is excluded. 5. the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) is excluded. 6. these include when the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) and the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) are used. remarks 1. f xp : main system clock oscillation frequency 2. for serial write operation characteristics, refer to 78k0/kx2 flash memory programming (programmer) application note ( document no.: u17739e) . 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 802 jul 15, 2010 chapter 31 electrical specif ications ((a) grade products) target products conventional-specificati on products expanded-specification products 78k0/kb2 pd78f0500(a), 78f0501(a), 78f0502(a), 78f0503(a) pd78f0500a(a), 78f0501a(a), 78f0502a(a), 78f0503a(a) 78k0/kc2 pd78f0511(a), 78f0512(a), 78f0513(a), 78f0514(a), 78f0515(a) pd78f0511a(a), 78f0512a(a), 78f0513a(a), 78f0514a(a), 78f0515a(a) 78k0/kd2 pd78f0521(a), 78f0522(a), 78f0523(a), 78f0524(a), 78f0525(a), 78f0526(a), 78f0527(a) pd78f0521a(a), 78f0522a(a), 78f0523a(a), 78f0524a(a), 78f0525a(a), 78f0526a(a), 78f0527a(a) 78k0/ke2 pd78f0531(a), 78f0532(a), 78f0533(a), 78f0534(a), 78f0535(a), 78f0536(a), 78f0537(a) pd78f0531a(a), 78f0532a(a), 78f0533a(a), 78f0534a(a), 78f0535a(a), 78f0536a(a), 78f0537a(a) 78k0/kf2 pd78f0544(a), 78f0545(a), 78f0546(a), 78f0547(a) pd78f0544a(a), 78f0545a(a), 78f0546a(a), 78f0547a(a) the following items are described separately for conventional-specification products ( pd78f05xx(a)) and expanded- specification products ( pd78f05xxa(a)). ? x1 clock oscillation frequency ( x1 oscillator characteristics ) ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and exter nal main system clock input low-level width ( (1) basic operation in ac characteristics ) ? a/d conversion time ( a/d converter characteristics ) ? number of rewrites per chip ( flash memory programming characteristics ) caution the pins mounted de pend on the product as follows. (1) port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins port 0 p00, p01 p00 to p03 p00 to p06 port 1 p10 to p17 port 2 p20 to p23 p20 to p25 p20 to p27 port 3 p30 to p33 port 4 ? p40, p41 p40 to p43 p40 to p47 port 5 ? p50 to p53 p50 to p57 port 6 p60, p61 p60 to p63 p60 to p67 port 7 ? p70, p71 p70 to p73 p70 to p75 p70 to p77 port 12 p120 to p122 p120 to p124 port 13 ? p130 port 14 ? p140 p140, p141 p140 to p145 (the remaining table is on the next page.) 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 803 jul 15, 2010 (2) non-port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins power supply, ground v dd , ev dd note 1 , v ss , ev ss note 1 , av ref , av ss v dd , av ref , v ss , av ss v dd , ev dd , v ss , ev ss , av ref , av ss regulator regc reset reset clock oscillation x1, x2, exclk x1, x2, xt1, xt2, exclk, exclks writing to flash memory flmd0 interrupt intp0 to intp5 intp0 to intp6 intp0 to intp7 key interrupt ? kr0, kr1 kr0 to kr3 kr0 to kr7 tm00 ti000, ti010, to00 tm01 ? ti001 note 2 , ti011 note 2 , to01 note 2 tm50 ti50, to50 tm51 ti51, to51 tmh0 toh0 timer tmh1 toh1 uart0 rxd0, txd0 uart6 rxd6, txd6 iic0 scl0, sda0 scl0, sda0, exscl0 csi10 sck10, si10, so10 csi11 ? sck11 note 2 , si11 note 2 , so11 note 2 , ssi11 note 2 serial interface csia0 ? scka0, sia0, soa0, busy0, stb0 a/d converter ani0 to ani3 ani0 to ani5 ani0 to ani7 clock output ? pcl buzzer output ? buz low-voltage detector (lvi) exlvi notes 1. this is not mounted onto 30-pin products. 2. this is not mounted onto the 78k0/ke2 prod ucts whose flash memory is less than 32 kb. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 804 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc ? 0.5 to +3.6 and ? 0.5 to v dd v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120 to p124, p140 to p145, x1, x2, xt1, xt2, reset, flmd0 ? 0.3 to v dd + 0.3 note v input voltage v i2 p60 to p63 (n-ch open drain) ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ani0 to ani7 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even mome ntarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under condit ions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 805 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 ? 10 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 ? 25 ma total of all pins ? 80 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 ? 55 ma per pin ? 0.5 ma total of all pins p20 to p27 ? 2 ma per pin ? 1 ma output current, high i oh total of all pins p121 to p124 ? 4 ma per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p130, p140 to p145 30 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 60 ma total of all pins 200 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 140 ma per pin 1 ma total of all pins p20 to p27 5 ma per pin 4 ma output current, low i ol total of all pins p121 to p124 10 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolu te maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. 2. the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 806 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 note 2 20.0 2.7 v v dd < 4.0 v 1.0 note 2 10.0 conventional- specification products ( pd78f05xx (a)) 1.8 v v dd < 2.7 v 1.0 5.0 mhz 2.7 v v dd 5.5 v 1.0 note 2 20.0 ceramic resonator, crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1 expanded- specification products ( pd78f05xxa (a)) 1.8 v v dd < 2.7 v 1.0 5.0 mhz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. it is 2.0 mhz (min.) when programming on the board via uart6. cautions 1. when using the x1 oscillator, wire as follow s in the area enclosed by th e broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by th e internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the o scillation stabilization time counter status register (ostc) by the user. determine th e oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficientl y evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 807 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 8.0 8.4 mhz rsts = 1 1.8 v v dd < 2.7 v 7.6 8.0 10.4 mhz 8 mhz internal oscillator in ternal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 2.7 v v dd 5.5 v 216 240 264 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.7 v 192 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) xt1 oscillator characteristics note 1 (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 2 32 32.768 35 khz notes 1. the 78k0/kb2 is not provi ded with the xt1 oscillator. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscilla tor, wire as follows in the area enclo sed by the broken lines in the above figure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is design ed as a low-amplitude circuit for re ducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular ca re is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 808 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (1/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 2.5 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 12.0 ma 2.7 v v dd < 4.0 v ? 7.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 18.0 ma 2.7 v v dd < 4.0 v ? 15.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 note 3 1.8 v v dd < 2.7 v ? 10.0 ma 4.0 v v dd 5.5 v ? 23.0 ma 2.7 v v dd < 4.0 v ? 20.0 ma i oh1 total of all the pins above note 3 1.8 v v dd < 2.7 v ? 15.0 ma per pin for p20 to p27 av ref = v dd ? 0.1 ma output current, high note 1 i oh2 per pin for p121 to p124 ? 0.1 ma 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p60 to p63 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 45.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 note 3 1.8 v v dd < 2.7 v 20.0 ma 4.0 v v dd 5.5 v 65.0 ma 2.7 v v dd < 4.0 v 50.0 ma i ol1 total of all the pins above note 3 1.8 v v dd < 2.7 v 29.0 ma per pin for p20 to p27 av ref = v dd 0.4 ma output current, low note 2 i ol2 per pin for p121 to p124 0.4 ma notes 1. value of current at which the device operatio n is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the device operation is guarant eed even if the current flows from an output pin to gnd. 3. specification under conditions w here the duty factor is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be ca lculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 809 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (2/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p121 to p124, p144, p145 0.7v dd v dd v v ih2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is at least 48 kb) note 1 v ih4 p60 to p63 0.7v dd 6.0 v v ih1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is less than 32 kb) note 2 v ih4 p60 to p63 0.7v dd 6.0 v v il1 p02, p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p121 to p124, p144, p145 0 0.3v dd v v il2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is at least 48 kb) note 1 v il3 p20 to p27 av ref = v dd 0 0.3av ref v v il1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p60 to p63, p121 to p124 0 0.3v dd v v il2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is less than 32 kb) note 2 v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd < 4.0 v, i oh1 = ? 2.5 ma v dd ? 0.5 v v oh1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v, i oh1 = ? 1.0 ma v dd ? 0.5 v p20 to p27 av ref = v dd , i oh2 = ? 100 a v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i oh2 = ? 100 a v dd ? 0.5 v notes 1. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is at least 48 kb, and 78k0/kf2 2. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is less than 32 kb, 78k0/kb2, and 78k0/kc2 remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 810 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (3/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.7 v 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.5 v v ol1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 1.8 v v dd < 2.7 v, i ol1 = 0.5 ma 0.4 v p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v v ol2 p121 to p124 i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.6 v 2.7 v v dd < 4.0 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.4 v i lih1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v dd 1 a i lih2 p20 to p27 v i = av ref = v dd 1 a i/o port mode 1 a input leakage current, high i lih3 p121 to 124 (x1, x2, xt1, xt2) v i = v dd osc mode 20 a i lil1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v ss ? 1 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 1 a i/o port mode ? 1 a input leakage current, low i lil3 p121 to 124 (x1, x2, xt1, xt2) v i = v ss osc mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 811 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (4/4) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.2 5.5 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 4.5 6.9 ma square wave input 1.6 2.8 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 2.3 3.9 ma square wave input 1.5 2.7 ma f xh = 10 mhz v dd = 3.0 v notes 2, 3 resonator connection 2.2 3.2 ma square wave input 0.9 1.6 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 1.3 2.0 ma square wave input 0.7 1.4 ma f xh = 5 mhz, v dd = 2.0 v notes 2, 3 resonator connection 1.0 1.6 ma f rh = 8 mhz, v dd = 5.0 v note 4 1.4 2.5 ma square wave input 6 30 a i dd1 operating mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 15 35 a square wave input 0.8 2.6 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 2.0 4.4 ma square wave input 0.4 1.3 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 1.0 2.4 ma square wave input 0.2 0.65 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.5 1.1 ma f rh = 8 mhz, v dd = 5.0 v note 4 0.4 1.2 ma square wave input 3.0 27 a i dd2 halt mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 12 32 a stop mode 1 20 a supply current note 1 i dd3 note 6 t a = ? 40 to +70 c 1 10 a a/d converter operating current i adc note 7 2.3 v av ref v dd , adcs = 1 0.86 1.9 ma watchdog timer operating current i wdt note 8 during 240 khz internal low-speed oscillation clock operation 5 10 a lvi operating current i lvi note 9 9 18 a remarks 1. f xh : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency or external subsystem clock frequency) (notes on next page) 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 812 jul 15, 2010 notes 1. total current flowing into the internal power supply (v dd, ev dd ), including the periphe ral operation current and the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the out put current of the port are not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, 240 khz internal oscillator, and xt1 oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillat or, xt1 oscillator, and 240 khz internal oscillator, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 5. not including the operating current of the x1 osc illation, 8 mhz internal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 7. current flowing only to the a/d converter (av ref ). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 8. current flowing only to the watchdog timer (including the operating current of the 240 khz internal oscillator). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 9. current flowing only to the lvi circuit. the current value of the 78k0/kx2 microc ontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 813 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac characteristics (1) basic operation (1/2) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s 2.7 v v dd < 4.0 v 0.2 32 s conventional- specification products ( pd78f05xx (a)) 1.8 v v dd < 2.7 v 0.4 note 1 32 s 2.7 v v dd 5.5 v 0.1 32 s main system clock (f xp ) operation expanded- specification products ( pd78f05xxa (a)) 1.8 v v dd < 2.7 v 0.4 note 1 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 2 114 122 125 s 4.0 v v dd 5.5 v 20 mhz 2.7 v v dd < 4.0 v 10 mhz conventional- specification products ( pd78f05xx (a)) 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 20 mhz 2.7 v v dd < 4.0 v note 3 20 mhz f prs = f xh (xsel = 1) expanded- specification products ( pd78f05xxa (a)) 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 mhz peripheral hardware clock frequency f prs f prs = f rh (xsel = 0) 1.8 v v dd < 2.7 v note 4 7.6 10.4 mhz 4.0 v v dd 5.5 v 1.0 note 5 20.0 mhz 2.7 v v dd < 4.0 v 1.0 note 5 10.0 mhz conventional-specification products ( pd78f05xx(a)) 1.8 v v dd < 2.7 v 1.0 5.0 mhz 2.7 v v dd 5.5 v 1.0 note 5 20.0 mhz external main system clock frequency f exclk expanded-specification products ( pd78f05xxa(a)) 1.8 v v dd < 2.7 v 1.0 5.0 mhz 4.0 v v dd 5.5 v 24 ns 2.7 v v dd < 4.0 v 48 ns conventional-specification products ( pd78f05xx(a)) 1.8 v v dd < 2.7 v 96 ns 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exclkh , t exclkl expanded-specification products ( pd78f05xxa(a)) 1.8 v v dd < 2.7 v 96 ns notes 1. 0.38 s when operating with the 8 mhz internal oscillator. 2. the 78k0/kb2 is not provi ded with a subsystem clock. 3. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f xh /2 (10 mhz) or less. the multiplier /divider, however, can operate on f xh (20 mhz). 4. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f rh /2 or less. 5. 2.0 mhz (min.) when using uart6 during on-board programming. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 814 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (1) basic operation (2/2) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit external subsystem clock frequency note 1 f exclks 32 32.768 35 khz external subsystem clock input high-level width, low-level width note 1 t exclksh , t exclksl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 2 s ti000, ti010, ti001, ti011 input high-level width, low-level width t tih0 , t til0 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 50 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. selection of f sam = f prs , f prs /4, f prs /256, or f prs , f prs /16, f prs /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode regi sters 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f prs. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 815 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. t cy vs. v dd (main system clock operation) <1> conventional-specification products ( pd78f05xx(a)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) <2> expanded-specification products ( pd78f05xxa(a)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 816 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac timing test points v ih v il test points v ih v il external main system clock timing , external subsystem clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f exclk t exclkl t exclkh 1/f exclks t exclksl t exclksh exclks 0.8v dd (min.) 0.2v dd (max.) 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 817 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ti timing ti000, ti010, ti001, ti011 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 818 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (c) iic0 standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of restart condition t su: sta 4.7 ? 0.6 ? s hold time note 1 t hd: sta 4.0 ? 0.6 ? s internal clock operation 4.7 ? 1.3 ? s hold time when scl0 = ?l? t low exscl0 clock (6.4 mhz) operation 4.7 ? 1.25 ? s hold time when scl0 = ?h? t high 4.0 ? 0.6 ? s data setup time (reception) t su: dat 250 ? 100 ? ns 0.9 note 4 f w = f xh /2 n or f w = f exscl0 selected note 3 0 3.45 0 1.00 note 5 s data hold time (transmission) note 2 t hd: dat f w = f rh /2 n selected note 3 0 3.45 0 1.05 s setup time of stop condition t su: sto 4.0 ? 0.6 ? s bus free time t buf 4.7 ? 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. f w indicates the iic0 transfer clock selected by the ii ccl and iicx0 registers. 4. when f w 4.4 mhz is selected 5. when f w < 4.4 mhz is selected 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 819 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (d) csi1n (master mode, sck1n? internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 400 ns sck1n cycle time t kcy1 1.8 v v dd < 2.7 v 600 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 note 1 ns 2.7 v v dd < 4.0 v t kcy1 /2 ? 30 note 1 ns sck1n high-/low-level width t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 60 note 1 ns 4.0 v v dd 5.5 v 70 ns 2.7 v v dd < 4.0 v 100 ns si1n setup time (to sck1n ) t sik1 1.8 v v dd < 2.7 v 190 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck1n and so1n output lines. (e) csi1n (slave mode, sck1n? external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns 4.0 v v dd 5.5 v 120 ns 2.7 v v dd < 4.0 v 120 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 1.8 v v dd < 2.7 v 180 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 820 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (f) csia0 (master mode, scka0?internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy3 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v t kcy3 /2 ? 50 ns 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns scka0 high-/low-level width t kh3 , t kl3 1.8 v v dd < 2.7 v t kcy3 /2 ? 200 ns 2.7 v v dd 5.5 v 100 ns sia0 setup time (to scka0 ) t sik3 1.8 v v dd < 2.7 v 200 ns sia0 hold time (from scka0 ) t ksi3 300 ns 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 300 ns delay time from scka0 to soa0 output t kso3 c = 100 pf note 1.8 v v dd < 2.7 v 400 ns time from scka0 to stb0 t sbd t kcy3 /2 ? 100 ns 4.0 v v dd 5.5 v t kcy3 ? 30 ns 2.7 v v dd < 4.0 v t kcy3 ? 60 ns strobe signal high-level width t sbw 1.8 v v dd < 2.7 v t kcy3 ? 120 ns 2.7 v v dd 5.5 v 100 ns busy signal setup time (to busy signal detection timing) t bys 1.8 v v dd < 2.7 v 200 ns busy signal hold time (from busy signal detection timing) t byh 100 ns 4.0 v v dd 5.5 v 2t kcy3 + 100 ns 2.7 v v dd < 4.0 v 2t kcy3 ? 150 ns time from busy inactive to scka0 t sps 1.8 v v dd < 2.7 v 2t kcy3 ? 200 ns note c is the load capacitance of the scka0 and soa0 output lines. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 821 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (g) csia0 (slave mode, scka0?external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy4 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v 300 ns 2.7 v v dd < 4.0 v 600 ns scka0 high-/low-level width t kh4 , t kl4 1.8 v v dd < 2.7 v 900 ns sia0 setup time (to scka0 ) t sik4 100 ns sia0 hold time (from scka0 ) t ksi4 2/f w + 100 note 1 ns 4.0 v v dd 5.5 v 2/f w + 100 note 1 ns 2.7 v v dd < 4.0 v 2/f w + 200 note 1 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 2 1.8 v v dd < 2.7 v 2/f w + 300 note 1 ns scka0 rise/fall time t r4 , t f4 1000 ns notes 1. f w is the csia0 base clock selected by the csis0 register. 2. c is the load capacitance of the soa0 output line. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 822 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (1/2) iic0: t low t high t hd:sta t su:dat t su:sta t hd:sta t hd:dat scl0 sda0 t buf t su:sto stop condition start condition restart condition stop condition csi1n: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 823 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (2/2) csia0: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw csia0 (busy processing): t byh t sps t bys 789 note 10 note 10 + n note 1 scka0 busy0 (active-high) note scka0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 824 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. a/d converter characteristics (t a = ? 40 to +85 c, 2.3 v av ref v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 a inl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s 2.7 v av ref < 4.0 v 12.2 36.7 s conventional- specification products ( pd78f05xx(a)) 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 6.1 66.6 s 2.7 v av ref < 4.0 v 12.2 66.6 s conversion time t conv expanded- specification products ( pd78f05xxa(a)) 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr zero-scale error notes 1, 2 e zs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error notes 1, 2 e fs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 i le 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 d le 2.3 v av ref < 2.7 v 2.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 825 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. 1.59 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power supply voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s 1.59 v poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 826 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. supply voltage rise time (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) (v dd : 0 v 1.8 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) (releasing reset input v dd : 1.8 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 1.8 v t pup1 supply voltage (v dd ) time 1.8 v t pup2 v poc reset pin 2.7 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v remark the operations of the poc circuit are as described below, depending on the pocmode (option byte) setting. option byte setting poc mode operation pocmode = 0 1.59 v mode operation a reset state is retained until v poc = 1.59 v (typ.) is reached after the power is turned on, and the reset is released when v poc is exceeded. after that, poc detection is performed at v poc , similarly as when the power was turned on. the power supply voltage must be raised at a time of t pup1 or t pup2 when pocmode is 0. pocmode = 1 2.7 v/1.59 v mode operation a reset state is retained until v ddpoc = 2.7 v (typ.) is reached after the power is turned on, and the reset is released when v ddpoc is exceeded. after that, poc detection is performed at v poc = 1.59 v (typ.) and not at v ddpoc . the use of the 2.7 v/1.59 v poc mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 v, is more relaxed than t pth . 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 827 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 1.98 2.08 2.18 v supply voltage level v lvi15 1.83 1.93 2.03 v detection voltage external input pin note 1 exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 828 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detection voltage. when the voltage drops, t he data is retained until a poc reset is effected, but data is not retai ned when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 78k0/kx2 chapter 31 electrical specifications ((a) grade products) r01uh0008ej0401 rev.4.01 829 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. flash memory programming characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 11.0 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s ? when a flash memory programmer is used, and the libraries note 4 provided by renesas electronics are used ? for program update retention: 15 years 1000 times expanded- specification products ( pd78f05xxa (a)) ? when the eeprom emulation libraries note 5 provided by renesas electronics are used ? the rewritable rom size: 4 kb ? for data update retention: 5 years 10000 times expanded- specification products ( pd78f05xxa (a)) number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 conventional- specification products ( pd78f05xx (a)) conditions other than the above note 6 retention: 10 years 100 times notes 1. characteristic of the flash memory. for the characte ristic when a dedicated flash programmer, pg-fp4 or pg- fp5, is used and the rewrite ti me during self programming, see tables 27-12 to 27-14 . 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. 4. the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) is excluded. 5. the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) is excluded. 6. these include when the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) and the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) are used. remarks 1. f xp : main system clock oscillation frequency 2. for serial write operation characteristics, refer to 78k0/kx2 flash memory programming (programmer) application note ( document no.: u17739e) . 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 830 jul 15, 2010 chapter 32 electrical specifications ((a2) grade products: t a = ? 40 to +110 c) target products conventional-specificati on products expanded-specification products 78k0/kb2 pd78f0500(a2), 78f0501(a2), 78f0502(a2), 78f0503(a2) pd78f0500a(a2), 78f0501a(a2), 78f0502a(a2), 78f0503a(a2) 78k0/kc2 pd78f0511(a2), 78f0512(a2), 78f0513(a2), 78f0514(a2), 78f0515(a2) pd78f0511a(a2), 78f0512a(a2), 78f0513a(a2), 78f0514a(a2), 78f0515a(a2) 78k0/kd2 pd78f0521(a2), 78f0522(a2), 78f0523(a2), 78f0524(a2), 78f0525(a2), 78f0526(a2), 78f0527(a2) pd78f0521a(a2), 78f0522a(a2), 78f0523a(a2), 78f0524a(a2), 78f0525a(a2), 78f0526a(a2), 78f0527a(a2) 78k0/ke2 pd78f0531(a2), 78f0532(a2), 78f0533(a2), 78f0534(a2), 78f0535(a2), 78f0536(a2), 78f0537(a2) pd78f0531a(a2), 78f0532a(a2), 78f0533a(a2), 78f0534a(a2), 78f0535a(a2), 78f0536a(a2), 78f0537a(a2) 78k0/kf2 pd78f0544(a2), 78f0545(a2), 78f0546(a2), 78f0547(a2) pd78f0544a(a2), 78f0545a(a2), 78f0546a(a2), 78f0547a(a2) the following items are described separately for conventional-specification products ( pd78f05xx(a2)) and expanded- specification products ( pd78f05xxa(a2)). ? x1 clock oscillation frequency ( x1 oscillator characteristics ) ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and exter nal main system clock input low-level width ( (1) basic operation in ac characteristics ) ? a/d conversion time ( a/d converter characteristics ) ? number of rewrites per chip ( flash memory programming characteristics ) caution the pins mounted de pend on the product as follows. (1) port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins port 0 p00, p01 p00 to p03 p00 to p06 port 1 p10 to p17 port 2 p20 to p23 p20 to p25 p20 to p27 port 3 p30 to p33 port 4 ? p40, p41 p40 to p43 p40 to p47 port 5 ? p50 to p53 p50 to p57 port 6 p60, p61 p60 to p63 p60 to p67 port 7 ? p70, p71 p70 to p73 p70 to p75 p70 to p77 port 12 p120 to p122 p120 to p124 port 13 ? p130 port 14 ? p140 p140, p141 p140 to p145 (the remaining table is on the next page.) 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 831 jul 15, 2010 (2) non-port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins power supply, ground v dd , ev dd note 1 , v ss , ev ss note 1 , av ref , av ss v dd , av ref , v ss , av ss v dd , ev dd , v ss , ev ss , av ref , av ss regulator regc reset reset clock oscillation x1, x2, exclk x1, x2, xt1, xt2, exclk, exclks writing to flash memory flmd0 interrupt intp0 to intp5 intp0 to intp6 intp0 to intp7 key interrupt ? kr0, kr1 kr0 to kr3 kr0 to kr7 tm00 ti000, ti010, to00 tm01 ? ti001 note 2 , ti011 note 2 , to01 note 2 tm50 ti50, to50 tm51 ti51, to51 tmh0 toh0 timer tmh1 toh1 uart0 rxd0, txd0 uart6 rxd6, txd6 iic0 scl0, sda0 scl0, sda0, exscl0 csi10 sck10, si10, so10 csi11 ? sck11 note 2 , si11 note 2 , so11 note 2 , ssi11 note 2 serial interface csia0 ? scka0, sia0, soa0, busy0, stb0 a/d converter ani0 to ani3 ani0 to ani5 ani0 to ani7 clock output ? pcl buzzer output ? buz low-voltage detector (lvi) exlvi notes 1. this is not mounted onto 30-pin products. 2. this is not mounted onto the 78k0/ke2 prod ucts whose flash memory is less than 32 kb. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 832 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc ? 0.5 to +3.6 and ? 0.5 to v dd v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120 to p124, p140 to p145, x1, x2, xt1, xt2, reset, flmd0 ? 0.3 to v dd + 0.3 note v input voltage v i2 p60 to p63 (n-ch open drain) ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ani0 to ani7 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even mome ntarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under condit ions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 833 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 ? 10 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 ? 25 ma total of all pins ? 80 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 ? 55 ma per pin ? 0.5 ma total of all pins p20 to p27 ? 2 ma per pin ? 1 ma output current, high i oh total of all pins p121 to p124 ? 4 ma per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p130, p140 to p145 30 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 60 ma total of all pins 200 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 140 ma per pin 1 ma total of all pins p20 to p27 5 ma per pin 4 ma output current, low i ol total of all pins p121 to p124 10 ma operating ambient temperature t a ? 40 to +110 c storage temperature t stg ? 65 to +150 c cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolu te maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. 2. the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 834 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. x1 oscillator characteristics (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 note 2 20.0 conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 1.0 note 2 10.0 mhz ceramic resonator, crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1 expanded-specification products ( pd78f05xxa(a2)) 1.0 note 2 20.0 mhz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. it is 2.0 mhz (min.) when programming on the board via uart6. cautions 1. when using the x1 oscillator, wire as follow s in the area enclosed by th e broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by th e internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the o scillation stabilization time counter status register (ostc) by the user. determine th e oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficientl y evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 835 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. internal oscillator characteristics (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit rsts = 1 7.6 8.0 8.4 mhz 8 mhz internal oscillator in ternal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 216 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) xt1 oscillator characteristics note 1 (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 2 32 32.768 35 khz notes 1. the 78k0/kb2 is not provi ded with the xt1 oscillator. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscilla tor, wire as follows in the area enclo sed by the broken lines in the above figure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is design ed as a low-amplitude circuit for re ducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular ca re is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 836 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (1/4) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 2.5 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v ? 2.0 ma 4.0 v v dd 5.5 v ? 7.5 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 2.7 v v dd < 4.0 v ? 6.0 ma 4.0 v v dd 5.5 v ? 12.5 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 note 3 2.7 v v dd < 4.0 v ? 10.0 ma 4.0 v v dd 5.5 v ? 16.0 ma i oh1 total of all the pins above note 3 2.7 v v dd < 4.0 v ? 14.0 ma per pin for p20 to p27 av ref = v dd ? 0.1 ma output current, high note 1 i oh2 per pin for p121 to p124 ? 0.1 ma 4.0 v v dd 5.5 v 5.0 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v 3.0 ma 4.0 v v dd 5.5 v 10.0 ma per pin for p60 to p63 2.7 v v dd < 4.0 v 3.0 ma 4.0 v v dd 5.5 v 13.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 2.7 v v dd < 4.0 v 10.0 ma 4.0 v v dd 5.5 v 25.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 note 3 2.7 v v dd < 4.0 v 20.0 ma 4.0 v v dd 5.5 v 38.0 ma i ol1 total of all the pins above note 3 2.7 v v dd < 4.0 v 30.0 ma per pin for p20 to p27 av ref = v dd 0.4 ma output current, low note 2 i ol2 per pin for p121 to p124 0.4 ma notes 1. value of current at which the device operatio n is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the device operation is guarant eed even if the current flows from an output pin to gnd. 3. specification under conditions w here the duty factor is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be ca lculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 837 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (2/4) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p121 to p124, p144, p145 0.7v dd v dd v v ih2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is at least 48 kb) note 1 v ih4 p60 to p63 0.7v dd 6.0 v v ih1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is less than 32 kb) note 2 v ih4 p60 to p63 0.7v dd 6.0 v v il1 p02, p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p121 to p124, p144, p145 0 0.3v dd v v il2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is at least 48 kb) note 1 v il3 p20 to p27 av ref = v dd 0 0.3av ref v v il1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p60 to p63, p121 to p124 0 0.3v dd v v il2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is less than 32 kb) note 2 v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 2.5 ma v dd ? 0.7 v v oh1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v, i oh1 = ? 2.0 ma v dd ? 0.5 v p20 to p27 av ref = v dd , i oh2 = ? 100 a v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i oh2 = ? 100 a v dd ? 0.5 v notes 1. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is at least 48 kb, and 78k0/kf2 2. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is less than 32 kb, 78k0/kb2, and 78k0/kc2 remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 838 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (3/4) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.7 v v ol1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v, i ol1 = 3.0 ma 0.7 v p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v v ol2 p121 to p124 i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 10.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 2.7 v v dd < 4.0 v, i ol1 =3.0 ma 0.6 v i lih1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v dd 3 a i lih2 p20 to p27 v i = av ref = v dd 3 a i/o port mode 3 a input leakage current, high i lih3 p121 to 124 (x1, x2, xt1, xt2) v i = v dd osc mode 20 a i lil1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v ss ? 3 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 3 a i/o port mode ? 3 a input leakage current, low i lil3 p121 to 124 (x1, x2, xt1, xt2) v i = v ss osc mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 839 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (4/4) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.2 7.2 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 4.5 9.0 ma square wave input 1.6 3.7 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 2.3 5.1 ma square wave input 1.5 3.6 ma f xh = 10 mhz v dd = 3.0 v notes 2, 3 resonator connection 2.2 4.2 ma square wave input 0.9 2.1 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 1.3 2.6 ma f rh = 8 mhz, v dd = 5.0 v note 4 1.4 3.3 ma square wave input 6 93 a i dd1 operating mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 15 100 a square wave input 0.8 3.4 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 2.0 5.8 ma square wave input 0.4 1.7 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 1.0 3.2 ma square wave input 0.2 0.85 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.5 1.5 ma f rh = 8 mhz, v dd = 5.0 v note 4 0.4 1.6 ma square wave input 3.0 89 a i dd2 halt mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 12 93 a stop mode 1 60 a supply current note 1 i dd3 note 6 t a = ? 40 to +70 c 1 10 a a/d converter operating current i adc note 7 2.7 v av ref v dd , adcs = 1 0.86 2.5 ma watchdog timer operating current i wdt note 8 during 240 khz internal low-speed oscillation clock operation 5 13 a lvi operating current i lvi note 9 9 24 a remarks 1. f xh : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency or external subsystem clock frequency) (notes on next page) 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 840 jul 15, 2010 notes 1. total current flowing into the internal power supply (v dd, ev dd ), including the periphe ral operation current and the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the out put current of the port are not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, 240 khz internal oscillator, and xt1 oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillat or, xt1 oscillator, and 240 khz internal oscillator, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 5. not including the operating current of the x1 osc illation, 8 mhz internal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 7. current flowing only to the a/d converter (av ref ). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 8. current flowing only to the watchdog timer (including the operating current of the 240 khz internal oscillator). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 9. current flowing only to the lvi circuit. the current value of the 78k0/kx2 microc ontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 841 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac characteristics (1) basic operation (1/2) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 0.2 32 s main system clock (f xp ) operation expanded- specification products ( pd78f05xxa (a2)) 2.7 v v dd 5.5 v 0.1 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 1 114 122 125 s 4.0 v v dd 5.5 v 20 mhz conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 10 mhz 4.0 v v dd 5.5 v 20 mhz f prs = f xh (xsel = 1) expanded- specification products ( pd78f05xxa (a2)) 2.7 v v dd < 4.0 v note 2 20 mhz peripheral hardware clock frequency f prs f prs = f rh (xsel = 0) 2.7 v v dd 5.5 v 7.6 8.4 mhz 4.0 v v dd 5.5 v 1.0 note 3 20.0 mhz conventional-specification products ( pd78f05xx(a2)) 2.7 v v dd < 4.0 v 1.0 note 3 10.0 mhz external main system clock frequency f exclk expanded-specification products ( pd78f05xxa(a2)) 2.7 v v dd 5.5 v 1.0 note 3 20.0 mhz 4.0 v v dd 5.5 v 24 ns conventional-specification products ( pd78f05xx(a2)) 2.7 v v dd < 4.0 v 48 ns external main system clock input high-level width, low-level width t exclkh , t exclkl expanded-specification products ( pd78f05xxa(a2)) 2.7 v v dd 5.5 v 24 ns notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f xh /2 (10 mhz) or less. the multiplier /divider, however, can operate on f xh (20 mhz). 3. 2.0 mhz (min.) when using uart6 during on-board programming. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 842 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (1) basic operation (2/2) (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit external subsystem clock frequency note 1 f exclks 32 32.768 35 khz external subsystem clock input high-level width, low-level width note 1 t exclksh , t exclksl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti000, ti010, ti001, ti011 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 2 s ti50, ti51 input frequency f ti5 10 mhz ti50, ti51 input high-level width, low-level width t tih5 , t til5 50 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. selection of f sam = f prs , f prs /4, f prs /256, or f prs , f prs /16, f prs /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode regi sters 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f prs. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 843 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. t cy vs. v dd (main system clock operation) <1> conventional-specification products ( pd78f05xx(a2)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) <2> expanded-specification products ( pd78f05xxa(a2)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 844 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac timing test points v ih v il test points v ih v il external main system clock timing , external subsystem clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f exclk t exclkl t exclkh 1/f exclks t exclksl t exclksh exclks 0.8v dd (min.) 0.2v dd (max.) 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 845 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ti timing ti000, ti010, ti001, ti011 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 846 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (2) serial interface (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (c) iic0 standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of restart condition t su: sta 4.7 ? 0.6 ? s hold time note 1 t hd: sta 4.0 ? 0.6 ? s internal clock operation 4.7 ? 1.3 ? s hold time when scl0 = ?l? t low exscl0 clock (6.4 mhz) operation 4.7 ? 1.25 ? s hold time when scl0 = ?h? t high 4.0 ? 0.6 ? s data setup time (reception) t su: dat 250 ? 100 ? ns 0.9 note 4 f w = f xh /2 n or f w = f exscl0 selected note 3 0 3.45 0 1.00 note 5 s data hold time (transmission) note 2 t hd: dat f w = f rh /2 n selected note 3 0 3.45 0 1.05 s setup time of stop condition t su: sto 4.0 ? 0.6 ? s bus free time t buf 4.7 ? 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. f w indicates the iic0 transfer clock selected by the ii ccl and iicx0 registers. 4. when f w 4.4 mhz is selected 5. when f w < 4.4 mhz is selected 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 847 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (d) csi1n (master mode, sck1n? internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns sck1n cycle time t kcy1 2.7 v v dd < 4.0 v 400 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 note 1 ns sck1n high-/low-level width t kh1 , t kl1 2.7 v v dd < 4.0 v t kcy1 /2 ? 30 note 1 ns 4.0 v v dd 5.5 v 70 ns si1n setup time (to sck1n ) t sik1 2.7 v v dd < 4.0 v 100 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck1n and so1n output lines. (e) csi1n (slave mode, sck1n? external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 120 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 848 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (f) csia0 (master mode, scka0?internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy3 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v t kcy3 /2 ? 50 ns scka0 high-/low-level width t kh3 , t kl3 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns sia0 setup time (to scka0 ) t sik3 100 ns sia0 hold time (from scka0 ) t ksi3 300 ns 4.0 v v dd 5.5 v 200 ns delay time from scka0 to soa0 output t kso3 c = 100 pf note 2.7 v v dd < 4.0 v 300 ns time from scka0 to stb0 t sbd t kcy3 /2 ? 100 ns 4.0 v v dd 5.5 v t kcy3 ? 30 ns strobe signal high-level width t sbw 2.7 v v dd < 4.0 v t kcy3 ? 60 ns busy signal setup time (to busy signal detection timing) t bys 100 ns busy signal hold time (from busy signal detection timing) t byh 100 ns 4.0 v v dd 5.5 v 2t kcy3 + 100 ns time from busy inactive to scka0 t sps 2.7 v v dd < 4.0 v 2t kcy3 ? 150 ns note c is the load capacitance of the scka0 and soa0 output lines. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 849 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (g) csia0 (slave mode, scka0?external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy4 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v 300 ns scka0 high-/low-level width t kh4 , t kl4 2.7 v v dd < 4.0 v 600 ns sia0 setup time (to scka0 ) t sik4 100 ns sia0 hold time (from scka0 ) t ksi4 2/f w + 100 note 1 ns 4.0 v v dd 5.5 v 2/f w + 100 note 1 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 2 2.7 v v dd < 4.0 v 2/f w + 200 note 1 ns scka0 rise/fall time t r4 , t f4 1000 ns notes 1. f w is the csia0 base clock selected by the csis0 register. 2. c is the load capacitance of the soa0 output line. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 850 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (1/2) iic0: t low t high t hd:sta t su:dat t su:sta t hd:sta t hd:dat scl0 sda0 t buf t su:sto stop condition start condition restart condition stop condition csi1n: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 851 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (2/2) csia0: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw csia0 (busy processing): t byh t sps t bys 789 note 10 note 10 + n note 1 scka0 busy0 (active-high) note scka0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 852 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. a/d converter characteristics (t a = ? 40 to +110 c, 2.7 v av ref v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr overall error notes 1, 2 a inl 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s conventional- specification products ( pd78f05xx(a2)) 2.7 v av ref < 4.0 v 12.2 36.7 s 4.0 v av ref 5.5 v 6.1 66.6 s conversion time t conv expanded- specification products ( pd78f05xxa (a2)) 2.7 v av ref < 4.0 v 12.2 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 e zs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 e fs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 i le 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 d le 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 853 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. 1.59 v poc circuit characteristics (t a = ? 40 to +110 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power supply voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s 1.59 v poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 854 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. supply voltage rise time (t a = ? 40 to +110 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 2.7 v (v dd (min.)) (v dd : 0 v 2.7 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 2.7 v (v dd (min.)) (releasing reset input v dd : 2.7 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 2.7 v t pup1 supply voltage (v dd ) time 2.7 v t pup2 v poc reset pin 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 855 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. 2.7 v poc circuit characteristics (t a = ? 40 to +110 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v remark the operations of the poc circuit are as described below, depending on the pocmode (option byte) setting. option byte setting poc mode operation pocmode = 0 1.59 v mode operation a reset state is retained until v poc = 1.59 v (typ.) is reached after the power is turned on, and the reset is released when v poc is exceeded. after that, poc detection is performed at v poc , similarly as when the power was turned on. the power supply voltage must be raised at a time of t pup1 or t pup2 when pocmode is 0. pocmode = 1 2.7 v/1.59 v mode operation a reset state is retained until v ddpoc = 2.7 v (typ.) is reached after the power is turned on, and the reset is released when v ddpoc is exceeded. after that, poc detection is performed at v poc = 1.59 v (typ.) and not at v ddpoc . the use of the 2.7 v/1.59 v poc mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 v, is more relaxed than t pth . 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 856 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. lvi circuit characteristics (t a = ? 40 to +110 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v supply voltage level v lvi9 2.75 2.85 2.95 v detection voltage external input pin note 1 exlvi exlvi < v dd , 2.7 v v dd 5.5 v 1.11 1.21 1.31 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 9 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 857 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +110 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detection voltage. when the voltage drops, t he data is retained until a poc reset is effected, but data is not retai ned when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 78k0/kx2 chapter 32 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 858 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. flash memory programming characteristics (t a = ? 40 to +110 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 14.0 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s ? when a flash memory programmer is used, and the libraries note 4 provided by renesas electronics are used ? for program update retention: 15 years 1000 times expanded- specification products ( pd78f05xxa (a2)) ? when the eeprom emulation libraries note 5 provided by renesas electronics are used ? the rewritable rom size: 4 kb ? for data update retention: 5 years 10000 times expanded- specification products ( pd78f05xxa (a2)) number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 conventional- specification products ( pd78f05xx (a2)) conditions other than the above note 6 retention: 10 years 100 times notes 1. characteristic of the flash memory. for the characte ristic when a dedicated flash programmer, pg-fp4 or pg- fp5, is used and the rewrite ti me during self programming, see tables 27-12 to 27-14 . 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. 4. the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) is excluded. 5. the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) is excluded. 6. these include when the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) and the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) are used. remarks 1. f xp : main system clock oscillation frequency 2. for serial write operation characteristics, refer to 78k0/kx2 flash memory programming (programmer) application note ( document no.: u17739e) . 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 859 jul 15, 2010 chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c) target products conventional-specificati on products expanded-specification products 78k0/kb2 pd78f0500(a2), 78f0501(a2), 78f0502(a2), 78f0503(a2) pd78f0500a(a2), 78f0501a(a2), 78f0502a(a2), 78f0503a(a2) 78k0/kc2 pd78f0511(a2), 78f0512(a2), 78f0513(a2), 78f0514(a2), 78f0515(a2) pd78f0511a(a2), 78f0512a(a2), 78f0513a(a2), 78f0514a(a2), 78f0515a(a2) 78k0/kd2 pd78f0521(a2), 78f0522(a2), 78f0523(a2), 78f0524(a2), 78f0525(a2), 78f0526(a2), 78f0527(a2) pd78f0521a(a2), 78f0522a(a2), 78f0523a(a2), 78f0524a(a2), 78f0525a(a2), 78f0526a(a2), 78f0527a(a2) 78k0/ke2 pd78f0531(a2), 78f0532(a2), 78f0533(a2), 78f0534(a2), 78f0535(a2), 78f0536(a2), 78f0537(a2) pd78f0531a(a2), 78f0532a(a2), 78f0533a(a2), 78f0534a(a2), 78f0535a(a2), 78f0536a(a2), 78f0537a(a2) 78k0/kf2 pd78f0544(a2), 78f0545(a2), 78f0546(a2), 78f0547(a2) pd78f0544a(a2), 78f0545a(a2), 78f0546a(a2), 78f0547a(a2) the following items are described separately for conventional-specification products ( pd78f05xx(a2)) and expanded- specification products ( pd78f05xxa(a2)). ? x1 clock oscillation frequency ( x1 oscillator characteristics ) ? instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and exter nal main system clock input low-level width ( (1) basic operation in ac characteristics ) ? a/d conversion time ( a/d converter characteristics ) ? number of rewrites per chip ( flash memory programming characteristics ) caution the pins mounted de pend on the product as follows. (1) port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins port 0 p00, p01 p00 to p03 p00 to p06 port 1 p10 to p17 port 2 p20 to p23 p20 to p25 p20 to p27 port 3 p30 to p33 port 4 ? p40, p41 p40 to p43 p40 to p47 port 5 ? p50 to p53 p50 to p57 port 6 p60, p61 p60 to p63 p60 to p67 port 7 ? p70, p71 p70 to p73 p70 to p75 p70 to p77 port 12 p120 to p122 p120 to p124 port 13 ? p130 port 14 ? p140 p140, p141 p140 to p145 (the remaining table is on the next page.) 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 860 jul 15, 2010 (2) non-port functions 78k0/kb2 78k0/kc2 78k0/kd2 78k0/ke2 78k0/kf2 port 30/36 pins 38 pins 44 pins 48 pi ns 52 pins 64 pins 80 pins power supply, ground v dd , ev dd note 1 , v ss , ev ss note 1 , av ref , av ss v dd , av ref , v ss , av ss v dd , ev dd , v ss , ev ss , av ref , av ss regulator regc reset reset clock oscillation x1, x2, exclk x1, x2, xt1, xt2, exclk, exclks writing to flash memory flmd0 interrupt intp0 to intp5 intp0 to intp6 intp0 to intp7 key interrupt ? kr0, kr1 kr0 to kr3 kr0 to kr7 tm00 ti000, ti010, to00 tm01 ? ti001 note 2 , ti011 note 2 , to01 note 2 tm50 ti50, to50 tm51 ti51, to51 tmh0 toh0 timer tmh1 toh1 uart0 rxd0, txd0 uart6 rxd6, txd6 iic0 scl0, sda0 scl0, sda0, exscl0 csi10 sck10, si10, so10 csi11 ? sck11 note 2 , si11 note 2 , so11 note 2 , ssi11 note 2 serial interface csia0 ? scka0, sia0, soa0, busy0, stb0 a/d converter ani0 to ani3 ani0 to ani5 ani0 to ani7 clock output ? pcl buzzer output ? buz low-voltage detector (lvi) exlvi notes 1. this is not mounted onto 30-pin products. 2. this is not mounted onto the 78k0/ke2 prod ucts whose flash memory is less than 32 kb. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 861 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc ? 0.5 to +3.6 and ? 0.5 to v dd v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120 to p124, p140 to p145, x1, x2, xt1, xt2, reset, flmd0 ? 0.3 to v dd + 0.3 note v input voltage v i2 p60 to p63 (n-ch open drain) ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ani0 to ani7 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even mome ntarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under condit ions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 862 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 ? 10 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 ? 25 ma total of all pins ? 80 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 ? 55 ma per pin ? 0.5 ma total of all pins p20 to p27 ? 2 ma per pin ? 1 ma output current, high i oh total of all pins p121 to p124 ? 4 ma per pin p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p130, p140 to p145 30 ma p00 to p04, p40 to p47, p120, p130, p140 to p145 60 ma total of all pins 200 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 140 ma per pin 1 ma total of all pins p20 to p27 5 ma per pin 4 ma output current, low i ol total of all pins p121 to p124 10 ma operating ambient temperature t a ? 40 to +125 c storage temperature t stg ? 65 to +150 c cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolu te maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. 2. the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 863 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. x1 oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 1.0 note 2 20.0 conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 1.0 note 2 10.0 mhz ceramic resonator, crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1 expanded-specification products ( pd78f05xxa(a2)) 1.0 note 2 20.0 mhz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. it is 2.0 mhz (min.) when programming on the board via uart6. cautions 1. when using the x1 oscillator, wire as follow s in the area enclosed by th e broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by th e internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the o scillation stabilization time counter status register (ostc) by the user. determine th e oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficientl y evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 864 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. internal oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit rsts = 1 7.6 8.0 8.46 mhz 8 mhz internal oscillator in ternal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 216 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) xt1 oscillator characteristics note 1 (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 2 32 32.768 35 khz notes 1. the 78k0/kb2 is not provi ded with the xt1 oscillator. 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscilla tor, wire as follows in the area enclo sed by the broken lines in the above figure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is design ed as a low-amplitude circuit for re ducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular ca re is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator constant, cu stomers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 865 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (1/4) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 1.5 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v ? 1.0 ma 4.0 v v dd 5.5 v ? 6.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 2.7 v v dd < 4.0 v ? 4.0 ma 4.0 v v dd 5.5 v ? 10.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p77 note 3 2.7 v v dd < 4.0 v ? 8.0 ma 4.0 v v dd 5.5 v ? 14.0 ma i oh1 total of all the pins above note 3 2.7 v v dd < 4.0 v ? 12.0 ma per pin for p20 to p27 av ref = v dd ? 0.1 ma output current, high note 1 i oh2 per pin for p121 to p124 ? 0.1 ma 4.0 v v dd 5.5 v 4.0 ma per pin for p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v 2.0 ma 4.0 v v dd 5.5 v 8.0 ma per pin for p60 to p63 2.7 v v dd < 4.0 v 2.0 ma 4.0 v v dd 5.5 v 10.0 ma total of p00 to p04, p40 to p47, p120, p130, p140 to p145 note 3 2.7 v v dd < 4.0 v 8.0 ma 4.0 v v dd 5.5 v 20.0 ma total of p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p77 note 3 2.7 v v dd < 4.0 v 16.0 ma 4.0 v v dd 5.5 v 30.0 ma i ol1 total of all the pins above note 3 2.7 v v dd < 4.0 v 24.0 ma per pin for p20 to p27 av ref = v dd 0.4 ma output current, low note 2 i ol2 per pin for p121 to p124 0.4 ma notes 1. value of current at which the device operatio n is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the device operation is guarant eed even if the current flows from an output pin to gnd. 3. specification under conditions w here the duty factor is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be ca lculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 866 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (2/4) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p121 to p124, p144, p145 0.7v dd v dd v v ih2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is at least 48 kb) note 1 v ih4 p60 to p63 0.7v dd 6.0 v v ih1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0.8v dd v dd v v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v input voltage, high (products whose flash memory is less than 32 kb) note 2 v ih4 p60 to p63 0.7v dd 6.0 v v il1 p02, p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p121 to p124, p144, p145 0 0.3v dd v v il2 p00, p01, p03 to p06, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140 to p143, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is at least 48 kb) note 1 v il3 p20 to p27 av ref = v dd 0 0.3av ref v v il1 p02 to p06, p12, p13, p15, p40 to p43, p50 to p53, p60 to p63, p121 to p124 0 0.3v dd v v il2 p00, p01, p10, p11, p14, p16, p17, p30 to p33, p70 to p77, p120, p140, p141, exclk, exclks, reset 0 0.2v dd v input voltage, low (products whose flash memory is less than 32 kb) note 2 v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 1.5 ma v dd ? 0.7 v v oh1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v, i oh1 = ? 1.0 ma v dd ? 0.5 v p20 to p27 av ref = v dd , i oh2 = ? 100 a v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i oh2 = ? 100 a v dd ? 0.5 v notes 1. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is at least 48 kb, and 78k0/kf2 2. supported products: 78k0/kd2 and 78k0/ke2 whose flash memory is less than 32 kb, 78k0/kb2, and 78k0/kc2 remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 867 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (3/4) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 4.0 ma 0.7 v v ol1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, p130, p140 to p145 2.7 v v dd < 4.0 v, i ol1 = 2.0 ma 0.7 v p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v v ol2 p121 to p124 i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 8.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 2.0 ma 0.6 v output voltage, low v ol3 p60 to p63 2.7 v v dd < 4.0 v, i ol1 = 2.0 ma 0.6 v i lih1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v dd 5 a i lih2 p20 to p27 v i = av ref = v dd 5 a i/o port mode 5 a input leakage current, high i lih3 p121 to 124 (x1, x2, xt1, xt2) v i = v dd osc mode 20 a i lil1 p00 to p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120, p140 to p145, flmd0, reset v i = v ss ? 5 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 5 a i/o port mode ? 5 a input leakage current, low i lil3 p121 to 124 (x1, x2, xt1, xt2) v i = v ss osc mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 868 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. dc characteristics (4/4) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.2 8.3 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 4.5 10.5 ma square wave input 1.6 4.2 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 2.3 5.9 ma square wave input 1.5 4.1 ma f xh = 10 mhz v dd = 3.0 v notes 2, 3 resonator connection 2.2 4.8 ma square wave input 0.9 2.4 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 1.3 3.0 ma f rh = 8 mhz, v dd = 5.0 v note 4 1.4 3.8 ma square wave input 6 138 a i dd1 operating mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 15 145 a square wave input 0.8 3.9 ma f xh = 20 mhz, v dd = 5.0 v note 2 resonator connection 2.0 6.6 ma square wave input 0.4 2.0 ma f xh = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 1.0 3.6 ma square wave input 0.2 1.0 ma f xh = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.5 1.7 ma f rh = 8 mhz, v dd = 5.0 v note 4 0.4 1.8 ma square wave input 3.0 133 a i dd2 halt mode f sub = 32.768 khz, v dd = 5.0 v note 5 resonator connection 12 138 a stop mode 1 100 a supply current note 1 i dd3 note 6 t a = ? 40 to +70 c 1 10 a a/d converter operating current i adc note 7 2.7 v av ref v dd , adcs = 1 0.86 2.9 ma watchdog timer operating current i wdt note 8 during 240 khz internal low-speed oscillation clock operation 5 15 a lvi operating current i lvi note 9 9 27 a remarks 1. f xh : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency or external subsystem clock frequency) (notes on next page) 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 869 jul 15, 2010 notes 1. total current flowing into the internal power supply (v dd, ev dd ), including the periphe ral operation current and the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the out put current of the port are not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, 240 khz internal oscillator, and xt1 oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillat or, xt1 oscillator, and 240 khz internal oscillator, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 5. not including the operating current of the x1 osc illation, 8 mhz internal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. 7. current flowing only to the a/d converter (av ref ). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 8. current flowing only to the watchdog timer (including the operating current of the 240 khz internal oscillator). the current value of the 78k0/kx2 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 9. current flowing only to the lvi circuit. the current value of the 78k0/kx2 microc ontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 870 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac characteristics (1) basic operation (1/2) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 32 s conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 0.2 32 s main system clock (f xp ) operation expanded- specification products ( pd78f05xxa (a2)) 2.7 v v dd 5.5 v 0.1 32 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation note 1 114 122 125 s 4.0 v v dd 5.5 v 20 mhz conventional- specification products ( pd78f05xx (a2)) 2.7 v v dd < 4.0 v 10 mhz 4.0 v v dd 5.5 v 20 mhz f prs = f xh (xsel = 1) expanded- specification products ( pd78f05xxa (a2)) 2.7 v v dd < 4.0 v note 2 20 mhz peripheral hardware clock frequency f prs f prs = f rh (xsel = 0) 2.7 v v dd 5.5 v 7.6 8.4 mhz 4.0 v v dd 5.5 v 1.0 note 3 20.0 mhz conventional-specification products ( pd78f05xx(a2)) 2.7 v v dd < 4.0 v 1.0 note 3 10.0 mhz external main system clock frequency f exclk expanded-specification products ( pd78f05xxa(a2)) 2.7 v v dd 5.5 v 1.0 note 3 20.0 mhz 4.0 v v dd 5.5 v 24 ns conventional-specification products ( pd78f05xx(a2)) 2.7 v v dd < 4.0 v 48 ns external main system clock input high-level width, low-level width t exclkh , t exclkl expanded-specification products ( pd78f05xxa(a2)) 2.7 v v dd 5.5 v 24 ns notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. characteristics of the main system clock frequency. set the division clock to be set by a peripheral function to f xh /2 (10 mhz) or less. the multiplier /divider, however, can operate on f xh (20 mhz). 3. 2.0 mhz (min.) when using uart6 during on-board programming. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 871 jul 15, 2010 caution the pins mounted de pend on the product. refer to caution 2 at the beginning of this chapter. (1) basic operation (2/2) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit external subsystem clock frequency note 1 f exclks 32 32.768 35 khz external subsystem clock input high-level width, low-level width note 1 t exclksh , t exclksl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti000, ti010, ti001, ti011 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 2 s ti50, ti51 input frequency f ti5 10 mhz ti50, ti51 input high-level width, low-level width t tih5 , t til5 50 ns interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. the 78k0/kb2 is not provi ded with a subsystem clock. 2. selection of f sam = f prs , f prs /4, f prs /256, or f prs , f prs /16, f prs /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode regi sters 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f prs. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 872 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. t cy vs. v dd (main system clock operation) <1> conventional-specification products ( pd78f05xx(a2)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) <2> expanded-specification products ( pd78f05xxa(a2)) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 32 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range (the gray portion is applicable only if amph = 1 is set.) 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 873 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ac timing test points v ih v il test points v ih v il external main system clock timing , external subsystem clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f exclk t exclkl t exclkh 1/f exclks t exclksl t exclksh exclks 0.8v dd (min.) 0.2v dd (max.) 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 874 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. ti timing ti000, ti010, ti001, ti011 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 875 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (2) serial interface (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (c) iic0 standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of restart condition t su: sta 4.7 ? 0.6 ? s hold time note 1 t hd: sta 4.0 ? 0.6 ? s internal clock operation 4.7 ? 1.3 ? s hold time when scl0 = ?l? t low exscl0 clock (6.4 mhz) operation 4.7 ? 1.25 ? s hold time when scl0 = ?h? t high 4.0 ? 0.6 ? s data setup time (reception) t su: dat 250 ? 100 ? ns 0.9 note 4 f w = f xh /2 n or f w = f exscl0 selected note 3 0 3.45 0 1.00 note 5 s data hold time (transmission) note 2 t hd: dat f w = f rh /2 n selected note 3 0 3.45 0 1.05 s setup time of stop condition t su: sto 4.0 ? 0.6 ? s bus free time t buf 4.7 ? 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. f w indicates the iic0 transfer clock selected by the ii ccl and iicx0 registers. 4. when f w 4.4 mhz is selected 5. when f w < 4.4 mhz is selected 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 876 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (d) csi1n (master mode, sck1n? internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns sck1n cycle time t kcy1 2.7 v v dd < 4.0 v 400 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 note 1 ns sck1n high-/low-level width t kh1 , t kl1 2.7 v v dd < 4.0 v t kcy1 /2 ? 30 note 1 ns 4.0 v v dd 5.5 v 70 ns si1n setup time (to sck1n ) t sik1 2.7 v v dd < 4.0 v 100 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck1n and so1n output lines. (e) csi1n (slave mode, sck1n? external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 120 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 877 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (f) csia0 (master mode, scka0?internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy3 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v t kcy3 /2 ? 50 ns scka0 high-/low-level width t kh3 , t kl3 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns sia0 setup time (to scka0 ) t sik3 100 ns sia0 hold time (from scka0 ) t ksi3 300 ns 4.0 v v dd 5.5 v 200 ns delay time from scka0 to soa0 output t kso3 c = 100 pf note 2.7 v v dd < 4.0 v 300 ns time from scka0 to stb0 t sbd t kcy3 /2 ? 100 ns 4.0 v v dd 5.5 v t kcy3 ? 30 ns strobe signal high-level width t sbw 2.7 v v dd < 4.0 v t kcy3 ? 60 ns busy signal setup time (to busy signal detection timing) t bys 100 ns busy signal hold time (from busy signal detection timing) t byh 100 ns 4.0 v v dd 5.5 v 2t kcy3 + 100 ns time from busy inactive to scka0 t sps 2.7 v v dd < 4.0 v 2t kcy3 ? 150 ns note c is the load capacitance of the scka0 and soa0 output lines. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 878 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. (g) csia0 (slave mode, scka0?external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns scka0 cycle time t kcy4 2.7 v v dd < 4.0 v 1200 ns 4.0 v v dd 5.5 v 300 ns scka0 high-/low-level width t kh4 , t kl4 2.7 v v dd < 4.0 v 600 ns sia0 setup time (to scka0 ) t sik4 100 ns sia0 hold time (from scka0 ) t ksi4 2/f w + 100 note 1 ns 4.0 v v dd 5.5 v 2/f w + 100 note 1 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 2 2.7 v v dd < 4.0 v 2/f w + 200 note 1 ns scka0 rise/fall time t r4 , t f4 1000 ns notes 1. f w is the csia0 base clock selected by the csis0 register. 2. c is the load capacitance of the soa0 output line. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 879 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (1/2) iic0: t low t high t hd:sta t su:dat t su:sta t hd:sta t hd:dat scl0 sda0 t buf t su:sto stop condition start condition restart condition stop condition csi1n: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 880 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. serial transfer timing (2/2) csia0: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw csia0 (busy processing): t byh t sps t bys 789 note 10 note 10 + n note 1 scka0 busy0 (active-high) note scka0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 881 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. a/d converter characteristics (t a = ? 40 to +125 c, 2.7 v av ref v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr overall error notes 1, 2 a inl 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s conventional- specification products ( pd78f05xx(a2)) 2.7 v av ref < 4.0 v 12.2 36.7 s 4.0 v av ref 5.5 v 6.1 66.6 s conversion time t conv expanded- specification products ( pd78f05xxa (a2)) 2.7 v av ref < 4.0 v 12.2 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 e zs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 e fs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 i le 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 d le 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 882 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. 1.59 v poc circuit characteristics (t a = ? 40 to +125 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power supply voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s 1.59 v poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 883 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. supply voltage rise time (t a = ? 40 to +125 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 2.7 v (v dd (min.)) (v dd : 0 v 2.7 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 2.7 v (v dd (min.)) (releasing reset input v dd : 2.7 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 2.7 v t pup1 supply voltage (v dd ) time 2.7 v t pup2 v poc reset pin 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 884 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. 2.7 v poc circuit characteristics (t a = ? 40 to +125 c, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v remark the operations of the poc circuit are as described below, depending on the pocmode (option byte) setting. option byte setting poc mode operation pocmode = 0 1.59 v mode operation a reset state is retained until v poc = 1.59 v (typ.) is reached after the power is turned on, and the reset is released when v poc is exceeded. after that, poc detection is performed at v poc , similarly as when the power was turned on. the power supply voltage must be raised at a time of t pup1 or t pup2 when pocmode is 0. pocmode = 1 2.7 v/1.59 v mode operation a reset state is retained until v ddpoc = 2.7 v (typ.) is reached after the power is turned on, and the reset is released when v ddpoc is exceeded. after that, poc detection is performed at v poc = 1.59 v (typ.) and not at v ddpoc . the use of the 2.7 v/1.59 v poc mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 v, is more relaxed than t pth . 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 885 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. lvi circuit characteristics (t a = ? 40 to +125 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v supply voltage level v lvi9 2.75 2.85 2.95 v detection voltage external input pin note 1 exlvi exlvi < v dd , 2.7 v v dd 5.5 v 1.11 1.21 1.31 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 9 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 886 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detection voltage. when the voltage drops, t he data is retained until a poc reset is effected, but data is not retai ned when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 78k0/kx2 chapter 33 electrical specifications (a 2) grade products r01uh0008ej0401 rev.4.01 887 jul 15, 2010 caution the pins mounted depend on the product. refer to cautio n at the beginning of this chapter. flash memory programming characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 16.0 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s ? when a flash memory programmer is used, and the libraries note 4 provided by renesas electronics are used ? for program update retention: 15 years 1000 times expanded- specification products ( pd78f05xxa (a2)) ? when the eeprom emulation libraries note 5 provided by renesas electronics are used ? the rewritable rom size: 4 kb ? for data update retention: 5 years 10000 times expanded- specification products ( pd78f05xxa (a2)) number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 conventional- specification products ( pd78f05xx (a2)) conditions other than the above note 6 retention: 10 years 100 times notes 1. characteristic of the flash memory. for the characte ristic when a dedicated flash programmer, pg-fp4 or pg- fp5, is used and the rewrite ti me during self programming, see tables 27-12 to 27-14 . 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. 4. the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) is excluded. 5. the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) is excluded. 6. these include when the sample library specified by the 78k0/kx2 flash memory self programming user?s manual (document no.: u17516e ) and the sample program specified by the 78k0/kx2 eeprom emulation application note (document no.: u17517e ) are used. remarks 1. f xp : main system clock oscillation frequency 2. for serial write operation characteristics, refer to 78k0/kx2 flash memory programming (programmer) application note ( document no.: u17739e) . 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 888 jul 15, 2010 chapter 34 package drawings 34.1 78k0/kb2 ? pd78f0500mc-5a4-a, 78f0501mc-5a 4-a, 78f0502mc-5a4-a, 78f0503m c-5a4-a, 78f0503dmc-5a4-a s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 889 jul 15, 2010 ? pd78f0500mc(a)-cab-ax, 78f0501mc(a)-cab-ax, 78f0502mc(a)-cab-ax, 78f0503mc(a)-cab-ax ? pd78f0500mc(a2)-cab-ax, 78f0501mc(a2)-cab-ax, 78f0502mc(a2)-cab-ax, 78f0503mc(a2)-cab-ax ? pd78f0500amc-cab-ax, 78f0501amc-cab-ax, 78f05 02amc-cab-ax, 78f0503amc-cab-ax, 78f0503damc- cab-ax ? pd78f0500amca-cab-g, 78f0501amca-cab-g, 78f0502amca-cab-g, 78f0503amca-cab-g ? pd78f0500amca2-cab-g, 78f0501amca2-cab-g, 78f0502amca2-cab-g, 78f0503amca2-cab-g 16 30 1 m s s v 30-pin plastic ssop (7.62mm (300)) detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p.) 0.10 0.05 1.30 0.10 1.20 8.10 0.20 6.10 0.10 1.00 0.20 0.50 0.13 0.10 0.22 + 0.10 ? 0.05 k 0.15 + 0.05 ? 0.01 p 3 + 5 ? 3 (unit:mm) p30mc-65-cab v w w a i f g e c n d m b k h j p u t l 9.70 0.10 t u v 0.25(t.p.) 0.60 0.15 0.25 max. w 0.15 max. 15 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 890 jul 15, 2010 ? pd78f0500fc-aa3-a, 78f0501fc-aa 3-a, 78f0502fc-aa3-a, 78f05 03fc-aa3-a, 78f0503dfc-aa3-a ? pd78f0500afc-aa3-a, 78f0501afc-aa3-a, 78f0502afc -aa3-a, 78f0503afc-aa3-a, 78f0503dafc-aa3-a item dimensions d e w e a b x y y1 zd ze 4.00 0.10 4.00 0.10 0.05 0.20 0.91 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.75 0.75 36-pin plastic flga (4x4) s y1 s a s y s x 32x b a b m e s wb zd ze index mark b c d a s wa d e 2.90 2.90 e 1 2 fedcba 3 4 5 6 p36fc-50-aa3-2 detail of c part b 0.34 0.05 0.55 0.70 0.05 0.55 0.05 0.70 0.05 0.55 0.05 0.75 0.75 0.55 0.55 r0.17 0.05 r0.17 0.05 r0.12 0.05 r0.12 0.05 r0.275 0.05 r0.35 0.05 0.75 0.55 0.05 0.70 0.05 0.55 0.75 0.55 0.05 0.70 0.05 detail of d part detail of e part (land pad) (aperture of solder resist) 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 891 jul 15, 2010 34.2 78k0/kc2 ? pd78f0511amc-gaa-ax, 78f0512amc-gaa-ax, 78f0513amc-gaa-ax, 78f0513damc-gaa-ax ? pd78f0511amca-gaa-g, 78f0512amca-gaa-g, 78f0513amca-gaa-g ? pd78f0511amca2-gaa-g, 78f0512amca2-gaa-g, 78f0513amca2-gaa-g 20 38 1 m s s v 38-pin plastic ssop (7.62mm (300)) detail of lead end note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p.) 0.125 0.075 2.00 max. 1.70 0.10 8.10 0.20 6.10 0.10 1.00 0.20 0.50 0.10 0.10 0.30 + 0.10 ? 0.05 k 0.15 + 0.10 ? 0.05 p 3 + 5 ? 3 (unit:mm) p38mc-65-gaa v w w a i f g e c n d m b k h j p u t l 12.30 0.10 t u v 0.25(t.p.) 0.60 0.15 0.25 max. w 0.15 max. 19 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 892 jul 15, 2010 ? pd78f0511gb-ues-a, 78f0512gb-ues-a, 78f0513gb-ues-a, 78f0513dgb-ues-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p44gb-80-ues-1 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 44-pin plastic lqfp(10x10) 0.37 + 0.08 ? 0.07 b 11 22 1 44 12 23 34 33 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 893 jul 15, 2010 ? pd78f0511gb(a)-gaf-ax, 78f0512gb(a)-gaf-ax, 78f0513gb(a)-gaf-ax ? pd78f0511gb(a2)-gaf-ax, 78f0512gb(a2)-gaf-ax, 78f0513gb(a2)-gaf-ax ? pd78f0511agb-gaf-ax, 78f0512agb-gaf-ax, 78f0513agb-gaf-ax, 78f0513dagb-gaf-ax ? pd78f0511agba-gaf-g, 78f0512ag ba-gaf-g, 78f0513agba-gaf-g ? pd78f0511agba2-gaf-g, 78f0512agb a2-gaf-g, 78f0513agba2-gaf-g s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p44gb-80-gaf 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 44-pin plastic lqfp (10x10) 0.35 + 0.08 ? 0.04 b 11 22 44 12 23 34 33 1 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 894 jul 15, 2010 ? pd78f0511ga-8eu-a, 78f0 512ga-8eu-a, 78f0513ga-8e u-a, 78f0514ga-8eu-a, 78f0515ga-8eu-a, 78f0515dga-8eu-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p48ga-50-8eu 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 48-pin plastic lqfp (fine pitch)(7x7) 0.22 0.05 b 12 24 1 48 13 25 37 36 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 895 jul 15, 2010 ? pd78f0511ga(a)-gam-ax, 78f0512g a(a)-gam-ax, 78f0513ga(a)-ga m-ax, 78f0514ga(a)-gam-ax, 78f0515ga(a)-gam-ax ? pd78f0511ga(a2)-gam-ax, 78f0512ga( a2)-gam-ax, 78f0513ga(a2)-ga m-ax, 78f0514ga(a2)-gam-ax, 78f0515ga(a2)-gam-ax ? pd78f0511aga-gam-ax, 78f0512aga-gam-ax, 78f 0513aga-gam-ax, 78f0514aga-gam-ax, 78f0515aga- gam-ax, 78f0515daga-gam-ax ? pd78f0511agaa-gam-g, 78f0512agaa-gam-g, 78f0 513agaa-gam-g, 78f0514agaa-gam-g, 78f0515agaa- gam-g ? pd78f0511agaa2-gam-g, 78f051 2agaa2-gam-g, 78f0513agaa2-gam-g, 78f0514agaa2-gam-g, 78f0515agaa2-gam-g 48-pin plastic lqfp (fine pitch) (7x7) s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p48ga-50-gam 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 12 24 1 48 13 25 37 36 + 0.07 ? 0.03 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 896 jul 15, 2010 34.3 78k0/kd2 ? pd78f0521gb-uet-a, 78f0522gb-ue t-a, 78f0523gb-uet-a, 78f0524g b-uet-a, 78f0525gb-uet-a, 78f0526gb-uet-a, 78f0527gb -uet-a, 78f0527dgb-uet-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.10 1.10 l lp l1 0.50 0.60 0.15 1.00 0.20 p52gb-65-uet-1 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 52-pin plastic lqfp(10x10) 0.32 + 0.08 ? 0.07 b 13 26 1 52 14 27 40 39 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 897 jul 15, 2010 ? pd78f0521gb(a)-gag-ax, 78f0522gb(a)-gag-ax, 78f0523gb(a )-gag-ax, 78f0524gb(a)-gag-ax, 78f0525gb(a)-gag-ax, 78f0526gb(a )-gag-ax, 78f0527gb(a)-gag-ax ? pd78f0521gb(a2)-gag-ax, 78f0522gb(a2)-gag-ax, 78f 0523gb(a2)-gag-ax, 78f0524gb(a2)-gag-ax, 78f0525gb( a2)-gag-ax, 78f0526gb(a2)-gag -ax, 78f0527gb(a2)-gag-ax ? pd78f0521agb-gag-ax, 78f0522agb-gag-ax, 78f0523agb-gag-ax, 78f0524a gb-gag-ax, 78f0525agb- gag-ax, 78f0526agb-gag-ax, 78f0527ag b-gag-ax, 78f0527dagb-gag-ax ? pd78f0521agba-gag-g, 78f0522agba-gag-g, 78f0523agba-gag-g, 78f0524agba-gag-g, 78f0525agba-gag-g, 78f0526agba-gag-g, 78f0527agba-gag-g ? pd78f0521agba2-gag-g, 78f0522agba2-gag-g, 78f0523agba2-g ag-g, 78f0524agba2-gag-g, 78f0525agba2-gag-g, 78f0526ag ba2-gag-g, 78f0527agba2-gag-g s y e s x b m l c lp hd he zd ze a1 a2 a d e a3 s 0.125 + 0.08 ? 0.04 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.10 1.10 l lp l1 0.50 0.60 0.15 1.00 0.20 p52gb-65-gag 3 + 5 ? 3 note each lead centerline is located within 0.13mm of its true position at maximum material condition. detail of lead end 52-pin plastic lqfp (10x10) 0.30 b 13 26 1 52 14 27 39 40 l1 + 0.075 ? 0.025 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 898 jul 15, 2010 34.4 78k0/ke2 ? pd78f0531gb-ueu-a, 78f0532gb- ueu-a, 78f0533gb-ueu-a, 78f0 534gb-ueu-a, 78f0535gb-ueu-a, 78f0536gb-ueu-a, 78f0537gb- ueu-a, 78f0537dgb-ueu-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.55 ? 0.45 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-ueu 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 899 jul 15, 2010 ? pd78f0531gb(a)-gah-ax, 78f0532g b(a)-gah-ax, 78f0533gb(a)-gah -ax, 78f0534gb(a)-gah-ax, 78f0535gb(a)-gah-ax, 78f0536gb(a )-gah-ax, 78f0537gb(a)-gah-ax ? pd78f0531gb(a2)-gah-ax, 78f0532gb( a2)-gah-ax, 78f0533gb(a2)-gah -ax, 78f0534gb(a2)-gah-ax, 78f0535gb(a2)-gah-ax, 78f0536gb( a2)-gah-ax, 78f0537gb(a2)-gah-ax ? pd78f0531agb-gah-ax, 78f0532agb-gah-ax, 78f 0533agb-gah-ax, 78f0534agb-gah-ax, 78f0535agb- gah-ax, 78f0536agb-gah-ax, 78f0537 agb-gah-ax, 78f0537dagb-gah-ax ? pd78f0531agba-gah-g, 78f0532agba-gah-g, 78f0533a gba-gah-g, 78f0534agba-gah-g, 78f0535agba- gah-g, 78f0536agba-gah-g, 78f0537agba-gah-g ? pd78f0531agba2-gah-g, 78f053 2agba2-gah-g, 78f0533agba2-gah-g, 78f0534agba2-gah-g, 78f0535agba2-gah-g, 78f0536agba2 -gah-g, 78f0537agba2-gah-g s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-gah 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) + 0.07 ? 0.03 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 900 jul 15, 2010 ? pd78f0531gc-ubs-a, 78f0532gc-u bs-a, 78f0533gc-ubs-a, 78f0534g c-ubs-a, 78f0535gc-ubs-a, 78f0536gc-ubs-a, 78f0537gc- ubs-a, 78f0537dgc-ubs-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.17 + 0.03 ? 0.06 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.80 0.886 0.15 1.60 0.20 p64gc-80-ubs 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 64-pin plastic lqfp(14x14) 0.37 + 0.08 ? 0.07 b 16 32 64 17 33 49 48 1 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 901 jul 15, 2010 ? pd78f0531gc(a)-gal-ax, 78f0532g c(a)-gal-ax, 78f0533gc(a)-gal -ax, 78f0534gc(a)-gal-ax, 78f0535gc(a)-gal-ax, 78f0536gc(a)-gal-ax, 78f0537gc(a)-gal-ax ? pd78f0531gc(a2)-gal-ax, 78f0532gc( a2)-gal-ax, 78f0533gc(a2)-ga l-ax, 78f0534gc(a2)-gal-ax, 78f0535gc(a2)-gal-ax, 78f0536gc(a2)-gal-ax, 78f0537gc(a2)-gal-ax ? pd78f0531agc-gal-ax, 78f0532agc-gal-ax, 78f0533agc-gal-ax, 78f0534agc-gal-ax, 78f0535agc-gal-ax, 78f0536agc-gal-ax, 78f0537agc-gal-ax, 78f0537dagc-gal-ax ? pd78f0531agca-gal-g, 78f0532agca-gal-g, 78f0533agca-gal-g, 78f0534agca-gal-g, 78f0535agca-gal-g, 78f0536agca-gal-g, 78f0537agca-gal-g ? pd78f0531agca2-gal-g, 78f0532agca2-gal-g, 78f0533agca2-gal-g, 78f0534agca2-gal-g, 78f0535agca2-gal-g, 78f0536agca2-gal-g, 78f0537agca2-gal-g s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.80 0.886 0.15 1.60 0.20 p64gc-80-gal 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 64-pin plastic lqfp (14x14) 0.35 + 0.08 ? 0.04 b 16 32 64 17 33 49 48 1 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 902 jul 15, 2010 ? pd78f0531gk-uet-a, 78f0532gk-ue t-a, 78f0533gk-uet-a, 78f0534g k-uet-a, 78f0535gk-uet-a, 78f0536gk-uet-a, 78f0537gk-u et-a, 78f0537dgk-uet-a note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end l c lp hd he zd ze l1 a1 a2 a d e 16 32 1 64 17 33 49 48 s y e s x b m a3 s 64-pin plastic lqfp(12x12) 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gk-65-uet-1 3 + 5 ? 3 0.32 + 0.08 ? 0.07 b 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 903 jul 15, 2010 ? pd78f0531gk(a)-gaj-ax, 78f05 32gk(a)-gaj-ax, 78f0533gk(a)-g aj-ax, 78f0534gk(a)-gaj-ax, 78f0535gk(a)-gaj-ax, 78f0536gk(a )-gaj-ax, 78f0537gk(a)-gaj-ax ? pd78f0531gk(a2)-gaj-ax, 78f053 2gk(a2)-gaj-ax, 78f0533gk(a2)- gaj-ax, 78f0534gk(a2)-gaj-ax, 78f0535gk(a2)-gaj-ax, 78f0536gk(a2 )-gaj-ax, 78f0537gk(a2)-gaj-ax ? pd78f0531agk-gaj-ax, 78f0532agk-gaj-ax, 78f0533agk-gaj-ax, 78f0534agk-gaj-ax, 78f0535agk-gaj-ax, 78f0536agk-gaj-ax, 78f0537agk-gaj-ax, 78f0537dagk-gaj-ax ? pd78f0531agka-gaj-g, 78f0532agka-gaj-g, 78f0533agka-gaj-g, 78f0534agka-gaj-g, 78f0535agka- gaj-g, 78f0536agka-gaj-g, 78f0537agka-gaj-g ? pd78f0531agka2-gaj-g, 78f0532agka2-gaj- g, 78f0533agka2-gaj-g, 78f0534agka2-gaj-g, 78f0535agka2-gaj-g, 78f0536agka2 -gaj-g, 78f0537agka2-gaj-g l c lp hd he zd ze l1 a1 a2 a d e 0.125 + 0.75 ? 0.25 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gk-65-gaj 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 64-pin plastic lqfp (12x12) 0.30 + 0.08 ? 0.04 b 16 32 1 64 17 33 49 48 s y e s x b m a3 s 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 904 jul 15, 2010 ? pd78f0531ga-9ev-a, 78f0532ga-9 ev-a, 78f0533ga-9ev-a, 78f0534g a-9ev-a, 78f0535ga-9ev-a, 78f0536ga-9ev-a, 78f0537ga- 9ev-a, 78f0537dga-9ev-a s y e s x b m hd he zd ze a1 a2 a d e s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.40 0.07 0.08 0.50 0.50 l lp l1 0.50 0.60 0.15 1.00 0.20 p64ga-40-9ev-1 3 + 5 ? 3 note each lead centerline is located within 0.07 mm of its true position at maximum material condition. 64-pin plastic tqfp (fine pitch) (7x7) 0.18 0.05 b 16 32 1 64 17 33 49 48 l c lp l1 a3 detail of lead end 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 905 jul 15, 2010 ? pd78f0531aga-hab-ax, 78f0532aga-hab-ax, 78f0533aga-hab-ax, 78f0534aga-hab-ax, 78f0535aga-hab-ax, 78f0536aga-hab-ax, 78f 0537aga-hab-ax, 78f0537daga-hab-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s note each lead centerline is located within 0.07mm of its true position at maximum material condition. detail of lead end 16 32 1 64 17 33 49 48 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.40 0.07 0.08 0.50 0.50 l lp l1 0.50 0.60 0.15 1.00 0.20 p64ga-40-hab 3 + 5 ? 3 0.16 b 64-pin plastic tqfp (fine pitch) (7x7) + 0.07 ? 0.03 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 906 jul 15, 2010 ? pd78f0531fc-aa1-a, 78f0532fc-aa1- a, 78f0533fc-aa1-a, 78f0534fc- aa1-a, 78f0535fc-aa1-a, 78f0536fc- aa1-a, 78f0537fc-aa1-a, 78f0537dfc-aa1-a ? pd78f0531afc-aa1-a, 78f0532afc-aa1-a, 78f0533afc -aa1-a, 78f0534afc-aa1-a, 78f0535afc-aa1-a, 78f0536afc-aa1-a, 78f0537afc-aa1-a, 78f0537dafc-aa1-a item dimensions d e w e a b x y y1 zd ze 5.00 0.10 5.00 0.10 0.05 0.20 0.91 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.75 0.75 s y1 s a s detail of c part y s xab m e 60x b b 0.34 0.05 0.55 0.70 0.05 0.55 0.05 0.70 0.05 0.55 0.05 0.75 0.75 0.55 0.55 r0.17 0.05 r0.17 0.05 r0.12 0.05 r0.12 0.05 r0.275 0.05 r0.35 0.05 0.75 0.55 0.05 0.70 0.05 0.55 0.75 0.55 0.05 0.70 0.05 s wb zd ze index mark b c d a s wa d e 3.90 3.90 detail of d part detail of e part e 1 2 hg f e dc ba 3 4 5 6 7 8 (land pad) (aperture of solder resist) p64fc-50-aa1-1 64-pin plastic flga(5x5) 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 907 jul 15, 2010 ? pd78f0531af1-aa2-a, 78f0532af1-aa2-a, 78f0533af1 -aa2-a, 78f0534af1-aa2-a, 78f0535af1-aa2-a, 78f0536af1-aa2-a, 78f0537af1-aa2-a, 78f0537daf1-aa2-a 64-pin plastic fbga (4x4) item dimensions d e w a a1 a2 e 4.00 0.10 4.00 0.10 0.40 0.05 0.08 0.20 0.60 0.60 0.15 0.20 0.05 0.05 0.89 0.10 0.69 p64f1-40-aa2 0.25 (unit:mm) x y y1 zd ze b zd ze a index mark a2 a1 e s w a s wb b a s y s y1 s s x bab m 8 7 6 5 4 3 2 1 a b c d e f g h d e index mark 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 908 jul 15, 2010 34.5 78k0/kf2 ? pd78f0544gc-ubt-a, 78f 0545gc-ubt-a, 78f0546gc-ubt-a, 78f 0547gc-ubt-a, 78f0547dgc-ubt-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.17 + 0.03 ? 0.06 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-ubt 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 80-pin plastic lqfp(14x14) 0.32 0.06 b 20 40 80 21 41 61 60 1 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 909 jul 15, 2010 ? pd78f0544gc(a)-gad-ax, 78f0545g c(a)-gad-ax, 78f0546gc(a)-g ad-ax, 78f0547gc(a)-gad-ax ? pd78f0544gc(a2)-gad-ax, 78f0545g c(a2)-gad-ax, 78f0546gc(a2)-g ad-ax, 78f0547gc(a2)-gad-ax ? pd78f0544agc-gad-ax, 78f0545agc -gad-ax, 78f0546agc-gad-ax, 78f0547agc-gad-ax, 78f0547dagc- gad-ax ? pd78f0544agca-gad-g, 78f0545agca-gad- g, 78f0546agca-gad-g, 78f0547agca-gad-g ? pd78f0544agca2-gad-g, 78f0545agca2-gad- g, 78f0546agca2-gad-g, 78f0547agca2-gad-g s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-gad 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 0.30 b 20 40 80 21 41 60 1 + 0.08 ? 0.04 61 80-pin plastic lqfp(14x14) 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 910 jul 15, 2010 ? pd78f0544gk-8eu-a, 78f0 545gk-8eu-a, 78f0546gk-8e u-a, 78f0547gk-8eu-a, 78f0547dgk-8eu-a s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-8eu-1 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 20 40 1 80 21 41 61 60 80-pin plastic lqfp(fine pitch)(12x12) 78k0/kx2 chapter 34 package drawings r01uh0008ej0401 rev.4.01 911 jul 15, 2010 ? pd78f0544gk(a)-gak-ax, 78f05 45gk(a)-gak-ax, 78f0546gk(a )-gak-ax, 78f0547gk(a)-gak-ax ? pd78f0544gk(a2)-gak-ax, 78f0545g k(a2)-gak-ax, 78f0546gk(a2)- gak-ax, 78f0547gk(a2)-gak-ax ? pd78f0544agk-gak-ax, 78f0545agk-gak-ax, 78f0546agk-gak-ax, 78f0547agk-gak-ax, 78f0547dagk-gak-ax ? pd78f0544agka-gak-g, 78f0545agka-g ak-g, 78f0546agka-gak-g, 78f0547agka-gak-g ? pd78f0544agka2-gak-g, 78f0545agka2-gak-g, 78f0546agka2-gak-g, 78f0547agka2-gak-g s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-gak 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 20 40 1 80 21 41 61 60 + 0.07 ? 0.03 80-pin plastic lqfp(fine pitch)(12x12) 78k0/kx2 chapter 32 electrical specif ications (a2) grade products r01uh0008ej0401 rev.4.01 912 jul 15, 2010 chapter 35 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those re commended below, please contact an renesas electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http:// www2.renesas.com/pkg/en/mount/index.html) table 35-1. soldering conditions of conventional-specification products ( pd78f05xx and 78f05xxd) (1/3) (1) 36-pin plastic flga (4x4) pd78f050xfc-aa3-a (x = 0 to 3), 78f0503dfc-aa3-a 64-pin plastic flga (5x5) pd78f053xfc-aa1-a (x = 1 to 7), 78f0537dfc-aa1-a soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution the pd78f05xxd has an on-chip debug function, which is pr ovided for development and evaluation. do not use the on-chip debug function in pro ducts designated for m ass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability ther efore cannot be guaranteed. ren esas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 32 electrical specif ications (a2) grade products r01uh0008ej0401 rev.4.01 913 jul 15, 2010 table 35-1. soldering conditions of conventional-specification products ( pd78f05xx and 78f05xxd) (2/3) (2) 30-pin plastic ssop (7.62 mm (300)) pd78f050xmc-5a4-a (x = 0 to 3), 78f0503dmc-5a4-a 44-pin plastic lqfp (10x10) pd78f051xgb-ues-a (x = 1 to 3), 78f0513dgb-ues-a 48-pin plastic lqfp (fine pitch) (7x7) pd78f051xga-8eu-a (x = 1 to 5), 78f0515dga-8eu-a pd78f051xga(a)-gam-ax (x = 1 to 5), 78f051xga(a2)-gam-ax (x = 1 to 5) 52-pin plastic lqfp (10x10) pd78f052xgb-uet-a (x = 1 to 7), 78f0527dgb-uet-a 64-pin plastic lqfp (fine pitch) (10x10) pd78f053xgb-ueu-a (x = 1 to 7), 78f0537dgb-ueu-a pd78f053xgb(a)-gah-ax (x = 1 to 7), 78f053xgb(a2)-gah-ax (x = 1 to 7) 64-pin plastic lqfp (14x14) pd78f053xgc-ubs-a (x = 1 to 7), 78f0537dgc-ubs-a 64-pin plastic lqfp (12x12) pd78f053xgk-uet-a (x = 1 to 7), 78f0537dgk-uet-a 64-pin plastic tqfp (fine pitch) (7x7) pd78f053xga-9ev-a (x = 1 to 7), 78f0537dga-9ev-a 80-pin plastic lqfp (14x14) pd78f054xgc-ubt-a (x = 4 to 7), 78f0547dgc-ubt-a 80-pin plastic lqfp (fine pitch) (12x12) pd78f054xgk-8eu-a (x = 4 to 7), 78f0547dgk-8eu-a pd78f054xgk(a)-gak-ax (x = 4 to 7), 78f054xgk(a2)-gak-ax (x = 4 to 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution the pd78f05xxd has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in pro ducts designated for m ass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product relia bility therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 32 electrical specif ications (a2) grade products r01uh0008ej0401 rev.4.01 914 jul 15, 2010 table 35-1. soldering conditions of conventional-specification products ( pd78f05xx and 78f05xxd) (3/3) (3) 30-pin plastic ssop (7.62 mm (300)) pd78f050xmc(a)-cab-ax (x = 0 to 3), 78f050xmc(a2)-cab-ax (x = 0 to 3) 44-pin plastic lqfp (10x10) pd78f051xgb(a)-gaf-ax (x = 1 to 3), 78f051xgb(a2)-gaf-ax (x = 1 to 3) 52-pin plastic lqfp (10x10) pd78f052xgb(a)-gag-ax (x = 1 to 7), 78f052xgb(a2)-gag-ax (x = 1 to 7) 64-pin plastic lqfp (14x14) pd78f053xgc(a)-gal-ax (x = 1 to 7), 78f053xgc(a2)-gal-ax (x = 1 to 7) 64-pin plastic lqfp (12x12) pd78f053xgk(a)-gaj-ax (x = 1 to 7), 78f053xgk(a2)-gaj-ax (x = 1 to 7) 80-pin plastic lqfp (14x14) pd78f054xgc(a)-gad-ax (x = 4 to 7), 78f054xgc(a2)-gad-ax (x = 4 to 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ws60-207-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). 78k0/kx2 chapter 32 electrical specif ications (a2) grade products r01uh0008ej0401 rev.4.01 915 jul 15, 2010 table 35-2. soldering conditions of expanded-specification products ( pd78f05xxa and 78f05xxda) (1/2) (1) 36-pin plastic flga (4x4) pd78f050xafc-aa3-a (x = 0 to 3), 78f0503dafc-aa3-a 64-pin plastic flga (5x5) pd78f053xafc-aa1-a (x = 1 to 7), 78f0537dafc-aa1-a soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 (2) 48-pin plastic lqfp (fine pitch) (7x7) pd78f051xaga-gam-ax (x = 1 to 5), 78f0515daga-gam-ax pd78f051xagaa-gam-g (x = 1 to 5), 78f051xagaa2-gam-g (x = 1 to 5) 64-pin plastic lqfp (fine pitch) (10x10) pd78f053xagb-gah-ax (x = 1 to 7), 78f0537dagb-gah-ax pd78f053xagba-gah-g (x = 1 to 7), 78f053xagba2-gah-g (x = 1 to 7) 80-pin plastic lqfp (fine pitch) (12x12) pd78f054xagk-gak-ax (x = 4 to 7), 78f0547dagk-gak-ax pd78f054xagka-gak-g (x = 4 to 7), 78f 054xagka2-gak-g (x = 4 to 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution the pd78f05xxda has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug functi on in products designate d for mass production, because the guaranteed number of re writable times of the flash memo ry may be exceeded when this function is used, and product reliability therefor e cannot be guaranteed. renesas electronics is not liable for problems occurring when th e on-chip debug function is used. 78k0/kx2 chapter 32 electrical specif ications (a2) grade products r01uh0008ej0401 rev.4.01 916 jul 15, 2010 table 35-2. soldering conditions of expanded-specification products ( pd78f05xxa and 78f05xxda) (2/2) (3) 30-pin plastic ssop (7.62 mm (300)) pd78f050xamc-cab-ax (x = 0 to 3), 78f0503damc-cab-ax pd78f050xamca-cab-g (x = 0 to 3), 78f050xamca2-cab-g (x = 0 to 3) 38-pin plastic ssop (7.62 mm (300)) pd78f051xamc-gaa-ax (x = 1 to 3), 78f0513damc-gaa-ax pd78f051xamca-gaa-g (x = 1 to 3), 78f051xamca2-gaa-g (x = 1 to 3) 44-pin plastic lqfp (10x10) pd78f051xagb-gaf-ax (x = 1 to 3), 78f0513dagb-gaf-ax pd78f05x1agba-gaf-g (x = 1 to 3), 78f051xagba2-gaf-g (x = 1 to 3) 52-pin plastic lqfp (10x10) pd78f052xagb-gag-ax (x = 1 to 7), 78f0527dagb-gag-ax pd78f052xagba-gag-g (x = 1 to 7), 78f052xagba2-gag-g (x = 1 to 7) 64-pin plastic lqfp (14x14) pd78f053xagc-gal-ax (x = 1 to 7), 78f0537dagc-gal-ax pd78f053xagca-gal-g (x = 1 to 7), 78f053xagca2-gal-g (x = 1 to 7) 64-pin plastic lqfp (12x12) pd78f053xagk-gaj-ax (x = 1 to 7), 78f0537dagk-gaj-ax pd78f053xagka-gaj-g (x = 1 to 7), 78f053xagka2-gaj-g (x = 1 to 7) 80-pin plastic lqfp (14x14) pd78f054xagc-gad-g (x = 4 to 7), 78f0547dagc-gad-ax pd78f054xagca-gad-g (x = 4 to 7), 78f054xagca2-gad-g (x = 4 to 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ws60-107-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. cautions 1. do not use differ ent soldering methods together (except for partial heating). 2. the pd78f05xxda has an on -chip debug function, which is provided for development and evaluation. do not use the on-chip debug func tion in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability ther efore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 78k0/kx2 chapter 36 cautions for wait r01uh0008ej0401 rev.4.01 917 jul 15, 2010 chapter 36 cautions for wait 36.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflicts with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conf lict, therefore, the cpu repeat edly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction proc essing but waits. if this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see tables 36-1 and 36-2 ). this must be noted when real-time processing is performed. 78k0/kx2 chapter 36 cautions for wait r01uh0008ej0401 rev.4.01 918 jul 15, 2010 36.2 peripheral hardware that generates wait table 36-1 lists the registers that issue a wait request when accessed by the cpu, and the number of cpu wait clocks and table 36-2 lists the ram accesses that issue a wa it request and the number of cpu wait clocks. table 36-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) serial interface iic0 iics0 read 1 clock (fixed) adm write ads write adpc write adcr read 1 to 5 clocks (when f ad = f prs /2 is selected) 1 to 7 clocks (when f ad = f prs /3 is selected) 1 to 9 clocks (when f ad = f prs /4 is selected) 2 to 13 clocks (when f ad = f prs /6 is selected) 2 to 17 clocks (when f ad = f prs /8 is selected) 2 to 25 clocks (when f ad = f prs /12 is selected) a/d converter the above number of clocks is when the same source clock is selected for f cpu and f prs . the number of wait clocks can be calculated by the following expression and under the following conditions. 78k0/kx2 chapter 36 cautions for wait r01uh0008ej0401 rev.4.01 919 jul 15, 2010 table 36-2. ram accesses that generate wait an d number of cpu wait clocks (78k0/kf2 only) area access number of wait clocks buffer ram write 1 to 81 clocks note 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 920 jul 15, 2010 appendix a development tools the following development tools are available for the development of systems t hat employ the 78k0/kx2 microcontrollers. figure a-1 shows the developm ent tool configuration. 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 921 jul 15, 2010 figure a-1. development tool configuration (1/2) (1) when using the in-circu it emulator qb-78k0kx2 language processing software assembler package c compiler package device file note 1 debugging software integrated debugger note 1 system simulator note 2 host machine (pc or ews) qb-78k0kx2 note 4 emulation probe target system software package project manager software package control software (windows only) note 3 power supply unit usb interface cable note 4 78k0/kx2 microcontroller flash memory programmer note 4 flash memory write adapter < flash memory write environment > conversion adapter on-board programming off-board programming target connector notes 1. download the device file for 78k0/kx2 microcontro llers (df780547) and the integrated debugger id78k0- qb from the download site for development tools (http://www2.renesas.com/mi cro/en/ods/index.html). 2. sm+ for 78k0 (instruction simulation version) is included in the software package. sm+ for 78k0/kx2 (instruction + peripheral simulation version) is not included. 3. the project manager pm+ is in cluded in the assembler package. pm+ cannot be used other than with windows tm . 4. qb-78k0kx2 is supplied with the integrated debug ger id78k0-qb, a usb interface cable, the on-chip debug emulator with programming functi on qb-mini2, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. any other pr oducts are sold separately. 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 922 jul 15, 2010 figure a-1. development tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 language processing software ? assembler package ? c compiler package ? device file note 1 debugging software ? integrated debugger note 1 ? system simulator note 2 host machine (pc or ews) usb interface cable note 4 qb-mini2 note 4 78k0-ocd board note 4 target connector target system ? software package ? project manager software package 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 923 jul 15, 2010 a.1 software package sp78k0 78k0 microcontroller software package development tools (software) common to the 78k0 microcontrollers are combined in this package. a.2 language processing software ra78k0 note 1 assembler package this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df780547). 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 924 jul 15, 2010 a.3 flash memory programming tools a.3.1 when using flash memory program mer fg-fp5, fl-pr5, fg-fp4, and fl-pr4 fg-fp5, fl-pr5, pg-fp4 note 1 , fl-pr4 flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. fa-xxxx note 2 flash memory programming adapter flash memory programming adap ter used connected to the flash memory programmer for use. notes 1. phase-out 2. the part numbers of the flash memory programming adapter and the packages of the target device are described below. package flash memory programming adapter 30-pin plastic ssop (mc-5a4 and mc-cab types) fa-30mc-cab-b, fa-78f0503mc-5a4-rx 78k0/kb2 36-pin plastic flga (fc-aa3 type) fa-36fc-aa3-b, fa-78f0503fc-aa3-rx 38-pin plastic ssop (mc- gaa type) fa-38mc-gaa-b 44-pin plastic lqfp (gb- ues and gb-gaf types) fa-44gb-gaf-b, fa-78f0513gb-ues-rx 78k0/kc2 48-pin plastic lqfp (ga- 8eu and ga-gam types) fa-48ga-gam-b, fa-78f0515ga-8eu-rx 78k0/kd2 52-pin plastic lqfp (gb-uet and gb-gag types) fa-52gb-gag-b, fa-78f0527gb-uet-rx 64-pin plastic lqfp (gb-ueu and gb-gah types) fa-64gb-gah-b, fa-78f0537gb-ueu-rx 64-pin plastic lqfp (gc- ubs and gc-gal types) fa-64gc-gal-b, fa-78f0537gc-ubs-rx 64-pin plastic lqfp (gk- uet and gk-gaj types) fa-64gk-gaj-b, fa-78f0537gk-uet-rx 64-pin plastic tqfp (ga-9ev and ga-hab types) fa-64ga-8ev-b, fa-64ga-hab-b, fa-78f0537ga-9ev-rx 78k0/ke2 64-pin plastic flga (fc-aa1 type) fa-78f0537fc-aa1-rx 80-pin plastic lqfp (gc- ubt and gc-gad types) fa-80gc-gad-b, fa-78f0547gc-ubt-rx 78k0/kf2 80-pin plastic lqfp (g k-8eu and gk-gak types) fa-80gk-gak-b, fa-78f0547gk-8eu-rx remarks 1. fl-pr5, fl-pr4, and fa-xxxx are products of naito densei machida mfg. co., ltd (http://www.ndk-m.co.jp/, tel: +81-42-750-4172). 2. use the latest version of the flash memory programming adapter. 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 925 jul 15, 2010 a.3.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application system s using the 78k0/kx2 microcontrollers. when using this as flash memo ry programmer, it should be used in combination with a connection cable (16-pin cable) and a usb in terface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface c able and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. a connection cabl e (10-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). a.4 debugging tools (hardware) a.4.1 when using in-circu it emulator qb-78k0kx2 qb-78k0kx2 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0/kx2 microcontrollers. it supports to the integrated debugger (id78k0- qb). this emulator should be used in combinat ion with a power supply unit and emulation probe, and the usb is used to connect this emulator to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-xxxx-ea-xxx note exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. qb-xxxx-ys-xxx note space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. qb-xxxx-yq-xxx note yq connector this yq connector is used to connect the target connector and exchange adapter. qb-xxxx-hq-xxx note mount adapter this mount adapter is used to mount the target device with socket. qb-xxxx-nq-xxx note , target connector this target connector is used to mount on the target system. (note and remarks are listed on the next page or later.) 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 926 jul 15, 2010 note the part numbers of the exchange adapter, space adapter, yq connector, mount adapter, and target connector and the packages of the target device are described below. package exchange adapter space adapter yq connector mount adapter target connector 30-pin plastic ssop (mc-5a4 and mc-cab types) qb-30mc- ea-02t qb-30mc- ys-01t qb-30mc- yq-01t qb-30mc- hq-01t qb-30mc- nq-01t 78k0/kb2 36-pin plastic flga (fc-aa3 type) qb-36fc- ea-01t none none none qb-36fc- nq-01t 38-pin plastic ssop (mc-gaa type) qb-38mc- ea-01t qb-38mc- yq-01t qb-38mc- yq-01t qb-38mc- hq-01t qb-38mc- nq-01t 44-pin plastic lqfp (gb-ues and gb- gaf types) qb-44gb- ea-03t qb-44gb- ys-01t qb-44gb- yq-01t qb-44gb- hq-01t qb-44gb- nq-01t 78k0/kc2 48-pin plastic lqfp (ga-8eu and ga- gam types) qb-48ga- ea-02t qb-48ga- ys-01t qb-48ga- yq-01t qb-48ga- hq-01t qb-48ga- nq-01t 78k0/kd2 52-pin plastic lqfp (gb-uet and gb- gag types) qb-52gb- ea-02t qb-52gb- ys-01t qb-52gb- yq-01t qb-52gb- hq-01t qb-52gb- nq-01t 64-pin plastic lqfp (gb-ueu and gb- gah types) qb-64gb- ea-04t qb-64gb- ys-01t qb-64gb- yq-01t qb-64gb- hq-01t qb-64gb- nq-01t 64-pin plastic lqfp (gc-ubs and gc- gal types) qb-64gc- ea-03t qb-64gc- ys-01t qb-64gc- yq-01t qb-64gc- hq-01t qb-64gc- nq-01t 64-pin plastic lqfp (gk-uet and gk- gaj types) qb-64gk- ea-04t qb-64gk- ys-01t qb-64gk- yq-01t qb-64gk- hq-01t qb-64gk- nq-01t 64-pin plastic tqfp (ga-9ev and ga- hab types) qb-64ga- ea-01t qb-64ga- ys-01t qb-64ga- yq-01t qb-64ga- hq-01t qb-64ga- nq-01t 78k0/ke2 64-pin plastic flga (fc-aa1 type) qb-64fc- ea-01t none none none qb-64fc- nq-01t 80-pin plastic lqfp (gc-ubt and gc- gad types) qb-80gc- ea-01t qb-80gc- ys-01t qb-80gc- yq-01t qb-80gc- hq-01t qb-80gc- nq-01t 78k0/kf2 80-pin plastic lqfp (gk-8eu and gk- gak type) qb-80gk- ea-01t qb-80gk- ys-01t qb-80gk- yq-01t qb-80gk- hq-01t qb-80gk- nq-01t 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 927 jul 15, 2010 remarks 1. the qb-78k0kx2 is supplied with the integrated debugger id78k0-qb, a usb interface cable, the on- chip debug emulator qb-mini2, connection cables ( 10-pin and 16-pin cables), and the 78k0-ocd board. download the software for operating the qb-mini 2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/i ndex.html) when using the qb-mini2. 2. the packed contents of qb-78k0kx2 diffe r depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-78k0kx2-zzz none qb-78k0kx2-t30mc qb-30mc-ea-02t qb-30mc-yq-01t qb-30mc-nq-01t qb-78k0kx2-t36fc qb-36fc-ea-01t none qb-36fc-nq-01t qb-78k0kx2-t38mc qb-38mc-ea-01t qb-38mc-yq-01t qb-38mc-nq-01t qb-78k0kx2-t44gb qb-44gb-ea-03t qb-44gb-yq-01t qb-44gb-nq-01t qb-78k0kx2-t48ga qb-48ga-ea-02t qb-48ga-yq-01t qb-48ga-nq-01t qb-78k0kx2-t52gb qb-52gb-ea-02t qb-52gb-yq-01t qb-52gb-nq-01t qb-78k0kx2-t64gb qb-64gb-ea-04t qb-64gb-yq-01t qb-64gb-nq-01t qb-78k0kx2-t64gc qb-64gc-ea-03t qb-64gc-yq-01t qb-64gc-nq-01t qb-78k0kx2-t64gk qb-64gk-ea-04t qb-64gk-yq-01t qb-64gk-nq-01t qb-78k0kx2-t64ga qb-64ga-ea-01t qb-64ga-yq-01t qb-64ga-nq-01t qb-78k0kx2-t64fc qb-64fc-ea-01t none qb-64fc-nq-01t qb-78k0kx2-t80gc qb-80gc-ea-01t qb-80gc-yq-01t qb-80gc-nq-01t qb-78k0kx2-t80gk qb-78k0kx2 qb-80-ep-01t qb-80gk-ea-01t qb-80gk-yq-01t qb-80gk-nq-01t note under development a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0/kx2. it is available also as flash memory programmer dedicated to microcontrollers with on-chip flash memory. when using this as on-chip debug emulator, it should be used in combination with a connection cable (10- pin cable or 16-pin cable), a usb interfac e cable that is used to connect the host machine, and the 78k0-ocd board. target connector specifications 10-pin general-purpose connector (2 .54 mm pitch) or 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface c able and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. a connection cabl e (10-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). 78k0/kx2 appendix a development tools r01uh0008ej0401 rev.4.01 928 jul 15, 2010 a.5 debugging tools (software) id78k0-qb note integrated debugger this debugger supports the in-circuit emul ators for the 78k0 microcontrollers. the id78k0-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (df780547). sm+ for 78k0 sm+ for 78k0/kx2 system simulator system simulator is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of system simulator allows the exec ution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. system simulator should be used in combination with the device file (df780547). the following two types of system simulators supporting the 78k0/kx 2 microcontrollers are available. ? sm+ for 78k0 (instruction simulation version) this can only simulate a cpu. it is included in the software package. ? sm+ for 78k0/ kx2 (instruction + peripheral simulation version) this can simulate a cpu and peripheral hardw are (ports, timers, serial interfaces, etc.). it is sold separately from the software package. note download the id78k0-qb from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 929 jul 15, 2010 appendix b notes on target system design this chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the qb-78k0kx2 is used. figure b-1. for 30-pin mc package 12.5 11.5 13.375 10 12.5 11.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 930 jul 15, 2010 figure b-2. for 36-pin fc package 3 3.5 4 3.5 21.8 : exchange adapter area: components up to 2.5 mm in height can be mounted : emulation probe tip area: components up to 4.5 mm in height can be mounted figure b-3. for 44-pin gb package 15 9.85 13.375 10 15 9.85 17.375 10 : exchange adapter area: components up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 931 jul 15, 2010 figure b-4. for 48-pin ga package 15 9.5 13.375 10 15 9.5 17.375 10 : exchange adapter area: components up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) figure b-5. for 52-pin gb package 15 9.85 13.375 10 15 9.85 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by using space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 932 jul 15, 2010 figure b-6. for 64-pin fc package 3 3.5 4 3.5 21.8 : exchange adapter area (connector part): components up to 2.45 mm in height can be mounted : exchange adapter area (probe part): components up to 4.5 mm in height can be mounted figure b-7. for 64-pin ga package 15 9.5 13.375 10 15 9.5 17.375 10 : exchange adapter area: componen ts up to 17.45 mm in height can be mounted note : emulation probe tip area: comp onents up to 24.45 mm in height can be mounted note note height can be adjusted by using space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 933 jul 15, 2010 figure b-8. for 64-pin gb package 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) figure b-9. for 64-pin gc package 15 11.85 13.375 10 15 11.85 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 934 jul 15, 2010 figure b-10. for 64-pin gk package 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) figure b-11. for 80-pin gc package 15 12.05 13.375 10 15 12.05 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) 78k0/kx2 appendix b notes on target system design r01uh0008ej0401 rev.4.01 935 jul 15, 2010 figure b-12. for 80-pin gk package 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: compon ents up to 17.45 mm in height can be mounted note : emulation probe tip area: components up to 24.45 mm in height can be mounted note note height can be adjusted by us ing space adapters (each adds 2.4 mm) 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 936 jul 15, 2010 appendix c register index c.1 register index (in al phabetical order with respect to register names) [a] a/d converter mode register (adm) .............................................................................................. ............................. 412 a/d port configuratio n register (adpc) ......................................................................................... ..................... 219, 419 analog input channel specification re gister (ads).............................................................................. ........................ 418 asynchronous serial interface control register 6 (asi cl6) ...................................................................... ................... 466 asynchronous serial interface operat ion mode regist er 0 (a sim0)................................................................ ............. 436 asynchronous serial interface operat ion mode regist er 6 (a sim6)................................................................ ............. 460 asynchronous serial interface recepti on error status regi ster 0 ( asis0) ........................................................ ............ 438 asynchronous serial interface recepti on error status regi ster 6 ( asis6) ........................................................ ............ 462 asynchronous serial interface transmi ssion status regi ster 6 ( asif6)........................................................... ............. 463 automatic data transfer address count register 0 (adt c0)....................................................................... ................. 523 automatic data transfer address point s pecification regist er 0 (a dtp0) ......................................................... ........... 521 automatic data transfer interval s pecification regist er 0 (adti0).............................................................. .................. 522 [b] baud rate generator contro l register 0 (brg c0) ................................................................................. ....................... 439 baud rate generator contro l register 6 (brg c6) ................................................................................. ....................... 465 [c] capture/compare contro l register 00 (crc0 0) .................................................................................... ....................... 280 capture/compare contro l register 01 (crc0 1) .................................................................................... ....................... 280 clock operation mode select register (oscctl) .................................................................................. ..................... 229 clock output selectio n register (cks).......................................................................................... ............................... 404 clock selection regi ster 6 (c ksr6) ............................................................................................. ............................... 463 [d] divisor selection r egister 0 (brgca0) .......................................................................................... ............................. 520 [e] 8-bit a/d conversion resu lt register (adcrh) ................................................................................... ......................... 417 8-bit timer compare re gister 50 (cr50) ......................................................................................... ............................. 347 8-bit timer compare re gister 51 (cr51) ......................................................................................... ............................. 347 8-bit timer coun ter 50 (t m50) .................................................................................................. ................................... 347 8-bit timer coun ter 51 (t m51) .................................................................................................. ................................... 347 8-bit timer h carrier cont rol register 1 (tmc yc1) .............................................................................. ......................... 371 8-bit timer h compare register 00 (cmp00)...................................................................................... .......................... 366 8-bit timer h compare register 01 (cmp01)...................................................................................... .......................... 366 8-bit timer h compare register 10 (cmp10)...................................................................................... .......................... 366 8-bit timer h compare register 11 (cmp11)...................................................................................... .......................... 366 8-bit timer h mode re gister 0 (tmhmd0) ......................................................................................... .......................... 367 8-bit timer h mode re gister 1 (tmhmd1) ......................................................................................... .......................... 367 8-bit timer mode contro l register 50 (tmc 50)................................................................................... .......................... 351 8-bit timer mode contro l register 51 (tmc 51)................................................................................... .......................... 351 external interrupt falling edg e enable regist er (egn) .......................................................................... ....................... 652 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 937 jul 15, 2010 external interrupt rising e dge enable regist er (egp) ........................................................................... ....................... 652 [i] iic clock selection re gister 0 (iiccl0) ........................................................................................ ................................ 565 iic control regist er 0 ( iicc0) ................................................................................................. ..................................... 556 iic flag register 0 (iicf0).................................................................................................... ........................................ 563 iic function expansion re gister 0 (iicx0)...................................................................................... .............................. 566 iic shift regist er 0 ( iic0) .................................................................................................... ......................................... 553 iic status regist er 0 ( iics0).................................................................................................. ...................................... 561 input switch contro l register (isc) ............................................................................................ .................................. 468 internal expansion ram size switching regi ster (ixs) ........................................................................... ..................... 722 internal memory size s witching regist er (ims).................................................................................. .......................... 721 internal oscillation mode register (rcm) ....................................................................................... ............................. 235 interrupt mask flag re gister 0h (mk0h)......................................................................................... ............................. 643 interrupt mask flag re gister 0l (mk0l) ......................................................................................... .............................. 643 interrupt mask flag re gister 1h (mk1h)......................................................................................... ............................. 643 interrupt mask flag re gister 1l (mk1l) ......................................................................................... .............................. 643 interrupt request flag register 0h (if0h)...................................................................................... ............................... 637 interrupt request flag register 0l (if 0l)...................................................................................... ................................ 637 interrupt request flag register 1h (if1h)...................................................................................... ............................... 637 interrupt request flag register 1l (if 1l)...................................................................................... ................................ 637 [k] key return mode re gister (krm)................................................................................................. ................................ 665 [l] low-voltage detection level selection regi ster (l vis) .......................................................................... ....................... 701 low-voltage detecti on register (lvim).......................................................................................... .............................. 699 [m] main clock mode register (mcm)................................................................................................. ............................... 237 main osc control register (moc) ................................................................................................ .............................. 236 memory bank select register (bank)............................................................................................. .......................... 150 multiplication/division data r egister a0 (md a0h, md a0l)........................................................................ .................. 623 multiplication/division dat a register b0 (mdb0) ................................................................................ .......................... 624 multiplier/divider contro l register 0 (dm uc0).................................................................................. ............................ 625 [o] oscillation stabilization time c ounter status r egister (ostc).................................................................. ............ 238, 667 oscillation stabilization time select regi ster (osts) .......................................................................... ................. 239, 668 [p] port mode regist er 0 (p m0) ..................................................................................................... ................... 205, 28 8, 498 port mode regist er 1 (p m1) .................................................................................................205, 353, 372, 440, 468, 498 port mode regist er 2 (p m2) ..................................................................................................... ........................... 205, 420 port mode regist er 3 (p m3) ..................................................................................................... ........................... 205, 353 port mode regist er 4 (p m4) ..................................................................................................... ................................... 205 port mode regist er 5 (p m5) ..................................................................................................... ................................... 205 port mode regist er 6 (p m6) ..................................................................................................... ........................... 205, 568 port mode regist er 7 (p m7) ..................................................................................................... ................................... 205 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 938 jul 15, 2010 port mode regist er 12 (p m12) ................................................................................................... ......................... 205, 702 port mode regist er 14 (p m14) ................................................................................................... ................. 205, 40 7, 523 port regist er 0 (p0) ........................................................................................................... .......................................... 210 port regist er 1 (p1) ........................................................................................................... .......................................... 210 port regist er 2 (p2) ........................................................................................................... .......................................... 210 port regist er 3 (p3) ........................................................................................................... .......................................... 210 port regist er 4 (p4) ........................................................................................................... .......................................... 210 port regist er 5 (p5) ........................................................................................................... .......................................... 210 port regist er 6 (p6) ........................................................................................................... .......................................... 210 port regist er 7 (p7) ........................................................................................................... .......................................... 210 port register 12 (p12) ......................................................................................................... ........................................ 210 port register 13 (p13) ......................................................................................................... ........................................ 210 port register 14 (p14) ......................................................................................................... ........................................ 210 prescaler mode regi ster 00 (prm00) ............................................................................................. ............................ 285 prescaler mode regi ster 01 (prm01) ............................................................................................. ............................ 285 priority specification fl ag register 0h (p r0h) ................................................................................. ............................ 648 priority specification fl ag register 0l (p r0l) ................................................................................. ............................. 648 priority specification fl ag register 1h (p r1h) ................................................................................. ............................ 648 priority specification fl ag register 1l (p r1l) ................................................................................. ............................. 648 processor clock cont rol regist er (pcc) ......................................................................................... ............................. 232 pull-up resistor opti on register 0 (pu0) ....................................................................................... ............................... 215 pull-up resistor opti on register 1 (pu1) ....................................................................................... ............................... 215 pull-up resistor opti on register 3 (pu3) ....................................................................................... ............................... 215 pull-up resistor opti on register 4 (pu4) ....................................................................................... ............................... 215 pull-up resistor opti on register 5 (pu5) ....................................................................................... ............................... 215 pull-up resistor opti on register 6 (pu6) ....................................................................................... ............................... 215 pull-up resistor opti on register 7 (pu7) ....................................................................................... ............................... 215 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ............................. 215 pull-up resistor opti on register 14 (pu 14) ..................................................................................... ............................. 215 [r] receive buffer regi ster 0 (rxb0)............................................................................................... ................................. 435 receive buffer regi ster 6 (rxb6)............................................................................................... ................................. 459 receive shift regi ster 0 (rxs0) ................................................................................................ .................................. 435 receive shift regi ster 6 (rxs6) ................................................................................................ .................................. 459 remainder data regi ster 0 (sdr0) ............................................................................................... .............................. 623 reset control flag register (resf)............................................................................................. ................................. 691 [s] serial clock selection register 10 (csic10) .................................................................................... ............................ 495 serial clock selection register 11 (csic11) .................................................................................... ............................ 495 serial i/o shift r egister 0 (sioa0) ............................................................................................ ................................... 515 serial i/o shift regi ster 10 (sio10) ........................................................................................... .................................. 492 serial i/o shift regi ster 11 (sio11) ........................................................................................... .................................. 492 serial operation mode register 10 (csim 10) ..................................................................................... ......................... 493 serial operation mode register 11 (csim 11) ..................................................................................... ......................... 493 serial operation m ode specification regi ster 0 (c sima0) ........................................................................ ................... 515 serial status regi ster 0 (csis0) ............................................................................................... ................................... 517 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 939 jul 15, 2010 serial trigger regi ster 0 (c sit0).............................................................................................. .................................... 519 slave address regi ster 0 (sva0) ................................................................................................ ................................ 553 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ..................... 273 16-bit timer capture/compar e register 001 (c r001) .............................................................................. ..................... 273 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ..................... 273 16-bit timer capture/compar e register 011 (c r011) .............................................................................. ..................... 273 16-bit timer count er 00 (t m00) ................................................................................................. .................................. 272 16-bit timer count er 01 (t m00) ................................................................................................. .................................. 272 16-bit timer mode contro l register 00 (tmc 00).................................................................................. ......................... 277 16-bit timer mode contro l register 01 (tmc 01).................................................................................. ......................... 277 16-bit timer output cont rol register 00 (t oc00) ................................................................................ .......................... 282 16-bit timer output cont rol register 01 (t oc01) ................................................................................ .......................... 282 [t] timer clock selection register 50 (tcl50)...................................................................................... ............................ 348 timer clock selection register 51 (tcl51)...................................................................................... ............................ 348 10-bit a/d conversion resu lt register (adcr) ................................................................................... .......................... 416 transmit buffer regi ster 10 (s otb10) ........................................................................................... ............................. 492 transmit buffer regi ster 11 (s otb11) ........................................................................................... ............................. 492 transmit buffer regi ster 6 (txb6) .............................................................................................. ................................. 459 transmit shift regi ster 0 (txs0)............................................................................................... ................................... 435 transmit shift regi ster 6 (txs6)............................................................................................... ................................... 459 [w] watch timer operation mode register (wtm) ...................................................................................... ....................... 391 watchdog timer enable register (wdte).......................................................................................... .......................... 398 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 940 jul 15, 2010 c.2 register index (in al phabetical order with respect to register symbol) [a] adcr: 10-bit a/d conver sion result regist er................................................................................... .................... 416 adcrh: 8-bit a/d conver sion result register................................................................................... ...................... 417 adm: a/d conver ter mode re gister.............................................................................................. ..................... 412 adpc: a/d port conf iguration regist er ......................................................................................... ............... 219, 419 ads: analog input channel specific ation re gister.............................................................................. ............... 418 adtc0: automatic data transfe r address count register 0 ....................................................................... ............ 523 adti0: automatic data transfer inte rval specificati on register 0 .............................................................. ........... 522 adtp0: automatic data transfer addre ss point specificat ion regist er 0......................................................... ....... 521 asicl6: asynchronous serial in terface control register 6 ...................................................................... ............... 466 asif6: asynchronous serial interfac e transmission stat us regist er 6 ........................................................... ...... 463 asim0: asynchronous serial interf ace operation mode register 0 ................................................................ ....... 436 asim6: asynchronous serial interf ace operation mode register 6 ................................................................ ....... 460 asis0: asynchronous serial interface reception error stat us regist er 0 ........................................................ ...... 438 asis6: asynchronous serial interface reception error stat us regist er 6 ........................................................ ...... 462 [b] bank: memory bank select register ............................................................................................. ................... 150 brgc0: baud rate genera tor control r egister 0 ................................................................................. ................... 439 brgc6: baud rate genera tor control r egister 6 ................................................................................. ................... 465 brgca0: divisor sele ction regi ster 0.......................................................................................... ............................ 520 [c] cks: clock output se lection re gister.......................................................................................... ...................... 404 cksr6: clock select ion register 6............................................................................................. ........................... 463 cmp00: 8-bit timer h compare regi ster 00 ...................................................................................... ..................... 366 cmp01: 8-bit timer h compare regi ster 01 ...................................................................................... ..................... 366 cmp10: 8-bit timer h compare regi ster 10 ...................................................................................... ..................... 366 cmp11: 8-bit timer h compare regi ster 11 ...................................................................................... ..................... 366 cr000: 16-bit timer captur e/compare regi ster 000 .............................................................................. ................ 273 cr001: 16-bit timer captur e/compare regi ster 000 .............................................................................. ................ 273 cr010: 16-bit timer captur e/compare regi ster 010 .............................................................................. ................ 273 cr011: 16-bit timer captur e/compare regi ster 011 .............................................................................. ................ 273 cr50: 8-bit timer co mpare regi ster 50......................................................................................... ...................... 347 cr51: 8-bit timer co mpare regi ster 51......................................................................................... ...................... 347 crc00: capture/compare control regi ster 00 .................................................................................... .................. 280 crc01: capture/compare control regi ster 01 .................................................................................... .................. 280 csic10: serial clock selection re gister 10 .................................................................................... ........................ 495 csic11: serial clock selection re gister 11 .................................................................................... ........................ 495 csim10: serial operat ion mode regi ster 10..................................................................................... ...................... 493 csim11: serial operat ion mode regi ster 11..................................................................................... ...................... 493 csima0: serial operation m ode specification register 0 ........................................................................ ................ 515 csis0: serial st atus regi ster 0 ............................................................................................... ............................. 517 csit0: serial tr igger regi ster 0 .............................................................................................. ............................. 519 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 941 jul 15, 2010 [d] dmuc0: multiplier/divider control re gister 0 .................................................................................. ........................ 625 [e] egn: external interrupt falling edge enabl e regi ster .......................................................................... .............. 652 egp: external interrupt rising edge enabl e regi ster ........................................................................... .............. 652 [i] if0h: interrupt req uest flag regi ster 0h ...................................................................................... ...................... 637 if0l: interrupt req uest flag regi ster 0l...................................................................................... ....................... 637 if1h: interrupt req uest flag regi ster 1h ...................................................................................... ...................... 637 if1l: interrupt req uest flag regi ster 1l...................................................................................... ....................... 637 iic0: iic shi ft register 0 .................................................................................................... ............................... 553 iicc0: iic contro l register 0 ................................................................................................. .............................. 556 iiccl0: iic clock se lection regi ster 0........................................................................................ ........................... 565 iicf0: iic flag register 0 .................................................................................................... ................................ 563 iics0: iic status register 0 .................................................................................................. .............................. 561 iicx0: iic function ex pansion regi ster 0 ...................................................................................... ...................... 566 ims: internal memory size switchin g regi ster.................................................................................. ................ 721 isc: input switch control regist er ............................................................................................ ........................ 468 ixs: internal expansion ra m size switch ing regi ster ........................................................................... .......... 722 [k] krm: key return mode re gister ................................................................................................. ....................... 665 [l] lvim: low-voltage detection register.......................................................................................... ...................... 699 lvis: low-voltage detecti on level select ion regi ster .......................................................................... .............. 701 [m] mcm: main clo ck mode re gister................................................................................................. ....................... 237 mda0h: multiplication/d ivision data r egister a0............................................................................... ..................... 623 mda0l: multiplication/d ivision data r egister a0............................................................................... ..................... 623 mdb0: multiplication/div ision data r egister b0................................................................................ .................... 624 mk0h: interrupt ma sk flag regi ster 0h ......................................................................................... ...................... 643 mk0l: interrupt ma sk flag regi ster 0l ......................................................................................... ....................... 643 mk1h: interrupt ma sk flag regi ster 1h ......................................................................................... ...................... 643 mk1l: interrupt ma sk flag regi ster 1l ......................................................................................... ....................... 643 moc: main osc control r egister ................................................................................................ ...................... 236 [o] oscctl: clock operation mode select regist er .................................................................................. ................... 229 ostc: oscillation stabilization time counter st atus r egister .................................................................. ..... 238, 667 osts: oscillation stabilizat ion time sele ct regi ster .......................................................................... .......... 239, 668 [p] p0: port r egister 0 ........................................................................................................... .............................. 210 p1: port r egister 1 ........................................................................................................... .............................. 210 p2: port r egister 2 ........................................................................................................... .............................. 210 p3: port r egister 3 ........................................................................................................... .............................. 210 p4: port r egister 4 ........................................................................................................... .............................. 210 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 942 jul 15, 2010 p5: port r egister 5 ........................................................................................................... .............................. 210 p6: port r egister 6 ........................................................................................................... .............................. 210 p7: port r egister 7 ........................................................................................................... .............................. 210 p12: port register 12 ......................................................................................................... .............................. 210 p13: port register 13 ......................................................................................................... .............................. 210 p14: port register 14 ......................................................................................................... .............................. 210 pcc: processor cloc k control register......................................................................................... ..................... 232 pm0: port m ode regist er 0 ..................................................................................................... .......... 205, 288, 498 pm1: port mode regi ster 1 ........................................................................................205, 35 3, 372 , 440, 468, 498 pm2: port m ode regist er 2 ..................................................................................................... .................. 205, 420 pm3: port m ode regist er 3 ..................................................................................................... .................. 205, 353 pm4: port m ode regist er 4 ..................................................................................................... .......................... 205 pm5: port m ode regist er 5 ..................................................................................................... .......................... 205 pm6: port m ode regist er 6 ..................................................................................................... .................. 205, 568 pm7: port m ode regist er 7 ..................................................................................................... .......................... 205 pm12: port m ode regist er 12 ................................................................................................... .................. 205, 702 pm14: port m ode regist er 14 ................................................................................................... .......... 205, 407, 523 pr0h: priority specific ation flag r egister 0h ................................................................................. ..................... 648 pr0l: priority specific ation flag r egister 0l ................................................................................. ...................... 648 pr1h: priority specific ation flag r egister 1h ................................................................................. ..................... 648 pr1l: priority specific ation flag r egister 1l ................................................................................. ...................... 648 prm00: prescaler m ode register 00.............................................................................................. ....................... 285 prm01: prescaler mode register 01............................................................................................. ........................ 285 pu0: pull-up resistor option regi ster 0 ....................................................................................... ...................... 215 pu1: pull-up resistor option regi ster 1 ....................................................................................... ...................... 215 pu3: pull-up resistor option regi ster 3 ....................................................................................... ...................... 215 pu4: pull-up resistor option regi ster 4 ....................................................................................... ...................... 215 pu5: pull-up resistor option regi ster 5 ....................................................................................... ...................... 215 pu6: pull-up resistor option regi ster 6 ....................................................................................... ...................... 215 pu7: pull-up resistor option regi ster 7 ....................................................................................... ...................... 215 pu12: pull-up resistor option regi ster 12 ..................................................................................... ...................... 215 pu14: pull-up resistor option regi ster 14 ..................................................................................... ...................... 215 [r] rcm: internal oscill ation mode register ....................................................................................... ..................... 235 resf: reset cont rol flag re gister............................................................................................. .......................... 691 rxb0: receive bu ffer regist er 0............................................................................................... .......................... 435 rxb6: receive bu ffer regist er 6............................................................................................... .......................... 459 rxs0: receive sh ift regist er 0 ................................................................................................ ........................... 435 rxs6: receive sh ift regist er 6 ................................................................................................ ........................... 459 [s] sdr0: remainder data regist er 0 ............................................................................................... ....................... 623 sio10: serial i/o shift regi ster 10 ........................................................................................... ............................ 492 sio11: serial i/o shift regi ster 11 ........................................................................................... ............................ 492 sioa0: serial i/o shift regi ster 0 ............................................................................................ ............................. 515 sotb10: transmit bu ffer regist er 10........................................................................................... ........................... 492 78k0/kx2 appendix c register index r01uh0008ej0401 rev.4.01 943 jul 15, 2010 sotb11: transmit bu ffer regist er 11........................................................................................... ........................... 492 sva0: slave addre ss regist er 0 ................................................................................................. ........................ 553 [t] tcl50: timer clock se lection regi ster 50 ...................................................................................... ...................... 348 tcl51: timer clock se lection regi ster 51 ...................................................................................... ...................... 348 tm00: 16-bit ti mer count er 00................................................................................................. ........................... 272 tm01: 16-bit ti mer count er 01................................................................................................. ........................... 272 tm50: 8-bit ti mer coun ter 50.................................................................................................. ............................ 347 tm51: 8-bit ti mer coun ter 51.................................................................................................. ............................ 347 tmc00: 16-bit timer mo de control r egister 00 .................................................................................. .................... 277 tmc01: 16-bit timer mo de control r egister 01 .................................................................................. .................... 277 tmc50: 8-bit timer mode control re gister 50 ................................................................................... ..................... 351 tmc51: 8-bit timer mode control re gister 51 ................................................................................... ..................... 351 tmcyc1: 8-bit timer h carri er control r egister 1 .............................................................................. ....................... 371 tmhmd0: 8-bit timer h mode regi ster 0 ......................................................................................... ......................... 367 tmhmd1: 8-bit timer h mode regi ster 1 ......................................................................................... ......................... 367 toc00: 16-bit timer out put control re gister 00 ................................................................................ ..................... 282 toc01: 16-bit timer out put control re gister 01 ................................................................................ ..................... 282 txb6: transmit bu ffer register 6.............................................................................................. .......................... 459 txs0: transmit sh ift regist er 0 ............................................................................................... ........................... 435 txs6: transmit shi ft register 6 ................................................................................................ .......................... 459 [w] wdte: watchdog timer enable re gister........................................................................................... ................... 398 wtm: watch timer op eration mode regist er...................................................................................... ................ 391 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 944 jul 15, 2010 appendix d list of cautions this appendix lists cautions described in this document. ?classification (hard/soft)? in table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/30) chapter classification function details of function cautions page av ss make av ss the same potential as v ss . pp. 42, 44 to 47 av ss , ev ss make av ss and ev ss the same potential as v ss . pp. 43, 48 to 50 ev dd make ev dd the same potential as v dd . pp. 43, 48 to 50 regc connect the regc pin to v ss via a capacitor (0.47 to 1 f). pp. 42 to 50 chapter 1 hard pin function ani0/p20 to anin/p2n ani0/p20 to anin/p2n are set in the analog input mode after release of reset. pp. 42 to 50 ani0/p20 to ani7/p27 ani0/p20 to ani7/p27 are set in the analog input mode after release of reset. p. 81 in the product with an on-chip debug function ( pd78f05xxd and 78f05xxda), be sure to pull the p31/intp2/ocd1a pin down before a reset, release to prevent malfunction. p. 82 p31/intp2/ ocd1a process the p31/intp2/ocd1a pin of t he products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programme r or an on-chip debug emulator (see the table on p.83). p. 83 p121/x1/ocd0a process the p121/x1/ocd0a pin of the products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programme r or an on-chip debug emulator (see the table on p.87). p. 87 chapter 2 hard pin function regc pin keep the wiring length as short as possible for the broken-line part in the above figure. p. 90 regardless of the internal memory capacity, the initial values of the internal memory size switching register (ims) and internal expansion ram size switching register (ixs) of all products in the 78k0/kx2 micr ocontrollers are fixed (ims = cfh, ixs = 0ch). therefore, set the value corres ponding to each product as indicated below. p. 96 ims, ixs: internal memory size switching register, internal expansion ram size switching register to set the memory size, set ims and then ixs. set the memory size so that the internal rom and internal expansi on ram areas do not overlap. p. 96 instructions cannot be fetched between different memory banks. p. 113 branch and access cannot be directly exec uted between different memory banks. execute branch or access between differ ent memory banks via the common area. p. 113 allocate interrupt servicing in the common area. p. 113 memory bank an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. p. 113 sfr: special function register do not access addresses to which sfrs are not assigned. p. 116 chapter 3 soft memory space sp: stack pointer since reset si gnal generation makes the sp contents undefined, be sure to initialize the sp before using the stack. p. 126 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 945 jul 15, 2010 (2/30) chapter classification function details of function cautions page bank: memory bank select register be sure to change the value of the bank register in the common area (0000h to 7fffh). if the value of the bank register is c hanged in the bank area (8000h to bfffh), an inadvertent program loop occurs in the cp u. therefore, never change the value of the bank register in the bank area. p. 150 instructions cannot be fetched between different memory banks. p. 151 branching and accessing cannot be directly executed between different memory banks. execute branching or accessing between different memory banks via the common area. p. 151 allocate interrupt servicing in the common area. p. 151 chapter 4 soft memory bank switching function (products whose flash memory is at least 96 kb only) memory bank an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. p. 151 p02/so11, p04/sck11 to use p02/so11 and p04/sck11 as general -purpose ports, set serial operation mode register 11 (csim11) and serial clock selection register 11 (csic11) to the default status (00h). p. 164 p10/sck10/txd0, p12/so10 to use p10/sck10/txd0 and p12/so10 as general-purpose ports, set serial operation mode register 10 (csim10) and serial clock sele ction register 10 (csic10) to the default status (00h) p. 175 soft p13/txd6 to use p13/txd6 as general-purpos e port, clear bit 0 (txdlv6) of synchronous serial interface control register 6 ( asicl6) to 0 (normal output of txd6). p. 175 hard make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. p. 181 soft port 2 for the 38-pin products of 78k0/kc2, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. p. 182 in the product with an on-chip debug function ( pd78f05xxd and 78f05xxda), be sure to pull the p31/intp2/ocd1a pin down before a reset release, to prevent malfunction. p. 183 hard p31/intp2/ ocd1a process the p31/intp2/ocd1a pin of t he products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programme r or an on-chip debug emulator (see the table on p.183). p. 183 soft port 4 for the 38-pin products of 78k0/kc2, be sure to set bits 0 and 1 of pm4 and p4 to ?0?. p. 187 p60, p61 a through current flows through p60 and p61 if an intermediate potential is input to these pins, because the input buffer is also turned on when p60 and p61 are in output mode. consequently, do not input an intermediate potential when p60 and p61 are in output mode. p. 190 hard p62 a through current flows through p62 if an in termediate potential is input to this pin, because the input buffer is also turned on when p62 is in output mode. consequently, do not input an intermediate potential when p62 is in output mode. p. 191 chapter 5 soft port function port 7 for the 38-pin products of 78k0/kc2, be sure to set bits 2 and 3 of pm7 and p7 to ?0?. p. 195 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 946 jul 15, 2010 (3/30) chapter classification function details of function cautions page when using the p121 to p124 pins to connect a resonator for the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an external clock for the main system clock (exclk) or s ubsystem clock (exclks), the x1 oscillation mode, xt1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (oscctl) (f or details, see 6.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin). the reset value of oscctl is 00h (all of the p121 to p124 pins are i/o port pins). at this time, setting of t he pm121 to pm124 and p121 to p124 pins is not necessary. p. 196 p121/x1/ocd0a, p122/x2/exclk/o cd0b, p123/xt1, p124/xt2/exclks process the p121/x1/ocd0a pin of the products mounted with the on-chip debug function ( pd78f05xxd and 78f05xxda) as follows, when it is not used when it is connected to a flash memory programme r or an on-chip debug emulator (see the table on p.197). p. 197 be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm6, bits 3 to 7 of pm12 to 1. (78k0/kb2) p. 205 for the 38-pin products, be sure to set bits 2 to 7 of pm0, bits 6 and 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 4 to 7 of pm7, and bits 5 to 7 of pm12 to ?1?. also, be sure to set bits 0 and 1 of pm4, and bits 2 and 3 of pm7 to ?0?. for the 44-pin products, be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 4 to 7 of pm7, and bits 5 to 7 of pm12 to ?1?. for the 48-pin products, be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 6 and 7 of pm7, bits 5 to 7 of pm12, and bits 1 to 7 of pm14 to ?1?. (78k0/kc2) p. 206 be sure to set bits 4 to 7 of pm0, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 4 to 7 of pm6, bits 5 to 7 of pm12, and bits 1 to 7 of pm14 to 1. (78k0/kd2) p. 207 be sure to set bit 7 of pm0, bits 4 to 7 of pm3, bits 4 to 7 of pm4, bits 4 to 7 of pm5, bits 4 to 7 of pm6, bits 5 to 7 of pm12, and bits 2 to 7 of pm14 to ?1?. (78k0/ke2) p. 208 port mode registers be sure to set bit 7 of pm0, bits 4 to 7 of pm3, bits 5 to 7 of pm12, and bits 6 and 7 of pm14 to ?1?. (78k0/kf2) p. 209 port register (78k0/kc2) for the 38-pin products, be sure to set bits 6 and 7 of p2, bits 0 and 1 of p4, and bits 2 and 3 of p7 to ?0?. p. 211 set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). p. 220 adpc: a/d port configuration register if data is written to adpc, a wait cycle is generated. do not write data to adpc when the peripheral hardware clock is stopped. for details, see chapter 36 cautions for wait. p. 220 chapter 5 soft port function 1-bit manipulation instruction for port register n (pn) when a 1-bit manipulation instruction is ex ecuted on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewrite t he output latch when switching a port from input mode to output mode. p. 224 be sure to set amph to 1 if the high-speed system clock oscillation frequency exceeds 10 mhz. pp. 230, 231 chapter 6 soft clock generator oscctl: clock operation mode select register set amph before setting the main clock mode register (mcm). pp. 230, 231 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 947 jul 15, 2010 (4/30) chapter classification function details of function cautions page set amph before setting the peripheral functions after a reset release. the value of amph can be changed only once after a re set release. when the high-speed system clock (x1 oscillation) is selected as the cpu clock, supply of the cpu clock is stopped for 4.06 to 16.12 s after amph is set to 1. when the high-speed system clock (external clock input) is selected as the cpu clo ck, supply of the cpu clock is stopped for the duration of 160 external clocks after amph is set to 1. pp. 230, 231 if the stop instruction is executed when amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is released when the internal high- speed oscillation clock is selected as the cpu clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the cpu clock. when the high-speed system clock (x1 oscillation) is selected as the cpu clock, the oscillation stabilization time is counted after the stop mode is released. pp. 230, 231 to change the value of exclk and oscsel, be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). pp. 230, 231 oscctl: clock operation mode select register be sure to clear bits 1 to 5 to 0. (78k0/kb2) pp. 230, 231 be sure to clear bits 1 to 3 to 0. (78k0/kc2 to 78k0/kf2) p. 232 be sure to clear bits 3 and 7 to ?0?. (78k0/kc2 to 78k0/kf2) p. 233 the peripheral hardware clock (f prs ) is not divided when the di vision ratio of the pcc is set. pp. 232, 233 pcc: processor clock control register confirm that bit 5 (cls) of the processor cl ock control register (pcc) is 0 (cpu is operating with main system clock) when changing the current values of xtstart, exclks, and oscsels. p. 234 rcm: internal oscillation mode register when setting rstop to 1, be sure to conf irm that the cpu operates with a clock other than the internal high-speed oscillation cl ock. specifically, set under either of the following conditions. <1> 78k0/kb2 ? when mcs = 1 (when cpu operates with the high-speed system clock) <2> 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 ? when mcs = 1 (when cpu operates with the high-speed system clock) ? when cls = 1 (when cpu operates with the subsystem clock) in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting rstop to 1. p. 235 when setting mstop to 1, be sure to conf irm that the cpu operates with a clock other than the high-speed system clock. specifically, set under either of the following conditions. <1> 78k0/kb2 ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) <2> 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2 ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) ? when cls = 1 (when cpu operates with the subsystem clock) in addition, stop peripheral hardware that is operating on the high-speed system clock before setting mstop to 1. p. 236 do not clear mstop to 0 while bit 6 (o scsel) of the clock operation mode select register (oscctl) is 0 (i/o port mode). p. 236 chapter 6 soft clock generator moc: main osc control register the peripheral hardware cannot operate w hen the peripheral hardware clock is stopped. to resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, init ialize the peripheral hardware. p. 236 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 948 jul 15, 2010 (5/30) cha p te r classification function details of f unction cautions page xsel can be changed only once after a reset release. p. 237 soft do not rewrite mcm0 when the cpu clock operates with the subsystem clock. p. 237 hard mcm: main clock mode register a clock other than f prs is supplied to the following per ipheral functions regardless of the setting of xsel and mcm0. ? watchdog timer (operates with internal low-speed oscillation clock) ? when ?f rl ?, ?f rl /2 7 ?, or ?f rl /2 9 ? is selected as the count clock for 8-bit timer h1 (operates with internal low-speed oscillation clock) ? peripheral hardware selects the exte rnal clock as the clock source (except when the external count clock of tm0n (n = 0, 1) is selected (ti00n pin valid edge)) p. 237 after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. p. 238 soft the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p. 238 hard ostc: oscillation stabilization time counter status register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p. 238 to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. p. 239 do not change the value of the osts register during the x1 clock oscillation stabilization time. p. 239 soft the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p. 239 clock generator osts: oscillation stabilization time select register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p. 239 when using the x1 oscillator and xt1 oscillator, wire as follows in the area enclosed by the broken lines in the figures 6-12 and 6-13 to avoi d an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other si gnal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption. p. 241 chapter 6 hard x1/xt1 oscillator ? when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. p. 242 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 949 jul 15, 2010 (6/30) cha p te r classification function details of function cautions page it is not necessary to wait for the oscillation stabilization time when an external clock input from the exclk and exclks pins is used. pp. 246, 247 hard clock generator operation when power supply voltage is turned on ? a voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the power supply voltage reaches 1.59 v (typ.). if the supply voltage rises from 1.59 v (typ.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. p. 247 x1/p121 and x2/exclk/p122 the x1/p121 and x2/exclk/p122 pins are in the i/o port mode after a reset release. p. 248 do not change the value of exclk and oscsel while the x1 clock is operating. p. 249 x1 clock set the x1 clock after the supply voltage has reached the operable voltage of the clock to be used (see chapter 30 electrical specifications (standard products) to chapter 33 electr ical specifications ((a2) grade products : t a = ? 40 to +125 c)). p. 249 do not change the value of exclk and oscsel while the external main systerm clock is operating. p. 249 external main system clock set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see chapter 30 electrical specifications (standard products) to chapter 33 electrical specifications ((a2) grade products : t a = ? 40 to +125 c)). p. 249 main system clock if the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. p. 250 high-speed system clock be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. p. 251 internal high- speed oscillation clock be sure to confirm that mcs = 1 or cls = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operati ng on the internal high-speed oscillation clock. p. 253 xt1/p123, xt2/exclks/ p124 the xt1/p123 and xt2/exclks/p124 pins are in the i/o port mode after a reset release. p. 254 external clock from peripheral hardware pins do not start the peripheral hardware operation with the external cl ock from peripheral hardware pins when the internal high- speed oscillation clock and high-speed system clock are stopped while the cpu operates with the subsystem clock, or when in the stop mode. p. 254 xt1 clock, external subsystem clock do not change the value of xtstart, exclks, and oscsels while the subsystem clock is operating. p. 254 be sure to confirm that cls = 0 when clearing oscsels to 0. in addition, stop the watch timer if it is operating on the subsystem clock. p. 255 controlling high-speed system clock subsystem clock the subsystem clock oscillation cannot be stopped using the stop instruction. p. 255 chapter 6 soft controlling internal low- speed oscillation clock internal low- speed oscillation clock if ?internal low-speed oscillator cannot be stopped? is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. p. 256 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 950 jul 15, 2010 (7/30) cha p te r classification function details of function cautions page set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 30 electrical specifications (standard products) to chapter 33 electr ical specifications ((a2) grade products : t a = ? 40 to +125 c)). pp. 260, 261, 263 selection of the main system clock cycl e division factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the main system clock cycle division factor (pcc0 to pcc2) and sw itchover from the subsystem clock to the main system clock (changing css from 1 to 0). p. 266 when switching the internal high-speed o scillation clock to the high-speed system clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be changed only once after a reset release. p. 267 chapter 6 soft cpu clock ? do not rewrite mcm0 when the cpu clock operates with the subsystem clock. p. 267 hard the valid edge of ti010 and timer output (to00) cannot be used for the p01 pin at the same time, and the valid edge of ti011 and timer output (to01) cannot be used for the p06 pin at the same time. select either of the functions. p. 272 if clearing of bits 3 and 2 (tmc0n3 and tm c0n2) of 16-bit timer mode control register 0n (tmc0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. p. 272 ? to change the mode from the capture mode to the comparison mode, first clear the tmc0n3 and tmc0n2 bits to 00, and then change the setting. a value that has been once captured remains stored in cr00n unless the device is reset. if the mode has been changed to the comparison mode, be sure to set a comparison value. p. 272 tm0n: 16-bit timer counter 0n even if tm0n is read, the value is not captured by cr01n. p. 273 cr00n does not perform the capture operati on when it is set in the comparison mode, even if a capture tr igger is input to it. p. 274 cr01n does not perform the capture operati on when it is set in the comparison mode, even if a capture tr igger is input to it. p. 274 cr00n, cr01n: 16-bit timer capture/compare registers 00n, 01n to capture the count value of the tm0n regi ster to the cr00n register by using the phase reverse to that input to the ti00n pin, the interrupt request signal (inttm00n) is not generated after the val ue has been captured. if the valid edge is detected on the ti01n pin during this oper ation, the capture operation is not performed but the inttm00n signal is generated as an external interrupt signal. to not use the external interrupt, mask the inttm00n signal. p. 276 soft tmc0n: 16-bit timer mode control register 0n 16-bit timer/event counter 0n starts oper ation at the moment tmc0n2 and tmc0n3 are set to values other than 00 (operati on stop mode), respectively. set tmc0n2 and tmc0n3 to 00 to stop the operation. p. 277 hard crc0n: capture/ compare control register 0n to ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 0n (prm0n). pp. 280, 281 chapter 7 soft 16-bit timer/event counters 00, 01 toc0n: 16-bit timer output control register 0n be sure to set toc0n using the following procedure. <1> set toc0n4 and toc0n1 to 1. <2> set only toe0n to 1. <3> set either of lvs0n or lvr0n to 1. p. 282 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 951 jul 15, 2010 (8/30) cha p te r classification function details of function cautions page do not apply the following setting when setting the prm0n1 and prm0n0 bits to 11 (to specify the valid edge of the ti00n pin as a count clock). ? clear & start mode entered by the ti00n pin valid edge ? setting the ti00n pin as a capture trigger p. 285 soft if the operation of the 16-bit timer/event counter 0n is enabled when the ti00n or ti01n pin is at high level and when the valid edge of the ti00n or ti01n pin is specified to be the rising edge or both edges, the high level of the ti00n or ti01n pin is detected as a rising edge. note th is when the ti00n or ti01n pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. p. 285 hard prm0n: prescaler mode register 0n the valid edge of ti010 and timer output (to00) cannot be used for the p01 pin at the same time, and the valid edge of ti011 and timer output (to01) cannot be used for the p06 pin at the same time. select either of the functions. p. 285 clear & start mode entered by ti00n pin valid edge input do not set the count clock as the valid edge of the ti00n pin (prm0n1 and prm0n0 = 11). when prm0n1 and prm0n0 = 11, tm0n may be cleared. p. 299 to change the duty factor (value of cr01n) during operation, see 7.5.1 rewriting cr01n during tm0n operation. p. 321 ppg output set values to cr00n and cr01n such that the condition 0000h cr01n < cr00n ffffh is satisfied. p. 323 do not input the trigger again (setting o spt0n to 1 or detecting the valid edge of the ti00n pin) while the one-shot pulse is output. to output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. p. 325 to use only the setting of ospt0n to 1 as the trigger of one-shot pulse output, do not change the level of the ti00n pin or its alternate function port pin. otherwise, the pulse will be unexpectedly output. p. 325 one-shot pulse output do not set the same value to cr00n and cr01n. p. 327 lvs0n, lvrn0 be sure to set lvs0n and lvr0n following steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. p. 339 soft ? table 7-3 shows the restrictions for each channel. p. 340 hard timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because counting tm0n is started asynchronously to the count pulse. p. 340 set a value other than 0000h to cr00n and cr01n in clear & start mode entered upon a match between tm0n and cr00n (tm0n cannot count one pulse when it is used as an external event counter). p. 340 when the valid edge is input to the ti00n/ti01n pin and the reverse phase of the ti00n pin is detected while cr00n/cr01n is read, cr01n performs a capture operation but the read value of cr00n/cr01n is not guaranteed. at this time, an interrupt signal (inttm00n/inttm01n) is generated when the valid edge of the ti00n/ti01n pin is detected (the interrupt signal is not generated when the reverse- phase edge of the ti00n pin is detected). when the count value is captured becaus e the valid edge of the ti00n/ti01n pin was detected, read the value of cr00n/cr01n after inttm00n/inttm01n is generated. p. 341 chapter 7 soft 16-bit timer/event counters 00, 01 cr00n, cr01n: 16-bit timer capture/compare registers 00n, 01n the values of cr00n and cr01n are not guaranteed after 16-bit timer/event counter 0n stops. p. 341 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 952 jul 15, 2010 (9/30) chapter classification function details of function cautions page es0n0, es0n1 set the valid edge of the ti00n pin while the timer operation is stopped (tmc0n3 and tmc0n2 = 00). set the valid edge by using es0n0 and es0n1. p. 341 re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. be sure to input the next trigger after the current active level is output. p. 341 the ovf0n flag is set to 1 in the followi ng case, as well as when tm0n overflows. select the clear & start mode entered upon a match between tm0n and cr00n. set cr00n to ffffh. when tm0n matches cr00n and tm0n is cleared from ffffh to 0000h p. 342 ovf0n even if the ovf0n flag is cleared to 0 a fter tm0n overflows and before the next count clock is counted (before the value of tm 0n becomes 0001h), it is set to 1 again and clearing is invalid. p. 342 one-shot pulse output one-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the ti00n pin va lid edge. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm0n and cr00n. p. 342 soft ti00n when the valid edge of ti00n is specified as the count clock, the capture register for which ti00n is specified as a tr igger does not operate correctly. p. 343 ti00n, ti01n to accurately capture the count val ue, the pulse input to the ti00n and ti01n pins as a capture trigger must be wider than two count clocks selected by prm0n (see figure 7-9). p. 343 hard inttm00n, inttm01n the capture operation is performed at the falling edge of the count clock but the interrupt signals (inttm00n and inttm01n) are generated at the rising edge of the next count clock (see figure 7-9). p. 343 soft crc0n1 = 1 when the count value of the tm0n regist er is captured to the cr00n register in the phase reverse to the signal input to the ti 00n pin, the interrupt signal (inttm00n) is not generated after the count value is capt ured. if the valid edge is detected on the ti01n pin during this operation, the capt ure operation is not performed but the inttm00n signal is generated as an external interrupt signal. mask the inttm00n signal when the external interrupt is not used. p. 343 specifying valid edge after reset if the operation of the 16-bit timer/event counter 0n is enabled after reset and while the ti00n or ti01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti00n or ti01n pin, then the high level of the ti00n or ti01n pin is detected as the rising edge. note this when the ti00n or ti01n pin is pulled up. however, the rising edge is not detected when the operation is once stopped and then enabled again. p. 343 sampling clock for eliminating noise the sampling clock for eliminating noise differs depending on whether the valid edge of ti00n is used as the count clock or c apture trigger. in the former case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm0n is used for sampling. when the signal input to the ti00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 7-9). p. 343 ti00n/ti01n the signal input to the ti00n/ti01n pi n is not acknowledged while the timer is stopped, regardless of the operation mode of the cpu. p. 343 chapter 7 hard 16-bit timer/event counters 00, 01 reading of tm0n tm0n can be read without stopping t he actual counter, becaus e the count values captured to the buffer are fixed when it is read. the buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. p. 344 in the mode in which clear & start occurs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. p. 347 chapter 8 soft 8-bit timer/event counters 50, 51 cr5n: 8-bit timer compare register 5n in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. p. 347 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 953 jul 15, 2010 (10/30) chapter classification function details of f unction cautions page when rewriting tcl50 to other data, stop the timer operation beforehand. p. 349 tcl50: timer clock selection register 50 be sure to clear bits 3 to 7 to ?0?. p. 349 when rewriting tcl51 to other data, stop the timer operation beforehand. p. 350 tcl51: timer clock selection register 51 be sure to clear bits 3 to 7 to ?0?. p. 350 the settings of lvs5n and lvr5n are valid in other than pwm mode. p. 352 perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6: operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n p. 352 when tce5n = 1, setting the other bits of tmc5n is prohibited. p. 352 tmc5n: 8-bit timer mode control register 5n (tmc5n) the actual to50/ti50/p17 and to51/ti51/p33/intp4 pin outputs are determined depending on pm17 and p17, and pm33 and p33, besides to5n output. p. 352 interval timer do not write other values to cr5n during operation. p. 354 square-wave output do not write other values to cr5n during operation. p. 357 in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. p. 358 pwm output when reading from cr5n between <1> and <2> in figure 8-15, the value read differs from the actual value (read va lue: m, actual value of cr5n: n). p. 361 timer start error an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm51) are started asynchronously to the count clock. p. 362 chapter 8 soft 8-bit timer/event counters 50, 51 reading of tm5n tm5n can be read without stopping t he actual counter, becaus e the count values captured to the buffer are fixed when it is read. the buffer, however, may not be updated when it is read immediately befor e the counter counts up, because the buffer is updated at the timing the counter counts up. p. 362 cmp0n: 8-bit timer h comparer register 0n (cmp0n) cmp0n cannot be rewritten during time r count operation. cmp0n can be refreshed (the same value is writt en) during timer count operation. p. 366 cmp1n: 8-bit timer h compare register 1n (cmp1n) in the pwm output mode and carrier generator mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to cmp1n). p. 366 when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. however, tmhmd0 can be refreshed (the same value is written). p. 369 in the pwm output mode, be sure to set the 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). p. 369 tmhmd0: 8-bit timer h mode register 0 the actual toh0/p15 pin output is determined depending on pm15 and p15, besides toh0 output. p. 369 when tmhe1 = 1, setting the other bits of tmhmd1 is prohibited. however, tmhmd1 can be refreshed (the same value is written). p. 371 in the pwm output mode and carrier generator mode, be sure to set the 8-bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). p. 371 when the carrier generator mode is used, se t so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. p. 371 chapter 9 soft 8-bit timers h0, h1 tmhmd1: 8-bit timer h mode register 1 the actual toh1/intp5/p16 pin output is determined depending on pm16 and p16, besides toh1 output. p. 371 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 954 jul 15, 2010 (11/30) chapter classification function details of function cautions page soft tmcyc1: 8-bit timer h carrier register 1 do not rewrite rmc1 when tmhe = 1. however, tmcyc1 can be refreshed (the same value is written). p. 371 hard the set value of the cmp1n register can be changed while the timer counter is operating. however, this takes a duration of three operating clocks (signal selected by the cksn2 to cksn0 bits of the tmhmdn r egister) from when the value of the cmp1n register is changed until the value is transferred to the register. p. 377 be sure to set the cmp1n register when st arting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). p. 377 pwm output make sure that the cmp1n register setti ng value (m) and cmp0n r egister setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh p. 377 do not rewrite the nrzb1 bit again until at least the second clock after it has been rewritten, or else the transfer from the nrzb1 bit to the nrz1 bit is not guaranteed. p. 383 when the 8-bit timer/event count er 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when the 8-bit timer/event count er 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. p. 383 be sure to set the cmp11 register when st arting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). p. 385 set so that the count clock frequency of tm h1 becomes more than 6 times the count clock frequency of tm51. p. 385 set the values of the cmp01 and cmp11 registers in a range of 01h to ffh. p. 385 the set value of the cmp11 register can be changed while the timer counter is operating. however, it takes the duration of three operating clocks (signal selected by the cks12 to cks10 bits of the tmhmd1 register) since the value of the cmp11 register has been changed until the value is transferred to the register. p. 385 chapter 9 soft 8-bit timers h0, h1 carrier generator (8-bit timer h1 only) be sure to set the rmc1 bit before the count operation is started. p. 385 soft wtm: watch timer operation mode register do not change the count clock and interval time (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. p. 393 chapter 10 hard watch timer interrupt request when operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the interval until the first interrupt request signal (intwt) is generated after the register is set does not exactly match t he specification made with bits 2 and 3 (wtm2, wtm3) of wtm. subsequently, however, the intwt signal is generated at the specified intervals. p. 395 if a value other than ach is written to wdte , an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. p. 398 if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. p. 398 wdte: watchdog timer enable register the value read from wdte is 9ah/1ah (this di ffers from the written value (ach)). p. 398 the first writing to wdte after a reset rel ease clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. p. 399 chapter 11 soft watchdog timer operation control if the watchdog timer is cleared by writing ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. p. 399 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 955 jul 15, 2010 (12/30) chapter classification function details of function cautions page the watchdog timer can be cleared immediat ely before the count value overflows (ffffh). p. 399 operation control the operation of the watchdog timer in the halt and stop modes differs as follows depending on the set value of bit 0 (l srosc) of the option byte (see table on p. 402). if lsrosc = 0, the watchdog timer resumes counting after the halt or stop mode is released. at this time, the count er is not cleared to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed oscillator is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. p. 400 the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. pp. 400, 401 setting overflow time of watchdog timer, setting window open period of watchdog time the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. pp. 400, 401 setting window1 = window0 = 0 is pr ohibited when using the watchdog timer at 1.8 v v dd < 2.7 v. p. 401 chapter 11 soft watchdog timer setting window open period of watchdog timer the first writing to wdte after a reset re lease clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. p. 401 set ccs3 to ccs0 while the clock output operation is stopped (cloe = 0). pp. 405, 407 chapter 12 soft clock output/ buzzer output controller cks: clock output select register set bcs1 and bcs0 when the buzzer output operation is stopped (bzoe = 0). p. 407 adcr: 10-bit a/d conversion register, adcrh: 8-bit a/d conversion register when data is read from adcr and adcrh, a wait cycle is generated. do not read data from adcr and adcrh when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 411 a/d conversion must be stopped before rewriting bits fr0 to fr2, lv1, and lv0 to values other than the identical data. p. 413 adm: a/d converter mode register if data is written to adm, a wait cycle is generated. do not write data to adm when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 413 set the conversion times wi th the following conditions. (see pp.414, 415) pp. 414, 415 when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. pp. 414, 415 change lv0 from the default value, when 2.3 v av ref < 2.7 v. pp. 414, 415 a/d conversion timer selection the above conversion time does not in clude clock frequency errors. select conversion time, taking clock frequen cy errors into consideration. pp. 414, 415 when writing to the a/d converter m ode register (adm), analog input channel specification register (ads), and a/d por t configuration register (adpc), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to ad m, ads, and adpc. using timing other than the above may cause an incorrect conversion result to be read. p. 416 chapter 13 soft a/d converter adcr: 10-bit a/d conversion register if data is read from adcr, a wait cycle is generated. do not read data from adcr when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 416 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 956 jul 15, 2010 (13/30) chapter classification function details of function cautions page when writing to the a/d converter m ode register (adm), analog input channel specification register (ads), and a/d port c onfiguration register (adpc), the contents of adcrh may become undefined. read the conversion result following conversion completion before writing to adm, ads, and adpc. using timing other than the above may cause an incorrect conversion result to be read. p. 417 adcrh: 8-bit a/d conversion register if data is read from adcrh, a wait cycle is generated. do not read data from adcrh when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 417 be sure to clear bits 3 to 7 to ?0?. p. 418 ads: analog input channel specification register if data is written to ads, a wait cycle is generated. do not write data to ads when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 418 ads: analog input channel specification register, adpc: a/d port configuration register (adpc) set a channel to be used for a/d conversi on in the input mode by using port mode register 2 (pm2). pp. 418, 419 adpc: a/d port configuration register (adpc) if data is written to adpc, a wait cycle is generated. do not write data to adpc when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 419 port mode register 2 (pm2) for the 38-pin products of 78k0/kc2, be sure to set bits 6 and 7 of pm2 to ?1?, and bits 6 and 7 of p2 to ?0?. p. 420 basic operations of a/d converter make sure the period of <1> to <5> is 1 s or more. p. 421 make sure the period of <1> to <5> is 1 s or more. p. 425 <1> may be done between <2> and <4>. p. 425 <1> can be omitted. however, ignore data of the first conversion after <5> in this case. p. 425 a/d conversion operation the period from <6> to <9> differs from t he conversion time set using bits 5 to 1 (fr2 to fr0, lv1, lv0) of adm. the per iod from <8> to <9> is the conversion time set using fr2 to fr0, lv1, and lv0. p. 425 soft operating current in stop mode the a/d converter stops operating in the st op mode. at this time, the operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag regist er 1l (if1l) to 0 and start operation. p. 428 hard input range of ani0 to ani7 observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of abs olute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of t he other channels may also be affected. p. 428 if conflict occurs between a/d conversion result register (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion, adcr or adcrh read has priority. after the read operation, the new conversion result is written to adcr or adcrh. p. 428 chapter 13 soft a/d converter conflicting operations if conflict occurs between adcr or adcrh write and a/d converter mode register (adm) write, analog input channel specific ation register (ads), or a/d port configuration register (adpc) write upon t he end of conversion, adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. p. 428 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 957 jul 15, 2010 (14/30) chapter classification function details of f unction cautions page noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani7. ? connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. ? the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as show n in figure 13-20 is recommended. ? do not switch these pins with other pins during conversion. ? the accuracy is improved if the halt m ode is set immediately after the start of conversion. p. 428 the analog input pins (ani0 to ani7) are al so used as input port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not access p20 to p27 while conversion is in progre ss; otherwise the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27 starting with the ani0/p20 that is the furthest from av ref . p. 429 ani0/p20 to ani7/p27 if a digital pulse is applied to the pins adj acent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. p. 429 input impedance of ani0 to ani7 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flow s during sampling. consequently, the input impedance fluctuates depending on whether sa mpling is in progress, and on the other states. to make sure that sampling is effectiv e, however, it is recommended to keep the output impedance of the analog input source to within 10 k , and to connect a capacitor of about 100 pf to the ani0 to ani7 pins (see figure 13-20). p. 429 hard av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. p. 429 interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads ) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conver sion result and adif for the pre-change analog input may be set just before the ads rewrite. caution is therefore required since, at this time, when adif is read imm ediately after the ads rewrite, adif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then re sumed, clear adif before the a/d conversion operation is resumed. p. 430 conversion results just after a/d conversion start the first a/d conversion val ue immediately after a/d conversion starts may not fall within the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if the adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. p. 430 a/d conversion result register (adcr, adcrh) read operation when a write operation is performed to t he a/d converter mode register (adm), analog input channel specificati on register (ads), and a/d port configuration register (adpc), the contents of adcr and adcrh may become undefined. read the conversion result following conversion comp letion before writing to adm, ads, and adpc. using a timing other than the above may cause an incorrect conversion result to be read. p. 430 chapter 13 soft a/d converter internal equivalent circuit the equivalent circuit of the analog input bl ock is shown below. (see figure 13-22) p. 431 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 958 jul 15, 2010 (15/30) chapter classification function details of function cautions page if clock supply to serial in terface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and holds t he value immediately before clock supply was stopped. the t x d0 pin also holds t he value immediately before clock supply was stopped and outputs i t. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power0 = 0, rxe0 = 0, and txe0 = 0. p. 432 set power0 = 1 and then set txe0 = 1 (tr ansmission) or rxe0 = 1 (reception) to start communication. p. 432 txe0 and rxe0 are synchronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. p. 432 uart mode set transmit data to txs0 at least one base clock (f xclk0 ) after setting txe0 = 1. pp. 432, 435 txs0: transmit shift register 0 do not write the next transmit data to txs0 before the transmission completion interrupt signal (intst0) is generated. p. 435 to start the transmission, set power0 to 1 and then set txe0 to 1. to stop the transmission, clear txe0 to 0, and then clear power0 to 0. p. 437 to start the reception, set power0 to 1 and then set rxe0 to 1. to stop the reception, clear rxe0 to 0, and then clear power0 to 0. p. 437 set power0 to 1 and then set rxe0 to 1 while a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 while a low level is input, reception is started. p. 437 txe0 and rxe0 are synchronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. p. 437 set transmit data to txs0 at least one base clock (f xclk0 ) after setting txe0 = 1. p. 437 clear the txe0 and rxe0 bits to 0 before re writing the ps01, ps00, and cl0 bits. p. 437 make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. p. 437 asim0: asynchronous serial interface operation mode register 0 be sure to set bit 0 to 1. p. 437 the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial inte rface operation mode register 0 (asim0) p. 438 only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p. 438 if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. p. 438 asis0: asynchronous serial interface reception error status register 0 if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 438 make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. p. 440 soft make sure that bit 7 (power0) of the asim0 register = 0 when rewriting the tps01 and tps00 bits. p. 440 chapter 14 hard serial interface uart0 brgc0: baud rate generator control register 0 the baud rate value is the output clock of the 5-bit counter divided by 2. p. 440 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 959 jul 15, 2010 (16/30) chapter classification function details of function cautions page power0, txe0, rxe0: bits 7, 6, 5 of asim0 clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the communication, set power0 to 1, and then set txe0 or rxe0 to 1. p. 441 uart mode take relationship with the other party of communication when setting the port mode register and port register. p. 442 uart transmission after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. p. 445 if a reception error occurs, read asynchronous serial interface reception error status register 0 (asis0) and then read receive buffer register 0 (rxb0) to clear the error flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p. 446 uart reception reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. p. 446 keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 450 error of baud rate make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. p. 450 chapter 14 soft serial interface uart0 permissible baud rate range during reception make sure that the baud rate error during reception is within the permissible error range, by using the calculat ion expression shown below. p. 451 the t x d6 output inversion function invert s only the transmission side and not the reception side. to use this function, the reception side must be ready for reception of inverted data. p. 453 if clock supply to serial in terface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and holds t he value immediately before clock supply was stopped. the t x d6 pin also holds t he value immediately before clock supply was stopped and outputs i t. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. p. 453 set power6 = 1 and then set txe6 = 1 (tr ansmission) or rxe6 = 1 (reception) to start communication. p. 453 txe6 and rxe6 are synchronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or rxe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. p. 453 set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. p. 453 uart mode if data is continuously transmitted, the communication ti ming from the stop bit to the next start bit is extended two operating clocks of the macro. however, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. do not use the continuous tr ansmission function if the interface is used in lin communication operation. p. 453 do not write data to txb6 when bit 1 (t xbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. p. 459 do not refresh (write the same value to ) txb6 by software during a communication operation (when bits 7 and 6 (power6, txe6 ) of asynchronous serial interface operation mode register 6 (asim6) are 1 or when bits 7 and 5 (power6, rxe6) of asim6 are 1). p. 459 chapter 15 soft serial interface uart6 txb6: transmit buffer register 6 set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. p. 459 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 960 jul 15, 2010 (17/30) chapter classification function details of function cautions page to start the transmission, set power6 to 1 and then set txe6 to 1. to stop the transmission, clear txe6 to 0, and then clear power6 to 0. p. 461 to start the reception, set power6 to 1 and then set rxe6 to 1. to stop the reception, clear rxe6 to 0, and then clear power6 to 0. p. 461 set power6 to 1 and then set rxe6 to 1 while a high level is input to the r x d6 pin. if power6 is set to 1 and rxe6 is set to 1 while a low level is input, reception is started. p. 461 txe6 and rxe6 are synchronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or rxe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. p. 461 set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. p. 461 clear the txe6 and rxe6 bits to 0 before re writing the ps61, ps60, and cl6 bits. p. 461 fix the ps61 and ps60 bits to 0 when used in lin communication operation. p. 461 clear txe6 to 0 before rewriting the sl6 bi t. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. p. 461 asim6: asynchronous serial interface operation mode register 6 make sure that rxe6 = 0 when rewriting the isrm6 bit. p. 461 the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interf ace operation mode register 6 (asim6). p. 462 for the stop bit of the receive data, only t he first bit is checked regardless of the number of stop bits. p. 462 if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. p. 462 asis6: asynchronous serial interface reception error status register 6 if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 462 to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the tr ansmit data cannot be guaranteed. p. 463 asif6: asynchronous serial interface transmission status register 6 to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0? a fter generation of the transmission completion interrupt, and then execute initialization. if initialization is exec uted while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p. 463 cksr6: clock selection register 6 make sure power6 = 0 when rewriting tps63 to tps60. p. 465 soft make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. p. 465 hard brgc6: baud rate generator control register 6 the baud rate is the output clock of the 8-bit counter divided by 2. p. 465 asicl6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (pow er6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). however, do not set both sbrt6 and sbtt6 to 1 by a refresh operation during sbf re ception (sbrt6 = 1) or sbf transmission (until intst6 occurs since sbtt6 has been set (1)), because it may re-trigger sbf reception or sbf transmission. p. 466 in the case of an sbf reception error, the mode returns to the sbf reception mode. the status of the sbrf6 flag is held (1). p. 467 chapter 15 soft serial interface uart6 asicl6: asynchronous serial interface control register 6 before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. after setting the sbrt6 bit to 1, do not clear it to 0 before sbf reception is completed (before an interrupt request signal is generated). p. 467 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 961 jul 15, 2010 (18/30) chapter classification function details of f unction cautions page the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. p. 467 before setting the sbtt6 bit to 1, make su re that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. after setting the sbtt6 bit to 1, do not clear it to 0 before sbf transmission is completed (before an interrupt request signal is generated). p. 467 the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission p. 467 do not set the sbrt6 bit to 1 during reception, and do not set the sbtt6 bit to 1 during transmission. p. 467 when the txdlv6 bit is set to 1 (inver ted txd6 output), the txd6/scla0/p60 pin cannot be used as a general-pur pose port, regardless of the settings of power6 and txe6. when using the txd6/scla0/p60 pi n as a general-purpose port, clear the txdlv6 bit to 0 (normal txd6 output). p. 467 asicl6: asynchronous serial interface control register 6 before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0. p. 467 power6, txe6, rxe6: bits 7, 6, 5 of asim6 clear power6 to 0 after clearing txe6 and rxe6 to 0 to stop the operation. to start the communication, set power6 to 1, and then set txe6 or rxe6 to 1. p. 469 uart mode take relationship with the other party of communication when setting the port mode register and port register. p. 470 parity types and operation fix the ps61 and ps60 bits to 0 when t he device is used in lin communication operation. p. 473 the txbf6 and txsf6 flags of the asif6 r egister change from ?10? to ?11?, and to ?01? during continuous transmission. to c heck the status, therefore, do not use a combination of the txbf6 and txsf6 flags for judgment. read only the txbf6 flag when executing cont inuous transmission. p. 475 when the device is use in lin communica tion operation, the continuous transmission function cannot be used. make sure that asynchronous serial interface transmission status register 6 (asif6) is 00h before writ ing transmit data to transmit buffer register 6 (txb6). p. 475 to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf 6 flag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if dat a is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. p. 475 to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initializat ion. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p. 475 continuous transmission during continuous transmission, the nex t transmission may complete before execution of intst6 interrupt servicing after transmission of one data frame. as a countermeasure, detection c an be performed by developing a program that can count the number of transmit data and by referencing the txsf6 flag. p. 475 if a reception error occurs, read asis6 and then rxb6 to clear the error flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p. 479 reception is always performed with the ?num ber of stop bits = 1?. the second stop bit is ignored. p. 479 normal reception be sure to read asynchronous serial inte rface reception error status register 6 (asis6) before reading rxb6. p. 479 keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 486 error of baud rate make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. p. 486 chapter 15 soft serial interface uart6 permissible baud rate range during reception make sure that the baud rate error during reception is within the permissible error range, by using the calculat ion expression shown below. p. 487 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 962 jul 15, 2010 (19/30) chapter classification function details of f unction cautions page do not access sotb1n when csot1n = 1 ( during serial communication). p. 492 sotb1n: transmit buffer register 1n in the slave mode, transmission/recepti on is started when data is written to sotb11 with a low level input to the ssi11 pin. for details on the transmission/reception operation, see 16.4.2 (2) communication operation. p. 492 csim10: serial operation mode register 10 be sure to clear bit 5 to 0. p. 493 do not write to csic10 while csie10 = 1 (operation enabled). p. 496 to use p10/sck10/t x d0 and p12/so10 as general-pur pose ports, set csic10 in the default status (00h). p. 496 csic10: serial clock selection register 10 the phase type of the data clock is type 1 after reset. p. 496 do not write to csic11 while csie11 = 1 (operation enabled). p. 498 to use p02/so11 and p04/sck11 as gener al-purpose ports, set csic11 in the default status (00h). p. 498 csic11: serial clock selection register 11 the phase type of the data clock is type 1 after reset. p. 498 3-wire serial i/o mode take rela tionship with the other party of communication when setting the port mode register and port register. p. 500 do not access the control register and data register when csot1n = 1 (during serial communication). p. 503 communication operation when using serial interface csi11, wait fo r the duration of at least one clock before the clock operation is started to change the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. p. 503 chapter 16 soft serial interface csi10, csi11 so1n output if a value is written to csie1n, trmd1n, dap1n, and dir1n, the output value of so1n changes. p. 511 a communication operation is started by writing to sioa0. consequently, when transmission is disabled (bit 3 (txea0) of csima0 = 0), write dummy data to the sioa0 register to start the communica tion operation, and then perform a receive operation. p. 515 sioa0: serial i/o shift register 0 do not write data to sioa0 while the automatic transmit/rec eive function is operating. p. 515 when csiae0 = 0, the buffer ram cannot be accessed. p. 516 when csiae0 is changed from 1 to 0, t he registers and bits mentioned in note above are asynchronously initialized. to se t csiae0 = 1 again, be sure to re-set the initialized registers. p. 516 csima0: serial operation mode specification register 0 when csiae0 is re-set to 1 after csi ae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained. p. 516 be sure to clear bit 7 to 0. p. 517 csis0: serial status register 0 during transfer (tsf0 = 1), rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0 ), divisor selection register 0 (brgca0), automatic data transfer address point specif ication register 0 (adtp0), automatic data transfer interval specific ation register 0 (adti0), and serial i/o shift register 0 (sioa0) are prohibited. however, these registers can be read and re-written to the same value. in addition, the buffe r ram can be rewritten during transfer. p. 518 even if atstp0 or atsta0 is set to 1, automatic transfer cannot be started/stopped until 1-byte transfer is complete. p. 519 atstp0 and atsta0 change to 0 automatica lly after the interrupt signal intacsi is generated. p. 519 chapter 17 soft serial interface csia0 csit0: serial trigger register 0 after automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfe r address count register 0 (adtc0). however, since no function to restart autom atic data transfer is incorporated, when transfer is stopped by setting atstp0 = 1, start automatic data transfer by setting atsta0 to 1 after re-setting the registers. p. 519 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 963 jul 15, 2010 (20/30) chapter classification function details of f unction cautions page adtp0: automatic data transfer address point specification register 0 be sure to clear bits 7 to 5 to ?0?. p. 521 adti0: automatic data transfer interval specification register 0 because the setting of bit 5 (stbe0) and bit 4 (busye0) of serial status register 0 (csis0) takes priority over the adti0 se tting, the interval time based on the setting of stbe0 and busye0 is generated even when adti0 is cleared to 00h. p. 522 3-wire serial i/o mode take rela tionship with the other party of communication when setting the port mode register and port register. p. 525 1-byte transmission/ reception the soa0 pin becomes low level by an sioa0 write. p. 527 communication start if csiae0 is set to 1 after data is written to sioa0, communication does not start. p. 529 a wait state may be generated when data is written to the buffer ram. for details, see chapter 36 cautions for wait. p. 530 3-wire serial i/o mode with automatic transmit/receive function take the relationship with the other co mmunicating party into consideration when setting the port mode register and port register. p. 532 because, in the automatic transmi ssion/reception mode, the automatic transmit/receive function writ es/reads data to/from the internal buffer ram after 1- byte transmission/reception, an in terval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specificati on register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (5) automatic transmit/receive interval time). p. 534 automatic transmission/ reception mode if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the interval time specified by automatic data transfer in terval specification regist er 0 (adti0) may be extended. p. 534 because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer ram after 1-byte transmission, an interval is inserted until the next transmissi on. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (a dti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (5) automatic transmit/recei ve interval time). p. 539 automatic transmission if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the interval time specified by automatic data transfer in terval specification regist er 0 (adti0) may be extended. p. 539 because, in the repeat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the inte rval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon automatic data transfer interval specification register 0 (adti0) and t he set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csi s0) (see (5) automatic transmit/receive interval time). p. 541 chapter 17 soft serial interface csia0 repeat transmission mode if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the interval time specified by automatic data transfer in terval specification regist er 0 (adti0) may be extended. p. 541 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 964 jul 15, 2010 (21/30) chapter classification function details of f unction cautions page if the halt instruction is executed dur ing automatic transmission/reception, communication is suspended and the halt mode is set if during 8-bit data communication. when the halt mode is cleared, automatic transmission/reception is restarted from the suspended point. p. 544 automatic transmission/ reception suspension and restart when suspending automatic transmission/re ception, do not change the operating mode to 3-wire serial i/o mode while tsf0 = 1. p. 544 busy control option busy control cannot be used simultaneous ly with the interval time control function of automatic data transfer interval s pecification register 0 (adti0). p. 545 chapter 17 soft serial interface csia0 busy & strobe control option when tsf0 is cleared, the soa0 pin goes low. p. 547 ? do not use serial interface iic0 and t he multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface iic0 and the multiplier/divider. p. 550 do not write data to iic0 during data transfer. p. 553 write or read iic0 only during the wait per iod. accessing iic0 in a communication state other than during the wait period is pr ohibited. when the device serves as the master, however, iic0 can be written only once after the communication trigger bit (stt0) is set to 1. p. 553 iic0: iic shift register 0 when communication is reserved, write data to the iic0 register after the interrupt triggered by a stop condition is detected. p. 553 if the operation of i 2 c is enabled (iice0 = 1) when the scl0 line is high level, the sda0 line is low level, and the digital filter is turned on (dfc0 of the iiccl0 register = 1), a start condition will be inadvertently detected immediately. in this case, set (1) the lrel0 bit by using a 1-bit memory m anipulation instructi on immediately after enabling operation of i 2 c (iice0 = 1). p. 557 iicc0: iic control register 0 when bit 3 (trc0) of the iic status regist er 0 (iics0) is set to 1 (transmission status), bit 5 (wrel0) of the iicc0 regist er is set to 1 during the ninth clock and wait is canceled, after which the trc0 bit is cleared (reception status) and the sdaa0 line is set to high impedance. rel ease the wait performed while the trc bit is 1 (transmission status) by writ ing to the iic shift register. p. 560 iics0: iic status register 0 if data is read from iics0 register, a wait cycle is generated. do not read data from iics0 register when the peripheral hardware clock (f prs ) is stopped. for details, see chapter 36 cautions for wait. p. 561 write to stcen bit only when the operation is stopped (iice0 = 0). p. 564 as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating the first start condition (stt0 = 1), it is necessary to verify that no third party co mmunications are in progress in order to prevent such communicati ons from being destroyed. p. 564 iicf0: iic flag register 0 write to iicrsv bit only when the operation is stopped (iice0 = 0). p. 564 selection clock setting determine the transfer clock frequency of i 2 c by using clx0, smc0, cl01, and cl00 before enabling the operation (by setting bit 7 (iice0) of iic control register 0 (iicc0) to 1). to change the transfer clock frequency, clear iice0 once to 0. p. 567 when stcen = 0 immediately after i 2 c operation is enabled (iice0 = 1), the bus communication status (iicbsy (bit 6 of iicf0) = 1) is recognized regardless of the actual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. ? set iic clock selection register 0 (iiccl0). ? set bit 7 (iice0) of iic control register 0 (iicc0) to 1. ? set bit 0 (spt0) of iicc0 to 1. p. 584 chapter 18 soft serial interface iic0 when stcen = 1 immediately after i 2 c operation is enabled (iice0 = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (stt0 (bit 1 of iic control r egister 0 (iicc0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. p. 584 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 965 jul 15, 2010 (22/30) chapter classification function details of f unction cautions page if other i 2 c communications are already in progress if i 2 c operation is enabled and the device partici pates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low ( detects a start condition). if the value on the bus at this time can be recognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. ? clear bit 4 (spie0) of iicc0 to 0 to disable generation of an interrupt request signal (intiic0) when the stop condition is detected. ? set bit 7 (iice0) of iicc0 to 1 to enable the operation of i 2 c. ? wait for detection of the start condition. ? set bit 6 (lrel0) of iicc0 to 1 before ack is returned (4 to 80 clocks after setting iice0 to 1), to forcibly disable detection. p. 584 transfer clock frequency setting determine the transfer clock frequency by us ing smc0, cl01, cl00 (bits 3, 1, and 0 of iicl0), and clx0 (bit 0 of iicx0) before enabling the operation (iice0 = 1). to change the transfer clock frequency, clear iice0 to 0 once. p. 584 stt0, spt0: bits 1, 0 of iic control register 0 (iicc0) setting stt0 and spt0 (bits 1 and 0 of iicc0) again after they are set and before they are cleared to 0 is prohibited. p. 585 chapter 18 soft serial interface iic0 transmission reserve when transmission is reserved, set spie0 (bit 4 of iicl0) to 1 so that an interrupt request is generated when the stop condition is detected. transfer is started when communication data is written to iic0 a fter the interrupt request is generated. unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. however, it is not necessary to set spie0 to 1 when msts0 (bit 7 of iics0) is detected by software. p. 585 ? do not use serial interface iic0 and t he multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface iic0 and the multiplier/divider. p. 621 the value read from sdr0 during operati on processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. p. 623 sdr0: remainder data register 0 sdr0 is reset when the operation is started (when dmue is set to 1). p. 623 mda0h is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (dmuc0) is set to 81h). p. 623 do not change the value of mda0 during operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. p. 623 mda0h, mda0l: multiplication/ division data register a0 the value read from mda0 during operation processing (while dmue is 1) is not guaranteed. p. 623 do not change the value of mdb0 during operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. p. 624 mdb0: multiplication/ division data register b0 do not clear mdb0 to 0000h in the division mode. if set, undefined operation results are stored in mda0 and sdr0. p. 624 if dmue is cleared to 0 during operati on processing (when dmue is 1), the operation result is not guaranteed. if the operation is completed while the clearing instruction is being executed, the operati on result is guaranteed, provided that the interrupt flag is set. p. 625 do not change the value of dmusel0 duri ng operation processing (while dmue is 1). if it is changed, undefined operation resu lts are stored in multiplication/division data register a0 (mda0) and remainder data register 0 (sdr0). p. 625 chapter 19 soft multiplier/ divider dmuc0: multiplier/divider control register 0 if dmue is cleared to 0 during operation processing (while dmue is 1), the operation processing is stopped. to execute the operation again, set multiplication/division data register a0 (m da0), multiplication/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and start the operation (by setting dmue to 1). p. 625 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 966 jul 15, 2010 (23/30) chapter classification function details of function cautions page when operating a timer, serial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. p. 637 when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1). w hen describing in c language, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the compiled assembler must be a 1-bit memo ry manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it bec omes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of anot her bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. ther efore, care must be exercised when using an 8-bit memory manipulation instruction in c language. p. 637 be sure to clear bits 2, 4 to 7 of if1l and bits 1 to 7 of if1h to 0. (78k0/kb2) p. 638 be sure to clear bits 6 and 7 of if 1l to 0 in the 38-pin and 44-pin products. be sure to clear bit 7 of if1l to 0 in the 48-pin products. p. 639 be sure to clear bits 1 to 7 of if1h to 0. (78k0/kc2) p. 639 be sure to clear bit 7 of 1f1l and bits 1 to 7 of if1h to 0. (78k0/kd2) p. 640 be sure to clear bits 1 to 7 of if1h to 0 for the products whose flash memory is less than 32 kb. be sure to clear bits 4 to 7 of if1h to 0 for the products whose flas h memory is at least 48 kb. (78k0/ke2) p. 641 1f0l, 1f0l, 1f1l, 1f1h: interrupt request flag registers be sure to clear bits 5 to 7 of if1h to 0. (78k0/kf2) p. 642 be sure to set bits 2, 4 to 7 of mk1l and bits 1 to 7 of mk1h to 1. (78k0/kb2) p. 643 be sure to set bits 6 and 7 of mk1l to 1 in the 38-pin and 44-pin products. be sure to set bit 7 of mk1l to 1 in the 48-pin products. be sure to set bits 1 to 7 of mk1h to 1. (78k0/kc2) p. 644 be sure to set bit 7 of mk1l and bits 1 to 7 of mk1h to 1. (78k0/kd2) p. 645 be sure to set bits 1 to 7 of mk1h to 1 for the products whose flash memory is less than 32 kb. be sure to set bits 4 to 7 of mk1h to 1 fo r the products whose flas h memory is at least 48 kb. (78k0/ke2) p. 646 mk0l, mk0h, mk1l, mk1h: interrupt mask flag registers be sure to set bits 5 to 7 of mk1h to 1. (78k0/kf2) p. 647 be sure to set bits 2, 4 to 7 of pr1l and bits 1 to 7 of pr1h to 1. (78k0/kb2) p. 648 be sure to set bits 6 and 7 of pr1l to 1 in the 38-pin and 44-pin products. be sure to set bit 7 of pr1l to 1 in the 48-pin products. be sure to set bits 1 to 7 of pr1h to 1. (78k0/kc2) p. 649 be sure to set bit 7 of pr1l and bits 1 to 7 of pr1h to 1. (78k0/kd2) p. 650 be sure to set bits 1 to 7 of pr1h to 1 for the products whose flash memory is less than 32 kb. be sure to set bits 4 to 7 of pr1h to 1 fo r the products whose flas h memory is at least 48 kb. (78k0/ke2) p. 651 chapter 20 soft interrupt function pr0l, pr0h, pr1l, pr1h: priority specification flag registers be sure to set bits 5 to 7 of pr1h to 1. (78k0/kf2) p. 652 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 967 jul 15, 2010 (24/30) chapter classification function details of function cautions page be sure to clear bits 6 and 7 of egp and egn to 0 in 78k0/kb2, and the 38-pin and 44-pin products of 78k0/kc2. be sure to clear bit 7 of egp and egn to 0 in 78k0/kd2, and the 48-pin products of 78k0/kc2. p. 653 egp, egn: external interrupt rising edge, falling edge enable registers select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. p. 654 software interrupt request do not use the reti instruction for restoring from the software interrupt. p. 658 chapter 20 soft interrupt function brk instruction the brk instruction is not one of the above-listed interrupt r equest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. p. 662 if any of the krmn bits used is set to 1, set bit n (pu7n) of the corresponding pull-up resistor register 7 (pu7) to 1. p. 665 if krm is changed, the interrupt request flag ma y be set. therefore, disable interrupts and then change the krm register. clear the interrupt request flag and enable interrupts. p. 665 the bits not used in the key interrupt mode can be used as normal ports. p. 665 chapter 21 soft key interrupt function krm: key return mode register for the 38-pin products of 78k0/kc2, be sure to set bits 2 to 7 of krm to ?0?. for the 44-pin and 48-pin products of 78k0/kc2, be sure to set bits 4 to 7 of krm to ?0?. p. 665 the stop mode can be used only when the cpu is operating on the main system clock. the subsystem clock oscillati on cannot be stopped. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. p. 666 when shifting to the stop mode, be sure to stop the peripheral hardware operation operating with main system clock before executing stop instruction. p. 666 standby function the following sequence is recommended for oper ating current reduction of the a/d converter when the standby func tion is used: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the stop instruction. p. 666 after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. p. 668 soft the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high- speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p. 668 hard ostc: oscillation stabilization time counter status register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p. 668 to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. p. 669 do not change the value of the osts register during the x1 clock oscillation stabilization time. p. 669 chapter 22 soft standby function osts: oscillation stabilization time select register the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high- speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p. 669 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 968 jul 15, 2010 (25/30) chapter classification function details of function cautions page hard osts: oscillation stabilization time select register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p. 669 because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if se t. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (osts) has elapsed. p. 674 to use the peripheral hardware that st ops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillating in the stop mode after the stop mode is released, re start the peripheral hardware. p. 676 even if ?internal low-speed oscillator can be stopped by software? is selected by the option byte, the internal low-speed oscillation clock continues in the stop mode in the status before the stop mode is set. to stop the internal low-speed oscillator?s oscillation in the stop mode, stop it by software and then execute the stop instruction. p. 676 to shorten oscillation stabilization time after the stop mode is released when the cpu operates with the high-speed system clo ck (x1 oscillation), switch the cpu clock to the internal highspeed oscillation clock before the execution of the stop instruction using the following procedure. <1> set rstop to 0 (starting oscillation of the internal high-speed oscillator) <2> set mcm0 to 0 (switching the cpu from x1 oscillation to internal high-speed oscillation) <3> check that mcs is 0 (checking the cpu clock) <4> check that rsts is 1 (checking internal high-speed oscillation operation) <5> execute the stop instruction before changing the cpu clock from the internal high-speed oscillation clock to the high-speed system clock (x1 oscillation) afte r the stop mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (ostc). p. 676 if the stop instruction is executed when amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is released when the internal high- speed oscillation clock is selected as the cpu clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the cpu clock. p. 676 chapter 22 soft standby function stop mode execute the stop instruction after havi ng confirmed that the internal high-speed oscillator is operating stably (rsts = 1). p. 676 for an external reset, input a low level for 10 s or more to the reset pin. p. 681 during reset input, the x1 clock, xt1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscilla ting. external main system clock input and external subsystem clock input become invalid. p. 681 ? when the stop mode is released by a reset, the stop mode contents are held during reset input. however, the port pi ns become high-impedance, except for p130, which is set to low-level output. p. 681 block diagram of reset function an lvi circuit internal reset does not reset the lvi circuit. p. 682 hard watchdog timer overflow a watchdog timer internal reset resets the watchdog timer. p. 684 chapter 23 soft reset function resf: reset control flag register do not read data by a 1-bit memory manipulation instruction. p. 691 if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. p. 692 chapter 24 soft power-on- clear circuit ? set the low-voltage detector by software after the reset status is released (see chapter 25 low-voltage detector). pp. 694, 695 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 969 jul 15, 2010 (26/30) chapter classification function details of function cautions page in 2.7 v/1.59 v poc mode a voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 v (typ.). if the supply voltage rises from 1.59 v (typ.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. p. 695 chapter 24 soft power-on- clear circuit cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certai n period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbi trarily set by taking the following action. p. 696 soft to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulati on instruction: write 00h to lvim. ? when using 1-bit memory manipulati on instruction: clear lvion to 0. p. 700 hard input voltage from external input pin (exlvi) must be exlvi < v dd . p. 700 lvim: low- voltage detection register when using lvi as an interrupt, if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generated and lviif becomes 1. p. 701 lvim and lvis with the convent ional-specificat ion products ( pd78f05xx and 78f05xxd), after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. p. 701 be sure to clear bits 4 to 7 to ?0?. p. 701 do not change the value of lvis during lvi operation. p. 701 when an input voltage from the external input pin (exlvi) is detected, the detection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefor e, setting of lvis is not necessary. p. 701 lvis: low- voltage detection level selection register with the conventional-s pecification products ( pd78f05xx and 78f05xxd), after an lvi reset has been generated, do not write values to lvis and lvim when lvion = 1. p. 701 <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. p. 703 when used as reset (when detecting level of supply voltage (v dd )) if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. p. 703 <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. p. 706 soft if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an internal reset signal is not generated. p. 706 when used as reset (when detecting level of input voltage from external input pin (exlvi)) input voltage from external input pin (exlvi) must be exlvi < v dd . p. 706 hard when used as interrupt (when detecting level of input voltage from external input pin (exlvi)) input voltage from external input pin (exlvi) must be exlvi < v dd . p. 711 chapter 25 soft low- voltage detector cautions for low- voltage detector in a system where the supply voltage (v dd ) fluctuates for a certai n period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be ar bitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generat ed. take (b) of action (2) below. p. 713 0082h, 0083h/ 1082h, 1083h be sure to set 00h to 0082h and 0083h (0082h/1082h and 0083h/1083h when the boot swap function is used). p. 716 chapter 26 soft option byte 0080h/1080h set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. p. 716 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 970 jul 15, 2010 (27/30) chapter classification function details of function cautions page 0081h/1081h pocmode can only be written by usi ng a dedicated flash memory programmer. it cannot be set during self-programming or boot swap operation during self- programming. however, because the val ue of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. p. 716 be sure to set 00h (disabling on-chip debug operation) to 0084h for products not equipped with the on-chip debug function ( pd78f05xx and 78f05xxa). also set 00h to 1084h because 0084h and 1084h are swit ched during the boot swap operation. p. 717 0084h/1084h to use the on-chip debug function with a product equipped with the on-chip debug function ( pd78f05xxd and 78f05xxda), set 02h or 03h to 0084h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h are switched during the boot swap operation. p. 717 the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. p. 718 setting window1 = window0 = 0 is prohi bited when using the watchdog timer at 1.8 v v dd < 2.7 v. p. 718 the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during proc essing, the interrupt acknowledge time is delayed. set the overflow time and window si ze taking this delay into consideration. p. 718 if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, regardless of the setting of bit 0 (lsrstop) of the internal oscillation mode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit time r h1 even in the halt/stop mode p. 718 0080h/1080h be sure to clear bit 7 to 0. p. 718 chapter 26 soft option byte 0081h/1081h be sure to clear bits 7 to 1 to ?0?. p. 719 be sure to set each product to the values shown in table 27-1 after a reset release. p. 721 be sure to set each product to the values show n in table 27-2 after a reset release. p. 722 ims: internal memory size switching register, ixs: internal expansion ram size switching register to set the memory size, set ims and then ixs. set the memory size so that the internal rom and internal expans ion ram areas do not overlap. pp. 721, 723 only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. p. 731 operation clock only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart6 is used. p. 731 processing of x1, p31 pins for the product with an on-chip debug function ( pd78f05xxd and 78f05xxda), connect p31/intp2/ocd1a and p121/x1/ocd0a as follows when writing the flash memory with a flash memory programmer. ? p31/intp2/ocd1a: connect to ev ss via a resistor. ? p121/x1/ocd0a: connect to v ss via a resistor. p. 731 soft selecting communication mode when uart6 is selected, the receive clo ck is calculated based on the reset command sent from the dedicated flash memory programmer after the flmd0 pulse has been received. p. 733 after the security setting for the batch eras e is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memo ry cannot be written, because the erase command is disabled. p. 735 chapter 27 hard flash memory security settings if a security setting that rewrites boot clus ter 0 has been applied, boot cluster 0 of that device will not be rewritten, and the device will not be erased in batch. p. 735 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 971 jul 15, 2010 (28/30) chapter classification function details of function cautions page e.p.v. command usage when executing boot swapping, do not use the e.p.v. command with the dedicated flash memory programmer. pp. 737, 738, 753 the self-programming function cannot be used when the cpu operates with the subsystem clock. p. 739 oscillation of the internal high-speed oscilla tor is started during self programming, regardless of the setting of the rstop flag (bit 0 of the internal oscillation mode register (rcm)). oscillation of the internal high-speed oscillator cannot be stopped even if the stop instruction is executed. p. 739 hard input a high level to the flmd0 pin during self-programming. p. 739 be sure to execute the di instruction before starting self-programming. the self-programming function checks the inte rrupt request flags (if0l, if0h, if1l, and if1h). if an interrupt request is generated, self-programming is stopped. p. 739 self-programming is also stopped by an interr upt request that is not masked even in the di status. to prevent this, mask the interr upt by using the interrupt mask flag registers (mk0l, mk0h, mk1l, and mk1h). p. 739 chapter 27 soft flash memory flash memory programming by self- programming allocate the entry program for self-programming in the common area of 0000h to 7fffh. p. 740 pd78f05xxd and 78f05xxda the pd78f05xxd and 78f05xxda have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. p. 756 input the clock from the ocd0a/x1 pin during on-chip debugging. p. 756 when ocd0a/x1 and ocd0b/x2 are used control the ocd0a/x1 and ocd0b/x2 pins by externally pulling down the ocd1a/p31 pin or by using an external circuit using the p130 pin (that outputs a low level when the device is reset). p. 756 chapter 28 hard on-chip debug function ( pd78f 05xxd and 78f05xx da only) when using the port that controls the flmd0 pin when using the port that controls the flmd0 pin, make sure that it satisfies the values of the high-level output current and flmd0 supply voltage (minimum value: 0.8v dd ) stated in chapter 30 electrical spec ifications (standard products) to chapter 33 electrical specificat ions ((a2) grade products: t a = ? 40 to +125 c). p. 757 pd78f05xxd and 78f05xxda the pd78f05xxd and 78f05xxda have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. p. 772 pp. 772, ? the pins mounted depend on the product. 774 to 777, 780 to 783, 785 to 802, 804 to 811, 813 to 830, 832 to 839, 841 to 859, 861 to 868, 870 to 887 chapters 30, 31, 32, 33 hard electrical specificati ons absolute maximum ratings product quality may suffer if the absol ute maximum rating is exceeded even momentarily for any parameter. that is, t he absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ens ure that the absolute maximum ratings are not exceeded. pp. 774, 775, 804, 805, 832, 833, 861, 862 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 972 jul 15, 2010 (29/30) chapter classification function details of function cautions page value of the current the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. pp. 775, 805, 833, 862 when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adv erse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. pp. 776, 806, 834, 863 x1 oscillator characteristics since the cpu is started by the internal high-speed oscillation clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. pp. 776, 806, 834, 863 when using the xt1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adv erse effect from wiring capacitance ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. pp. 777, 807, 835, 864 xt1 oscillator characteristics the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular care is therefore required wi th the wiring method when the xt1 clock is used. pp. 777, 807, 835, 864 chapters 30, 31, 32, 33 hard electrical specifications recommended oscillator constants the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implem entation circuit. the oscillation voltage and oscillation frequency only indicate the oscillator characteristic. use the 78k0/kx2 so that the internal operation condi tions are within the specifications of the dc and ac characteristics. pp. 778, 779 78k0/kx2 appendix d list of cautions r01uh0008ej0401 rev.4.01 973 jul 15, 2010 (30/30) chapter classification function details of function cautions page pd78f05xxd the pd78f05xxd has an on-chip debug func tion, which is provided for development and evaluation. do not us e the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be e xceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when t he on-chip debug function is used. pp. 912, 913 ? do not use different soldering methods together (except for partial heating). pp. 914, 916 chapter 35 hard recommended soldering conditions pd78f05xxda the pd78f05xxda has an on-chip debug func tion, which is provided for development and evaluation. do not us e the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be e xceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when t he on-chip debug function is used. pp. 915, 916 chapter 36 soft wait ? when the peripheral hardware clock (f prs ) is stopped, do not access the registers listed above using an access method in which a wait request is issued. p. 918 78k0/kx2 appendix e revision history r01uh0008ej0401 rev.4.01 974 jul 15, 2010 appendix e revision history e.1 major revisions in this edition page description classification r01uh0008ej0400 r01uh0008ej0401 pp. 97, 396, 399, 722, 723 deletion of note (c) p. 93 change of recommended connection of unused pins of flmd0 pin in table 2-3. pin i/o circuit types (a) p. 135 change of note 2 of table 3-8. special function register list (5/5) (c) u18598jj3v0ud00 r01uh0008ej0400 throughout deletion of " recommended " from caution " connect the regc pin to v ss via a capacitor (0.47 to 1 f: recommended). " (c) chapter 1 outline p. 41 change of status of 64-pin plastic fbga (4x4) of 78k0/ke2 from under development to mass production (b) chapter 2 pin functions p. 69 change of 2. 1. 3 78k0/kd2 (2) non-port functions: 78k0/kd2 (c) pp. 72, 73 change of 2. 1. 4 78k0/ke2 (2) non-port functions: 78k0/ke2 (c) p. 93 change of table 2-3. pin i/o circuit types (3/3) (c) chapter 6 clock generator p. 230 change of caution 2 in figure 6-3. format of clock operatio n mode select register (oscctl) (78k0/kb2) (a) p. 231 change of caution 2 in figure 6-4. format of clock operatio n mode select register (oscctl) (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) (a) p. 259 change of figure 6-18. cpu clock status transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0), 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) (c) chapter 7 16-bit timer/event counters 00 and 01 p. 299 change of caution in 7.4.4 operation in clear & start mode entered by ti00n pin valid edge input (c) chapter 18 serial interface iic0 p. 553 addition of caution to figure 18-3. format of iic shift register 0 (iic0) (c) p. 553 change of description of 18.2 (2) slave address register 0 (sva0) (c) p. 557 addition of note to figure 18-5. format of iic control register 0 (iicc0) (1/4) and change of caution (c) p. 559 change of figure 18-5. format of iic control register 0 (iicc0) (3/4) (c) p. 560 change of figure 18-5. format of iic control register 0 (iicc0) (4/4) (c) p. 562 change of figure 18-6. format of iic status register 0 (iics0) (2/3) (c) chapter 20 interrupt functions p. 634 change of (c) external maskable interrupt (intkr) in figure 20-1 basic configuration of interrupt function (c) chapter 22 standby function p. 673 addition of note to figure 22-4. halt mode release by reset (c) p. 680 addition of note to figure 22-7. stop mode release by reset (c) chapter 27 flash memory p. 730 change of description of 27.6.5 regc pin (c) p. 755 addition of 27.11 creating rom code to place order for previously written product (c) appendix e revision history p. 975 addition of c.2 revision history of preceding editions (c) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): addition/ change of specifications, (c): additi on/change of description or note, (d): addition/change of package, part number, or managem ent division, (e): addition/change of related documents 78k0/kx2 appendix e revision history r01uh0008ej0401 rev.4.01 975 jul 15, 2010 e.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/4) edition description chapter addition of the conventional -specification products ( pd78f05xx, 78f05xx(a), 78f05xx(a2)) addition of the (a2) grade products of expanded-specification products ( pd78f05xxa(a2)) addition of the 64-pin pl astic fbga (4x4) package addition of sm+ tor 78k0 deletion of qb-78k0mini, pg-fpl3, and fp-lite3 (because of discontinued products) throughout addition of differences between conventional-specification products and expanded-specification products modification of related documents introduction addition of 1.1 differences between conventional-specification products ( pd78f05xx and 78f05xxd) and expanded-specification products ( pd78f05xxa and 78f05xxda) modification of 1.4 ordering information modification of 1.8 outline of functions chapter 1 outline modification of table 3-1 set values of internal memory size switching register (ims) (78k0/kb2, and 38-pin products and 44-pin products of the 78k0/kc2) and table 3-2 set values of internal memory size switching register (ims) and internal expansion ram size switching register (ixs) (48-pin products of the 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) addition of description in 3.2.1 (2) program status word (psw) modification of notes 2 to 4 in table 3-8 special function register list (5/5) chapter 3 cpu architecture addition of caution 2 to 5.2.2 port 1 modification of caution in figure 5-17 block diagram of p60 and p61 and figure 5-18 block diagram of p62 chapter 5 port functions addition of caution 2 to figure 6-3. format of clock operation mode select register (oscctl) (78k0/kb2) and figure 6-4 format of clock operation mode select register (oscctl) (78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) modification of note 1 in and addition of note 2 to figure 6-15 clock generator operation when power supply voltage is turned on (when 1.59 v poc mode is set (option byte: pocmode = 0)) addition of note to figure 6-17 cpu clock status transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0), 78k0/kb2) and figure 6-18 cpu clock status transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0), 78k0/kc2, 78k0/kd2, 78k0/ke2, and 78k0/kf2) chapter 6 clock generator modification of note 1 in and addition of note 3 to figure 7-13 format of prescaler mode register 00 (prm00) and figure 7-14 format of prescaler mode register 01 (prm01) 3nd edition modification of description in (f) 16-bit capture/compare register 00n (cr00n) in figure 7-46 example of register settings for ppg output operation (2/2) chapter 7 16-bit timer/event counters 00 and 01 78k0/kx2 appendix e revision history r01uh0008ej0401 rev.4.01 976 jul 15, 2010 (2/4) edition description chapter modification of note 1 in and addition of note 4 to figure 8-5 format of timer clock selection register 50 (tcl50) and figure 8-6 format of timer clock selection register 51 (tcl51) chapter 8 8-bit timer/event counters 50 and 51 modification of note 1 in and addition of note 3 to figure 9-5 format of 8-bit timer h mode register 0 (tmhmd0) and figure 9-6 format of 8-bit timer h mode register 1 (tmhmd1) chapter 9 8-bit timers h0 and h1 addition of note to figure 10-2 format of watch timer operation mode register (wtm) chapter 10 watch timer modification of note and description in 11.1 functions of watchdog timer modification of note and description in 11.4.1 controlling operation of watchdog timer modification of remark in 11.4.3 setting window open period of watchdog timer chapter 11 watchdog timer modification of note 1 in figure 12-3 format of clock output selection register (cks) (78k0/kd2, 48-pin products of 78k0/kc2) and figure 12-4 format of clock output selection register (cks) (78k0/ke2, 78k0/kf2) chapter 12 clock output/buzzer output controller addition of table 13-2 a/d conversion time selection (conventional- specification products ( pd78f05xx and 78f05xxd)) modification of table 13-3 a/d conversion time selection (expanded- specification products ( pd78f05xxa and 78f05xxda)) modification of figure 13-6 format of 10-bit a/d conversion result register (adcr) chapter 13 a/d converter modification of note 1 in figure 14-4 format of baud rate generator control register 0 (brgc0) modification of note 1 in table 14-4 set value of tps01 and tps00 modification of table 14-5 set data of baud rate generator chapter 14 serial interface uart0 modification of note 1 in figure 15-5 format of asynchronous serial interface operation mode register 6 (asim6) (1/2) modification of note 1 in and addition of note 3 to figure 15-8 format of clock selection register 6 (cksr6) addition of caution 8 to figure 15-10 format of asynchronous serial interface control register 6 (asicl6) (2/2) modification of note 1 in 15.4.1 (1) register used modification of note 1 in and addition of note 3 to table 15-4 set value of tps63 to tps60 chapter 15 serial interface uart6 modification of notes 1 and 2 in figure 16-5 format of serial clock selection register 10 (csic10) and figure 16-6 format of serial clock selection register 11 (csic11) addition of note 2 in and modification of table 16-2 relationship between register settings and pins 3nd edition modification of 16.4.2 (5) so1n output chapter 16 serial interfaces csi10 and csi11 78k0/kx2 appendix e revision history r01uh0008ej0401 rev.4.01 977 jul 15, 2010 (3/4) edition description chapter addition of notes 2 and 5 to and modification of note 3 in figure 17-3 format of serial status register 0 (csis0) (1/2) modification of note in figure 17-5 format of divisor selection register 0 (brgca0) chapter 17 serial interface csia0 addition of note 1 to table 18-2 selection clock setting modification of table 18-4 bit definitions of main extension code modification of figure 18-27 example of master to slave communication and figure 18-28 example of slave to master communication chapter 18 serial interface iic0 modification of note 1 in figure 22-3 halt mode release by interrupt request generation addition of caution 5 to table 22-3 operating statuses in stop mode modification of note 2 in figure 22-5 operation timing when stop mode is released (when unmasked interrupt request is generated) modification of note in figure 22-6 stop mode release by interrupt request generation chapter 22 standby function modification of figure 23-1 block diagram of reset function modification of notes 3 and 4 in table 23-2 hardware statuses after reset acknowledgment (1/4) chapter 23 reset function modification of figure 24-1 block diagram of power-on-clear circuit modification of notes 1 and 2 in and addition of note 3 to figure 24-2 timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector (1/2) modification of note 1 in figure 24-2 timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector (2/2) chapter 24 power- on-clear circuit addition of note to 25.1 functions of low-voltage detector modification of note 4 in and addition of caution 4 in figure 25-2 format of low- voltage detection register (lvim) addition of note 2 and caution 4 to figure 25-3 format of low-voltage detection level selection register (lvis) modification of figure 25-9 example of software processing after reset release chapter 25 low- voltage detector modification of caution in 26.1 (2) 0081h/1081h modification of note 1 in ? address: 0081h/1081h ? in figure 26-1 format of option byte (2/2) chapter 26 option byte modification of table 27-1 internal memory size switching register settings modification of caution 2 in 27.2 internal expansion ram size switching register modification of table 27-2 internal expansion ram size switching register settings modification of caution in 27.8 security settings addition of table 27-13 processing time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) addition of table 27-15. interrupt response time for self programming library (conventional-specification products ( pd78f05xx and 78f05xxd)) chapter 27 flash memory modification of caution in 28.1 connecting qb-mini2 to pd78f0503d and 78f0503da 3rd edition addition of caution in figure 28-3 connection of flmd0 pin for self programming by means of on-chip debugging chapter 28 on- chip debug function ( pd78f0503d and 78f0503da only) 78k0/kx2 appendix e revision history r01uh0008ej0401 rev.4.01 978 jul 15, 2010 (4/4) edition description chapter revision of this chapter chapter 30 electrical specifications (standard products) revision of this chapter chapter 31 electrical specifications ((a) grade products) addition of this chapter chapter 32 electrical specifications ((a2) grade products: t a = ? 40 to +110 c) addition of this chapter chapter 33 electrical specifications ((a2) grade products: t a = ? 40 to +125 c) revision of this chapter chapter 35 recommended soldering conditions revision of this chapter appendix a development tools 3rd edition addition of this chapter appendix e revision history [memo] 78k0/kx2 user?s manual: hardware publication date: rev.0.01 january 10, 2008 rev.4.01 july 15, 2010 published by: renesas electronics corporation http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2010 renesas electronics corporation. all rights reserved. colophon 1.0 78k0 / kx2 r01uh0008ej0401 (previous number: u18598ej3v0ud00) |
Price & Availability of UPD78F0511AGA-GAM-AX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |